DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on May 27, 2026 has been entered.
Response to Arguments
Applicant’s arguments, see pages 1-4 in the Remarks, filed May 27, 2026, with respect to the rejection of claims 1-7, 9-15, and 17-23 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Paluru et al (US Publication 2024/0248782 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-15, and 17-27 are rejected under 35 U.S.C. 103 as being unpatentable over Friedman et al (US Publication 2023/0196458 A1) in view of Paluru et al (US Publication 2024/248782 A1).
Regarding to claims 1 and 20, Friedman discloses an apparatus 400 (fig. 4) comprising: a network interface receiver 404 configured to receive a plurality of packets (pages 6-7 paragraph 0084); an electronic circuit 408 statically configured in hardware to extract a header of each received packet (page 7 paragraph 0087), evaluate each extracted header based on an access control ruleset (page 7 paragraph 0088; filter rules), and, based on the evaluation, pass a first portion of the received packets and discard a second portion of the received packets (page 7 paragraphs 0089-0090); and a network interface transmitter 406 configured to transmit the first portion of the received packets (page 9 paragraph 0115).
Friedman fails to teach for the access control ruleset is statically preconfigured in hardware and predefined.
However, Paluru discloses a switch 102 (fig. 1) employing access control lists ACLs, wherein the ACLs are statically (page 2 paragraph 0026) preconfigured in hardware (page 2 paragraph 0020) and predefined (page 2 paragraph 0017).
Thus, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange for ACLs statically preconfigured in hardware as taught by Paluru into Friedman's system for providing insights, analytics, and monitoring of the criticality of applications impacted by link failures.
Regarding to claim 2, Friedman discloses a housing 400 enclosing the network interface receiver, the electronic circuit, and the network interface transmitter, wherein the housing has a height of less than 10 mm, a width of less than 15 mm, and a length of less than 60 mm (page 7 paragraph 0085; noted the FPGA 400 include small form-factor housing supporting the measurements).
Regarding to claim 3, Friedman discloses the electronic circuit 408 comprises an application-specific integrated circuit (page 6 paragraph 0080).
Regarding to claim 4, Friedman discloses the electronic circuit 408 comprises a field-programmable gate array (page 6 paragraph 0080).
Regarding to claim 5, Friedman discloses the network interface receiver 404 comprises an electrical network interface receiver (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception) and the network interface transmitter 406 comprises an optical network interface transmitter (pages 6-7 paragraph 0084-0085; noted the network interfaces 404-406 includes physical layer module supporting gigabit Ethernet, which used optical fiber).
Regarding to claim 6, Friedman discloses the network interface receiver 404 comprises an optical network interface receiver (pages 6-7 paragraph 0084-0085; noted the network interfaces 404-406 includes physical layer module supporting gigabit Ethernet, which used optical fiber) and the network interface transmitter 406 comprises an electrical network interface transmitter (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception).
Regarding to claim 7, Friedman discloses the network interface receiver 404 comprises an electrical network interface receiver and the network interface transmitter 406 comprises an electrical network interface transmitter (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception).
Regarding to claim 9, Friedman discloses the electronic circuit 408 is further statically configured in hardware to take account of a volume of packets of a predetermined type in the evaluation (pages 4-5 paragraph 0053).
Regarding to claim 10, Friedman discloses an assembly 400 (fig. 4) for connection to an upstream network 104 (page 6 paragraph 0072), the assembly comprising: a small form-factor pluggable module (page 7 paragraph 0085) comprising: a network interface receiver 404 configured to receive a plurality of packets from the upstream network 104 pages 6-7 paragraph 0084); an electronic circuit 408 statically configured in hardware to extract a header of each received packet (page 7 paragraph 0087), evaluate each extracted header based on an access control ruleset (page 7 paragraph 0088; filter rules), and, based on the evaluation, pass a first portion of the received packets and discard a second portion of the received packets (page 7 paragraphs 0089-0090); a network interface transmitter 406 configured to transmit the first portion of the received packets (page 9 paragraph 0115); and a protected device 102 (fig. 1) coupled to the network interface transmitter 406 (page 3 paragraph 0036)
Friedman fails to teach for the access control ruleset is statically preconfigured in hardware and predefined.
However, Paluru discloses a switch 102 (fig. 1) employing access control lists ACLs, wherein the ACLs are statically (page 2 paragraph 0026) preconfigured in hardware (page 2 paragraph 0020) and predefined (page 2 paragraph 0017).
Thus, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange for ACLs statically preconfigured in hardware as taught by Paluru into Friedman's system for providing insights, analytics, and monitoring of the criticality of applications impacted by link failures.
Regarding to claim 12, Friedman discloses the electronic circuit 408 comprises an application-specific integrated circuit (page 6 paragraph 0080).
Regarding to claim 13, Friedman discloses the electronic circuit 408 comprises a field-programmable gate array (page 6 paragraph 0080).
Regarding to claim 14, the network interface receiver 404 comprises an electrical network interface receiver; the network interface transmitter 406 comprises an electrical network interface transmitter (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception); the network interface receiver 404 is coupled to the upstream network 104 with an electrical connector (pages 6-7 paragraph 0084; ports); and the network interface transmitter 406 is coupled to the protected device 420 with an electrical connector (pages 6-7 paragraph 0084; ports).
Regarding to claim 15, the network interface receiver 404 comprises an optical network interface receiver (pages 6- 7 paragraph 0084-0085; noted the network interfaces 404-406 includes physical layer module supporting gigabit Ethernet, which used optical fiber); the network interface transmitter 406 comprises an electrical network interface transmitter (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception); the network interface receiver 404 is coupled to the upstream network 104 with an optical connector (pages 6-7 paragraph 0084; ports); and the network interface transmitter 406 is coupled to the protected device 420 with an electrical connector (pages 6-7 paragraph 0084; ports).
Regarding to claim 17, Friedman discloses the electronic circuit 408 is further statically configured in hardware to take account of a volume of packets of a predetermined type in the evaluation (pages 4-5 paragraph 0053).
Regarding to claim 18, Friedman discloses a trusted network 104 (fig. 4) for connection to upstream (page 6 paragraph 0072) untrusted network 402, the trusted network comprising: a plurality of small form-factor pluggable modules (page 7 paragraph 0085) comprising: a network interface receiver 404 configured to receive a plurality of packets from the upstream network (pages 6-7 paragraph 0084); an electronic circuit 408 statically configured in hardware to extract a header of each received packet (page 7 paragraph 0087), evaluate each extracted header based on an access control ruleset (page 7 paragraph 0088; filter rules), and, based on the evaluation, pass a first portion of the received packets and discard a second portion of the received packets (page 7 paragraphs 0089-0090); a network interface transmitter 406 configured to transmit the first portion of the received packets (page 9 paragraph 0115); and a plurality of protected devices 102 (fig. 1), within the trusted network 104, and coupled to the network interface transmitter 406 of the plurality of small form-factor pluggable modules (page 3 paragraph 0036).
Friedman fails to teach for the access control ruleset is statically preconfigured in hardware and predefined.
However, Paluru discloses a switch 102 (fig. 1) employing access control lists ACLs, wherein the ACLs are statically (page 2 paragraph 0026) preconfigured in hardware (page 2 paragraph 0020) and predefined (page 2 paragraph 0017).
Thus, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange for ACLs statically preconfigured in hardware as taught by Paluru into Friedman's system for providing insights, analytics, and monitoring of the criticality of applications impacted by link failures.
Regarding to claim 19, Friedman discloses at least one of the plurality of connected devices comprises a router 202 (fig. 2 page 5 paragraph 0056) and at least another one of the plurality of connected devices comprises a customer premises equipment CPE unit 102(page 3 paragraph 0036).
Regarding to claim 21, Friedman discloses the receiving step is carried out at no more than 10 Gbps (page 7 paragraph 0084).
Regarding to claim 22, Friedman discloses the receiving is carried out using an optical connector pages 6-7 paragraph 0084-0085; noted the network interfaces 404-406 includes physical layer module supporting gigabit Ethernet, which used optical fiber) and the passing is carried out using an electrical connector transmitter (page 7 paragraph 0085; noted the network interfaces 404-406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception)
Regarding to claim 23, Friedman discloses the receiving is carried out using an electrical connector and the passing is carried out using an electrical connector transmitter (page 7 paragraph 0085; noted the network interfaces 404- 406 includes physical layer module and physical coding sub-layer PCS module, which provide electrical transmission/reception).
Regarding to claims 24-27, Paluru discloses statically configured in hardware to take account of a volume of packets of a predetermined type (page 2 paragraph 0023) in the evaluation (page 3 paragraph 0029).
Allowable Subject Matter
Claims 8 and 16 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Duc T Duong whose telephone number is (571)272-3122. The examiner can normally be reached Mon-Fri; 9am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hassan Phillips can be reached at (571)272-3940. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUC T DUONG/Primary Examiner, Art Unit 2467
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