DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW 111143783, filed on 11/16/2022. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/24/2023 and 12/22/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 11323082 by Huang et al.
Regarding claim 1, Huang teaches a Class-D amplifier (Abstract), comprising:
a loop filter circuit (Fig. 1, 4 #101, 103) configured to generate a first signal according to a first input signal (V_ip) and a first output signal (V_op), generate a second signal according to a second input signal (V_in) and a second output signal (V_on), and adjust a common-mode level of each of the first signal and the second signal according to a first common-mode signal (Fig. 1, 4 signal FS; Col. 2 lines 33-40);
a comparator circuitry (Fig. 1, 4, 6 #105, 603) configured to compare the first signal with a ramp signal (Signal Tr) to generate a first pulse signal (PW_p), and compare the second signal with the ramp signal to generate a second pulse signal (PW_n), wherein a common-mode level of the ramp signal is set based on a second common-mode signal (Fig. 6, Fig. 8 signal FS being combined with V_cmi to generate signal V_cm which eventually becomes signal Tr; Col. 4 lines 44-50);
an output circuitry (Fig. 1, 4, 6 #107, 605) configured to be powered by a power supply voltage (PVdd) to generate the first output signal (V_op) according to the first pulse signal (PW_p) and to generate the second output signal (V_on) according to the second pulse signal (PW_n); and
a common-mode control circuitry (Fig. 4 #109, Fig. 6, 8 #607, 609) configured to perform an AC-coupling operation on the power supply voltage to generate a first noise signal (Fig. 4, 8 signal output from C_HP) and generate a first one of the first common-mode signal (FS signal) and the second common-mode signal according to the first noise signal and a second one of the first common-mode signal and the second common-mode signal (The common mode control circuitry is used to produce the FS signal and the Tr signal as shown in different figures of Huang. Col. 5 lines 41-49. It would be obvious to a person of ordinary skill in the art to combine the different embodiments of Huang to achieve the claimed invention).
Regarding claim 2, Huang teaches the Class-D amplifier of claim 1, wherein the common-mode control circuitry is configured to suppress a DC frequency component in the power supply voltage to generate the first noise signal (Fig. 4, 8 C_HP blocks DC frequency component).
Regarding claim 10, Huang teaches the Class-D amplifier of claim 1, wherein the comparator circuitry comprises a plurality of comparator circuits, the plurality of comparator circuits respectively generate the first pulse signal and the second pulse signal, and a negative input terminal of each of the plurality of comparator circuits receives the ramp signal (Fig. 4 CM_1 and CM_2).
Regarding claim 11, Huang teaches the Class-D amplifier of claim 1, further comprising:
a ramp wave generator circuit (Fig. 8 #611) configured to generate the ramp signal (Tr) and adjust the common-mode level of the ramp signal according to the second common-mode signal (V_cm).
Regarding claim 12, Huang teaches the Class-D amplifier of claim 1, wherein the loop filter circuit is configured to generate the first signal according to a difference between the first input signal and the first output signal, and generate the second signal according to a difference between the second input signal and the second output signal (Fig. 1, 4, 8 feedback path P_1 and P_2 feed the output signal back to the input and combine with V_ip and V_in to generate the first and second signal that is then fed into OP_1).
Regarding claim 13, Huang teaches the Class-D amplifier of claim 1, wherein the comparator circuitry (Fig. 3 #105) is configured to generate the first pulse signal (PW_p) and the second pulse signal (PW_n) that each have a correction signal component in response to the first one of the first common-mode signal and the second common-mode signal, in order to reduce an impact from a power noise in the power supply voltage on the first output signal and the second output signal (Col. 4 lines 4-20).
Regarding claim 14, Huang teaches the Class-D amplifier of claim 1, wherein the comparator circuitry (Fig. 3, 4 #105, Fig. 8 #103)) comprises:
a first comparator circuit (CM_1) configured to compare the first signal with the ramp signal (Tr signal) to generate the first pulse signal (PW_p); and
a second comparator circuit (CM_2) configured to compare the second signal with the ramp signal (Tr signal) to generate the second pulse signal (PW_n).
Regarding claim 15, Huang teaches the class-D amplifier of claim 1, but doesn’t specify what type of circuitry is in the output circuit, only that it can be well known circuitry (Par. 15).
However, a first driver circuit and a second driver circuit that are powered by a power supply voltage and generate first and second output signals based on first and second pulse signals respectively are well known in the art, as shown in fig. 1 of US 20220278658 by Lesso et al.
Allowable Subject Matter
Claims 3-9 and 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843