Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application on 7 January 2026 after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed 23 October 2025 has been entered.
Response to Amendment
The Amendment filed 23 October 2025 has been entered. Claims 1-6, 8-13, and 15-20 remain pending in the application. Examiner acknowledges applicant’s amendments to the claims, and amended claims 1-6, 8-13, and 15-20 are rejected under 35 U.S.C. 103 following further search and consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 8-12, 15-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al (U.S. Patent Pub. No. 2019/0205043) in view of Wu et al (U.S. Patent Pub. No. 2020/0110697), hereinafter referred to as Wu, and Ko (U.S. Patent Pub. No. 2019/0377514).
In regard to claim 1, Huang et al teaches a system comprising: a memory device comprising a plurality of management units (Huang et al, Paragraph 0028, lines 1-2 disclose a memory controller 115 coupled to a memory array 120 (Fig. 1) which can implement superblocks in the flash translation layer. Superblocks are known according to the instant application and prior art as being equivalent to the claimed “management units”), each management unit comprising a plurality of blocks (Huang et al, Paragraph 0028, lines 2-5 explain superblocks as comprising a set of blocks across multiple planes and die of a memory array), and a processing device, operatively coupled with the memory device (Huang et al Fig. 1, memory controller 115). The system of Huang et al is capable of identifying, within the plurality of management units, a plurality of complete management units and a plurality of incomplete management units (Huang et al, Paragraph 0030, lines 1-5 explain the process of determining “partial” (incomplete) superblocks, and Paragraph 0032, lines 5-7 explain that non-partial (complete) superblocks are established as well), wherein a complete management unit of the plurality of complete management units comprises at least a predefined minimum number of blocks, (Huang et al Paragraph 0028, lines 1-7 disclose defining superblocks as including one block from each plane of each die of a memory device; this disclosure occurs before defining the structure of partial superblocks in Huang et al, meaning it implies a complete superblock must have at least that number of blocks). Huang et al also teaches performing a first operation using one or more complete management units from the plurality of complete management units as well as performing a second operation using one or more incomplete management units from the plurality of incomplete management units. These first and second operations are interpreted as non-sequential as explained in the instant application where the order of the claimed process can be changed unless specified. Huang et al, Paragraph 0049, lines 3-6 explain the use for complete (traditional) and incomplete (partial) management units (superblocks). Huang et al establishes exclusively using complete management units for specific data types (e.g. user data, SLC cache, etc.) while incomplete management units are used for storing other data (firmware code, first level translation table, etc.). Huang et al also teaches this system wherein the second operation comprises writing, to one or more incomplete management units, metadata associated with data stored in complete management units. Huang et al, Paragraph 0033, lines 4-8 explain using incomplete management units exclusively for data such as logical-to-physical (L2P) mapping of data stored in complete management units (Partial superblocks are disclosed in Huang et al as storing "at least one" type of data (meaning partial superblocks can be used to exclusively store a single type of data e.g. page tables, etc.) which could be logical to physical mapping. If partial superblocks only store logical to physical mapping data like first level translation tables (Huang Paragraph 0033, lines 7-10), then the mapping data must be directed to data stored elsewhere, which in the disclosure of Huang must be complete superblocks as the storage device is accessed and modified using said superblocks (superblocks are used to access all planes and dies of a memory device, Huang Paragraph 0028, lines 1-5).
Huang et al does not explicitly teach an embodiment wherein the pre-defined minimum number is determined based on a maximum number of parallel memory access operations performable on the memory device. However, Wu teaches a system including a plurality of channels used individually for parallel access (Fig. 1; ¶ 0019) wherein a complete super block spans one block per memory channel (¶ 0021), meaning a person of ordinary skill implementing the disclosure would determine a minimum number of blocks in a complete superblock based on a maximum number of channels (i.e. parallel memory access operations performable) on the device. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Wu in order to maximize parallel accesses and "simplify flash memory management and fully leverage [a] multi-channel architecture" (¶ 0020, lines 1-3).
The previously cited references do not explicitly teach remapping incomplete super blocks as claimed, however Ko teaches a memory management method including super blocks having multiple blocks (¶ 0009, lines 1-9) wherein one or more blocks from a first incomplete management unit of the plurality of incomplete management units is remapped to a second incomplete management unit of the plurality of incomplete management units (¶ 0070, lines 1-5 disclose that super physical units (management units) are grouped as good and partial good (complete and incomplete management units); line 8 and remaining text discloses remapping physical units between incomplete management units), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ko in order to decrease the probability of having bad erase units in management units and improve the service life of memory (¶ 0012).
As for claim 2, Huang et al discloses a memory system wherein each incomplete management unit comprises fewer than a threshold number of unusable blocks. Huang et al, Paragraph 0031, lines 1-3 disclose that partial superblocks “have a minimum number of planes with a good block in the same position”, which is equivalent to comprising fewer than a threshold number of unusable blocks. Therefore, the recited limitation was clearly anticipated by Huang et al.
As for claim 3, Huang et al discloses performing the first operation exclusively on complete management units. Huang et al, Paragraph 0049, lines 3-6 explain the use for complete (traditional) and incomplete (partial) superblocks (management units). Huang et al establishes exclusively using complete management units for specific data types (e.g. user data, SLC cache, etc.) while incomplete management units are used for storing other data (firmware code, first level translation table, etc.). Therefore, the recited limitation was clearly anticipated by Huang et al.
As for claim 4, Huang et al teaches receiving host data from a host device (Huang et al, Paragraph 0027, lines 1-5 describe receiving instructions from a host) and writing the host data to one or more complete management units. Huang et al, Paragraph 0027, lines 1-5 disclose that the memory controller 115 of Fig. 1 can write to or erase data from the memory array 120. Huang et al, Paragraph 0032, lines 5-7 disclose establishing complete superblocks, followed later by Paragraph 0049, lines 3-6 which detail using complete superblocks for varying types of data. Therefore, the recited limitations were clearly anticipated by Huang et al.
As for claim 5, Applicant is directed to the rejection of claim 3 set forth above, as it addresses the limitation of claim 5, which is rejected on the same rationale mentioned.
As for claim 8, Applicant is directed to the rejection of claim 1 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 9, Applicant is directed to the rejection of claim 2 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 10, Applicant is directed to the rejection of claim 3 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 11, Applicant is directed to the rejection of claim 4 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 12, Applicant is directed to the rejection of claim 5 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 14, Applicant is directed to the rejection of claim 7 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 15, Huang et al teaches a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations (Huang et al, Paragraph 0028, lines 1-2 disclose a memory controller 115 coupled to a memory array 120 (Fig. 1) which can implement superblocks in the flash translation layer). The device of Huang et al is capable of identifying, within the plurality of management units, a plurality of complete management units and a plurality of incomplete management units (Huang et al, Paragraph 0030, lines 1-5 explain the process of determining “partial” (incomplete) superblocks, and Paragraph 0032, lines 5-7 explain that non-partial (complete) superblocks are established as well), wherein a complete management unit of the plurality of complete management units comprises at least a predefined minimum number of blocks (Huang et al Paragraph 0028, lines 1-7 disclose defining superblocks as including one block from each plane of each die of a memory device; this disclosure occurs before defining the structure of partial superblocks in Huang et al, meaning it implies a complete superblock must have at least that number of blocks). Huang et al teaches performing a first operation using one or more complete management units from the plurality of complete management units wherein each block of each of the one or more complete management units is usable (Huang et al establishes complete superblocks as those with no bad blocks as partial superblocks have at least one bad block, Paragraph 0030, lines 1-5) as well as performing a second operation using one or more incomplete management units from the plurality of incomplete management units. These first and second operations are interpreted as non-sequential as explained in the instant application where the order of the claimed process can be changed unless specified. Huang et al, Paragraph 0049, lines 3-6 explain the use for complete (traditional) and incomplete (partial) management units (superblocks). Huang et al establishes exclusively using complete management units for specific data types (e.g. user data, SLC cache, etc.) while incomplete management units are used for storing other data (firmware code, first level translation table, etc.). Huang et al also teaches an example where each incomplete management unit comprises more than a predefined maximum number of unusable blocks. Huang et al, Paragraph 0045, lines 11-17 describe the possibility of forming a partial superblock using only a single unusable block on one plane as well as omitting a block from every plane to form the partial superblock, among other specified embodiments. The limitation of "more than a predefined maximum number" can be interpreted as a partial superblock having more than any previously set or discussed maximum number of bad blocks. In the case of Huang, a "predefined maximum" could be a single bad block as discussed, and partial superblocks could be formed using a larger number of bad blocks as is also discussed. Huang Paragraph 0046, lines 9-11 also disclose not forming superblocks having too many bad blocks, meaning the disclosure is capable of determining some predefined maximum number of bad blocks.
Huang et al does not explicitly teach an embodiment wherein the pre-defined minimum number is determined based on a maximum number of parallel memory access operations performable on the memory device. However, Wu teaches a system including a plurality of channels used individually for parallel access (Fig. 1; ¶ 0019) wherein a complete super block spans one block per memory channel (¶ 0021), meaning a person of ordinary skill implementing the disclosure would determine a minimum number of blocks in a complete superblock based on a maximum number of channels (i.e. parallel memory access operations performable) on the device. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Wu in order to maximize parallel accesses and "simplify flash memory management and fully leverage [a] multi-channel architecture" (¶ 0020, lines 1-3).
The previously cited references do not explicitly teach remapping incomplete super blocks as claimed, however Ko teaches a memory management method including super blocks having multiple blocks (¶ 0009, lines 1-9) wherein one or more blocks from a first incomplete management unit of the plurality of incomplete management units is remapped to a second incomplete management unit of the plurality of incomplete management units (¶ 0070, lines 1-5 disclose that super physical units (management units) are grouped as good and partial good (complete and incomplete management units); line 8 and remaining text discloses remapping physical units between incomplete management units), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Ko in order to decrease the probability of having bad erase units in management units and improve the service life of memory (¶ 0012).
As for claim 16, Applicant is directed to the rejection of claim 3 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 17, Applicant is directed to the rejection of claim 4 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 18, Applicant is directed to the rejection of the final clause of claim 1 set forth above, as they are directed to the same limitation and therefore rejected based on the same rationale.
As for claim 20, Applicant is directed to the rejection of claim 3 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
Claims 6, 13, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al in view of Wu, Ko, and Sinclair (U.S. Patent Pub. No. 2005/0144367).
In regard to claim 6, the previously cited references teach the system of claim 1. Huang et al does not teach the second operation comprises performing a media management operation comprising writing, to one or more incomplete management units, valid data copied from one or more complete management units. However, Sinclair teaches filling incomplete or reduced size metablocks (e.g. management units, superblocks, etc.) using data copied from original complete metablocks (Sinclair Paragraph 0247, lines 4-10). Sinclair’s disclosure aims to “reduce the effects of logical fragmentation” by configuring metablocks according to their data (Sinclair Paragraph 0016, lines 7-8). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Sinclair with those of Huang et al in order to “reduce the effects of logical fragmentation” (Sinclair Paragraph 0016, line 8).
As for claim 13, Applicant is directed to the rejection of claim 6 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
As for claim 19, Applicant is directed to the rejection of claim 6 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
Response to Arguments
Applicant’s arguments filed 18 September, 2025 (starting page 6 of response) with respect to the rejections of amended claims 1-5, 6-13, and 15-20 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Ko, which teaches the added limitation wherein blocks are remapped from one incomplete management unit to another.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/ Examiner, Art Unit 2139
/REGINALD G BRAGDON/ Supervisory Patent Examiner, Art Unit 2139