Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the argument/remarks filed on 11/24/2025.
Claims 1-20 are currently pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 5, 7-8, 12, 14-15, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yong Wang et al (US 20210232417 A1) in view of Boon S. Ang et al (US 20220103487 A1) & Jiyuan Tang et al (US 20160308771 A1).
For Claim 1, Wang discloses a method for a computer system to perform receive side scaling (RSS) (Wang teaches, in ¶ 0028, lines 1-4, VM1 121 may be reconfigured (see 240 in FIG. 2) to perform packet handling based on multiprocessor architecture configuration), wherein the method comprises:
in response to receiving a first packet that is associated with the first packet flow and destined for a first virtualized computing instance supported by the computer system, the programmable PNIC matching the first packet with the first flow entry (Wang teaches, in ¶ 0032, lines 1-3, in response to receiving first ingress packets (see “P1” 270 in FIG. 2) that requires processing by first VCPU=VCPU-1 211 running on NUMA1 160) and steering the first packet towards the first queue (Wang teaches, in ¶ 0032, lines 4-5, ingress packets 270 may be steered towards first RX queue=RXQ-1 221, which is allocated with memory from NUMA1 160); and
in response to receiving a second packet that is associated with the second packet flow and destined for a second virtualized computing instance supported by the computer system (Wang teaches, in ¶ 0033, lines 1-4, in response to receiving second ingress packets (see “P2” 280 in FIG. 2) that requires processing by second VCPU=VCPU-5 215 running on NUMA2 170), the programmable PNIC matching the second packet with the second flow entry and steering the second packet towards the second queue (Wang teaches, in ¶ 0047, lines 4-5, ingress packets 280 may be steered towards second RX queue=RXQ-5 225, which is allocated with memory from NUMA2 170).
Wang fails to expressly disclose generating and sending one or more instructions to a programmable physical network interface controller (PNIC) of the computer system.
However, Ang, in the analogous art, discloses generating and sending one or more instructions (Ang teaches, in ¶ 0056, that The received flow entries are stored (at 735) in a set of flow entries (e.g., a flow entry table) of the FPO hardware. In some embodiments, the set of flow entries is stored in a memory cache (e.g., content-addressable memory (CAM), ternary CAM (TCAM), etc.) that can be used to identify a flow entry that specifies a set of matching criteria associated with a received data message) to a programmable physical network interface controller (PNIC) of the computer system (Ang teaches, in ¶ 0049, lines 11-15, the processing units executing the flow processing and action generator are processing units of a host computer, while in other embodiments, the pNIC is an integrated MC (e.g., a programmable NIC, smart NIC, etc.).
Ang further teaches, in ¶ 0058, lines 1-6, determines (at 810) if the received data message matches a flow entry stored by the FPO hardware. In some embodiments, determining whether the FPO hardware stores a flow entry matching the received data message is based on a lookup in a set of stored flow entries based on characteristics of the received data message.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Wang with the storing of the flow entries taught in Ang. The motivation is to optimize the flow processing offloaded to a programmable NIC [Ang: ¶ 0001].
Wang and Ang fail to expressly disclose associating a first packet flow with a first queue and (b) associating a second packet flow with a second queue; and steering the first/second packet towards the first/second queue for processing by a first/second processing thread from the multiple processing threads.
However, Tang, in the analogous art, discloses associating a first packet flow with a first queue and (b) associating a second packet flow with a second queue (Tang teaches, in ¶ 0021, that acquire, from the data packet, identification information of a data stream … where the identification information of the data stream is used to differentiate the data stream to which the data packet belongs. Tang also discloses in ¶ 0007 that the data distribution system includes a splitter, a memory, and multiple threads used for processing data, and each thread corresponds to a cache queue (i.e., one-to-one mapping)); and steering the first/second packet towards the first/second queue for processing by a first/second processing thread from the multiple processing threads (Tang teaches, in ¶ 0024, send the data packet to a cache queue of the thread corresponding to the data stream, so that the thread corresponding to the data stream acquires the data packet from the cache queue).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Wang and Ang with the per-thread queuing taught in Tang. The motivation is to improve a processing capability of a multi-core processor [Tang: ¶ 0006].
For Claim 5, Wang discloses a method, wherein the method further comprises: prior to generating and sending the one or more instructions, receiving an advertisement from a device driver, wherein the advertisement indicates an RSS capability of the programmable PNIC (Wang teaches, in ¶ 0041, that PNIC1 181 may advertise various resource(s) associated with the NUMA-aware uplink capability, such as an uplink object (e.g., vmnicX) resides on NUMA1 160 and NUMA2 170; the number of RX queues supported by PNIC1 180 that reside on NUMA1 160 and NUMA2 170; support for packet filters based on receive-side scaling (RSS), destination MAC address (DMAC), layer-3 information, layer-4 information, application-layer information, or any combination thereof).
For Claim 7, Wang discloses a method, wherein generating and sending the one or more instructions comprises: generating and sending the one or more instructions to the programmable PNIC to configure the first flow entry based on non-uniform memory access (NUMA) affinity information associated with the first virtualized computing instance and the programmable PNIC (Wang teaches, in ¶ 0039, that PNIC1 181 may be attached to both NUMA1 160 and NUMA2 170 via separate peripheral component interconnect express (PCIe) interfaces ... The primary device (e.g., the PCIe device with more chips) may be used to steer RX packets to first queue set 221-224 supported by NUMA1 160, or second queue set 225-258 supported by NUMA2 170).
For Claim 8, please refer to the rejection of Claim 1, above.
For Claims 12, 18, please refer to the rejection of Claim 5, above.
For Claims 14, 20, please refer to the rejection of Claim 7, above.
For Claim 15, please refer to the rejection of Claim 1, above.
Claims 2-3, 9-10, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yong Wang et al (US 20210232417 A1) in view of Boon S. Ang et al (US 20220103487 A1) & Jiyuan Tang et al (US 20160308771 A1) as applied to claim 1, 8, or 15 above, and further in view of Kang Il Choi et al (US 20140376555 A1).
For Claims 2, 9, 16, Wang, Ang and Tang fail to expressly disclose supporting one or more application programming interface (API) functions for flow entry configuration.
However, Choi, in the analogous art, discloses supporting one or more application programming interface (API) functions for flow entry configuration (Choi teaches, in ¶ 0053, Finally, open application programming interfaces (APIs) (Openflow, OpenStack, OpenNaaS, OGF's NSI, etc.) may provide additional integration between the NFV and the cloud infrastructure).
Choi further teaches, in ¶ 0125, checking a data attribute or service attribute of the flow after the receiving the flow, wherein the switching of the flow switches the flow to the at least one network function virtual machine according to the switching table based on the data attribute or service attribute.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Wang, Ang and Tang with the flow controller taught in Choi. The motivation is to dynamically connect the processing modules to the flows or to disconnect the processing modules therefrom [Choi: ¶ 0113].
For Claims 3, 10, Ang discloses a method, wherein generating and sending the one or more instructions comprises: generating and sending, by a queue management layer of the computer system, the one or more instructions to the programmable PNIC via the programmable datapath interface (Ang teaches, in ¶ 0059, lines 1-4, that the flow processing and action generator sends (at 725) the generated flow entry to the FPO hardware. As described above, in some embodiments, the generated flow entry is sent to the FPO hardware using a PF of a PCIe connection between the processing units that execute the flow processing and action generator and the FPO hardware).
Claims 4, 11, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yong Wang et al (US 20210232417 A1) in view of Boon S. Ang et al (US 20220103487 A1) & Jiyuan Tang et al (US 20160308771 A1) as applied to claim 1, 8, or 15 above, and further in view of David T. Hass et al (US 20090201935 A1).
For Claims 4, 11, 17, Ang discloses a method, wherein generating and sending the one or more instructions comprises: generating and sending the one or more instructions to burn the first flow entry and the second flow entry into the programmable PNIC configuration (Ang teaches, in ¶ 0047, The method includes providing the pNIC with a set of mappings between VPIDs and PPIDs. FIG. 6 conceptually illustrates a process 600 performed in some embodiments to provide VPID to PPID mappings to be stored in a mapping table of the pNIC to perform flow processing). Ang also teaches, in ¶ 0039, lines 8-12, that The flow entries, in some embodiments, specify a set of matching criteria and an action to take for data messages that match the matching criteria. One or both of the set of matching criteria and the action use VPIDs to identify compute-node interfaces.
Tang teaches, in ¶ 0024, send the data packet to a cache queue of the thread corresponding to the data stream, so that the thread corresponding to the data stream acquires the data packet from the cache queue.
Wang, Ang and Tang fail to expressly disclose a flow key specifying a destination information associated with a packet flow.
However, Hass, in the analogous art, discloses a flow key specifying a destination information associated with a packet flow (Hass teaches, in ¶ 0007, a parse operation is performed utilizing the packet information to generate a key, and a hash algorithm is performed on this key to produce a hash. Further, the packets are allocated to different processor threads, utilizing the hash or the key).
Hass further teaches, in ¶ 0151, Once the key has been formed, the packet director 810 may use the key to classify and dispatch the packet using a classifier 808, hash logic 812, and a distribution mask 814. Furthermore, the classification and dispatch may be implemented in combination with a lookup table (not shown).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Wang, Ang and Tang with the key taught in Hass. The motivation is to quickly distribute packets to the threads designated by software as processing threads [Hass: ¶ 0128, lines 2-4].
Claims 6, 13, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Boon S. Ang et al (US 20220103487 A1) in view of Jiyuan Tang et al (US 20160308771 A1) as applied to claim 1, 8 or 15 above, and further in view of Ayyappan Veeraiyan (US 20140059111 A1).
For Claims 6, 13, 19, Ang and Tang fail to expressly disclose configuring a third flow entry that associates a third packet flow with an RSS pool that includes multiple third queues.
However, Veeraiyan, in the analogous art, discloses configuring a third flow entry that associates a third packet flow with an RSS pool that includes multiple third queues (Veeraiyan teaches, in ¶ 0034, lines 1-7, that After PNIC 322 allocates RSS receive queues 326, PNIC 322 can store incoming VXLAN encapsulated packets in different RSS receive queues based on the hash result of each packet's TCP/IP 5 tuple. In one embodiment load balancer modul3 328 only needs to issue one RSS receive queue allocation command for PNIC 322 to allocate a predetermined number of RSS receive queues (e.g., 4, 8, or more)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the system taught in Ang and Tang with the number of RSS receive queues taught in Veeraiyan. The motivation is to facilitates multi-core processing of the received encapsulated packets [Veeraiyan: ¶ 0007, lines 2-4].
Response to Arguments
Applicant's arguments filed on 11/24/2025 have been fully considered but they are not persuasive. Examiner will respond in the rebuttal that follows:
Rejections under 35 U.S.C. § 103
Examiner respectfully disagrees with Applicant’s argument that the Office Action has not demonstrated that the cited combination either teaches or suggests “the programmable PNIC ... steering the first packet towards the first queue for processing by a first processing thread from multiple processing threads running on the computer system; and
the programmable PNIC ... steering the second packet towards the second queue for processing by a second processing thread from the multiple processing threads,” (page 12 of 15).
The reason being Tang teaches, in ¶ 0021, to acquire, from the data packet, identification information of a data stream … where the identification information of the data stream is used to differentiate the data stream to which the data packet belongs.
Consistent with Applicant’s specification, which states “a one-to-one relationship between a queue (e.g., Q1queue (e.g., Q1171) and a processing thread (e.g., THREAD1 161)” (see para 0052), Tang discloses in ¶ 0007 that the data distribution system includes a splitter, a memory, and multiple threads used for processing data, and each thread corresponds to a cache queue (i.e., one-to-one mapping).
Tang then discloses, in ¶ 0023, determining, according to the correspondence between identification information of a data stream and a thread in the distribution table corresponding to the transport layer communications protocol to which the data packet belongs, a thread corresponding to the data stream to which the data packet belongs.
And, in ¶ 0024, Tang teaches, to send the data packet to a cache queue of the thread corresponding to the data stream, so that the thread corresponding to the data stream acquires the data packet from the cache queue.
Clearly, it can be seen that Tang discloses …determining/identifying the stream to which a received packet belongs; determining/identifying the thread that corresponds to the data stream; and sending the packet to a cache queue of the thread corresponding to the data stream.
When Tang’s recitation of to “send the data packet to a cache queue of the thread corresponding to the data stream” is read in light of Tangs’ disclosure that each thread corresponds to a cache queue, only one conclusion is reasonable. That conclusion is that Tang teaches steering the first packet towards the first queue for processing by a first processing thread from multiple processing threads running on the computer system; and steering the second packet towards the second queue for processing by a second processing thread from the multiple processing threads contrary to Applicant’s assertion.
Examiner also respectfully disagrees with Applicant’s apparent argument that since Tang does not teach or suggest that this splitter is a programmable PNIC, the Office Action has not established that claim 1 is prima facie unpatentable under § 103 over any combination of those references.
Admittedly, Applicant is fully informed that the rejection is based on a combination of references, and not on the Tang reference alone. Nevertheless, Examiner deems it useful to remind Applicant to beware that “one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986)”( MPEP 2145).
Specifically, Examiner cites Ang for teaching a programmable NIC, smart NIC in a host computer executing the [packet] flow processing (see ¶ 0049). And then, Examiner cites Tang, in the analogous art of packet flow/stream processing using multiple processing threads, to teach “send the data packet to a cache queue of the thread corresponding to the data stream,” wherein each thread corresponds to a cache queue. Tang argues, in ¶ 0031, that since each thread has its independent cache queue, Tang’s data distribution system can avoid inter-thread exclusion and synchronization overheads, avoid an inter-core cache failure, thereby improving a processing capability of a multi-core processor (i.e., motivation to combine).
Moreover, Wang is also cited to teach in response to receiving second ingress packets (see “P2” 280 in FIG. 2) that requires processing by second VCPU=VCPU-5 215 running on NUMA2, that ingress packets 280 may be steered towards second RX queue=RXQ-5 225 (see ¶ 0033 and ¶ 0047). In other words, Wang teaches to “steer packets that are destined for different virtualized computing instances”.
Therefore, Examiner respectfully submits that the combination of Wang, Ang, and Tang does disclose, suggest, or otherwise render obvious the limitations recited in Independent Claims 1, 8 and 15.
Dependent claims 2-7, 9-14, and 16-20 are not yet allowable for multiple reasons, including being rejected on their own merits, as well as for depending from rejected base claims 1, 8 and 15.
For at least the above reasons, Examiner respectfully submits that the pending claims 1-20 are not yet allowable.
In light of the above rejection and rebuttal, the rejection of claims 1-20, in this office action, is hereby made final.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Mehra (US 9882815 B2) is pertinent to a method for forwarding packets in a network device is disclosed. The method comprises receiving a packet; mapping the packet to a bucket, where the bucket is associated with a packet processing thread from a plurality of packet processing threads; and determining whether the packet processing thread is oversubscribed
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMED A KAMARA whose telephone number is (571)270-5629. The examiner can normally be reached M-F 9AM-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHARLES JIANG can be reached on 5712707191. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMED A KAMARA/Primary Examiner, Art Unit 2412
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