DETAILED ACTION
Contents
I. Notice of Pre-AIA or AIA Status 3
II. Priority 3
III. Pertinent Prosecution History 3
IV. Reissue Requirements 4
V. Claim Status 5
VI. Information Disclosure Statement 6
VII. Application Data Sheet 6
VIII. Specification Objections 7
IX. Claim Objections 7
X. Claim Interpretation 8
A. Lexicographic Definitions 9
B. 35 U.S.C. § 112 6th Paragraph 9
XI. Claim Rejections – 35 USC § 103 10
A. Claims 17 and 29-34 are rejected under 35 U.S.C. 103 as obvious over Hasenplaugh et al. (U.S. Patent No. 7,725,657)(“ Hasenplaugh”) in view of Herdich et al. (U.S. Publication No. 2013/0263902) (“Herdich”). 10
B. Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hasenplaugh et al. (U.S. Patent No. 7,725,657)(“ Hasenplaugh”) in view of Herdich et al. (U.S. Publication No. 2013/0263902) (“Herdich”) as applied to claims 17 and 29-34 above, and in further view of Man et al. (U.S. Publication No. 2014/0089688)(“Man”). 18
XII. Allowable Subject Matter 19
A. Claims 18-23 19
B. Claims 25-28 20
XIII. Conclusion 22
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant filed the instant divisional reissue application 18/238,056 (“‘056 Div Reissue Application”) on 25 August 2023 for U.S. Reissue Application No. 17/092,029 (“‘029 Reissue Application”), filed 06 November 2020, for U.S. Patent Application No. 14/866,862 (“ ‘862 Application"), filed 26 September 2015, now U.S. Patent No. 10,120,809 (“‘809 Patent”), issued 06 November 2018.
Thus, the Examiner concludes that, for examination purposes, the instant ‘056 Div Reissue Application has an effective U.S. filing date of the ‘862 Application, i.e., 26 September 2015.
Pertinent Prosecution History
As set forth supra, Applicant filed the application for the instant ‘056 Div Reissue Application on 25 August 2023. The Examiner finds that the instant ‘056 Div Reissue Application included a preliminary amendment (“Aug 2025 Preliminary Amendment”) to the claims (“Aug 2025 Claim Amendment”) and the specification (“Aug 2025 Spec Amendment”). The Aug 2025 Claim Amendment includes an amendment: canceling original claims 1-16; and adding new claims 17-30.
On 09 February 2026, Applicant filed a supplemental amendment to the claims (“Feb 2026 Claim Amendment”) further adding new claims 31-34.
Reissue Requirements
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the ‘809 Patent is or was involved. These proceedings would include interferences, reissues, reexaminations, post-grant proceedings and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
The Examiner notes that Amendment practice for Reissue Applications is NOT the same as for non-provisional applications. See MPEP §§ 1413 and 1453. Reissue application amendments must comply with 37 CFR 1.173, while non-provisional application amendments must comply with 37 CFR 1.121. Particularly,
Manner of making amendments under 37 CFR 1.173:
All markings (underlining and bracketing) are made relative to the original patent text, 37 CFR 1.173(g) (and not relative to the prior amendment).
For amendments to the abstract, specification and claims, the deleted matter must be enclosed in brackets, and the added matter must be underlined. See 37 CFR 1.173(d).
For amendments to the drawings, any changes to a patent drawing must be submitted as a replacement sheet of drawings which shall be an attachment to the amendment document. Any replacement sheet of drawings must be in compliance with § 1.84 and shall include all of the figures appearing on the original version of the sheet, even if only one figure is amended. Amended figures must be identified as "Amended," and any added figure must be identified as "New." In the event that a figure is canceled, the figure must be surrounded by brackets and identified as "Canceled." All changes to the drawing(s) shall be explained, in detail, beginning on a separate sheet accompanying the papers including the amendment to the drawings. See 37 CFR 1.173(d)(3).
The Examiner further notes that all amendments to the instant ‘056 Div Reissue Application must comply with 37 CFR 1.173(b)-(g).
Claim Status
The Examiner finds that the claim status in the instant ‘056 Div Reissue Application is as follows:
Claim(s) 1-16 (Original and Canceled)
Claim(s) 17-34 (New)
Thus, the Examiner concludes that claims 17-34 are pending in the instant ‘056 Div Reissue Application. Claims 17-34 are examined (“Examined Claims”).
Information Disclosure Statement
The Applicants’ Information Disclosure Statements filed: 18 January 2024 (“Jan 2024 IDS”); 04 June 2024 (“June 2024 IDS”); and 22 August 2024 (“Aug 2024 IDS”) have been received and entered into the record. Since the Information Disclosure Statements comply with the provisions of MPEP § 609, the references cited therein have been considered by the Examiner. See attached PTO-1449 forms.
Application Data Sheet
The application data sheet (ADS) filed on 25 August 2023 (“Aug 2023 ADS”) is objected to because the Aug 2023 ADS does not properly identify the domestic benefit information of the ‘056 Div Reissue Application as both a divisional1 of the 029 Reissue Application and a reissue application of the ‘809 Patent (emphasis added). See the Reissue Application Filing Guide at http://www.uspto.gov/sites/default/files/forms/uspto_reissue_ads_guide_Sept2014.pdf for more information and in particular see the screen shot on page 10 given the sample facts presented on page 9. The corrected ADS should comply with 37 CFR 1.76(c)(2), which requires that any changes to an ADS be identified with markings (underline for addition, strike through for deletion).
Applicant should additionally file, as a paper separate from its next response, a Request for Corrected Filing Receipt. This is the best way to ensure that these changes are acted upon and corrected by the appropriate official.
Specification Objections
The Aug 2025 Spec Amendment is objected to because the first sentence of the specification does not contain sufficient notification stating that more than one reissue application has been filed and identifying each of the reissue applications by relationship, application number and filing date as set forth in 37 CFR 1.177(a). (See MPEP § 1451). Specifically, the Examiner finds that the “more than one” statement: is not the ‘first sentence’ of the ‘971 patent as required by 37 CFR 1.177(a); and does not indicate that the more than one reissue application has been filed for the “U.S. Patent No. 10,120,809” and then identify each of the reissue applications by relationship, application number and filing date.
Appropriate correction is required.
Claim Objections
MPEP § 1453 states,
pursuant to 37 CFR 1.173(c), each claim amendment must be accompanied by an explanation of the support in the disclosure of the patent for the amendment (i.e., support for all changes made in the claim(s), whether insertions or deletions). The failure to submit an explanation will generally result in a notification to applicant that the amendment before final rejection is not completely responsive (see 37 CFR 1.135(c)).
(MPEP § 1453; emphasis added). The Examiner finds that Applicant has not provided sufficient explanation of support for at least the amendments to claims instantly provided in the Aug 2025 Claim Amendment, as set forth in 37 CFR 1.173(c). (Id.) Specifically, the Examiner finds that appropriate explanation of support in accordance with Rule 1.173(c) – with reference to particular passages and/or figures in the specification, and preferably on a claim-by-claim and limitation-by-limitation basis – is required.
In addition, the Aug 2025 Claim Amendment does not comply with 37 CFR 1.173(b) and is objected to because the indicated new claims in the Aug 2025 Claim Amendment are not underlined in their entirety (i.e., claim number, claim status identifier and claim limitations), as set forth in 37 CFR 1.173(d). (See MPEP § 1453).
Moreover, the Examiner finds that the amended new claims 17-34 are not indicated as “New,” as set forth in 37 CFR 1.173(b)(2). (Id.)
Appropriate correction is required.
Furthermore, claim 19 is objected to because of the following informalities: in line 2, the recitation to “second number of lanes” should read – the second number of lanes…–. Appropriate correction is required.
Claim Interpretation
During examination, claims are given the broadest reasonable interpretation consistent with the specification and limitations in the specification are not read into the claims. See MPEP § 2111, MPEP § 2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP § 2111.01(I). It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP § 2111.01(II). Therefore, unless one of the exceptions applies below, Examiners will interpret the limitations of the pending and examined claims using the broadest reasonable interpretation.
Lexicographic Definitions
A first exception to the prohibition of reading limitations from the specification into the claims is when the Applicant for patent has provided a lexicographic definition for the term. (See MPEP § 2111.01(IV)). After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiner, the Examiner finds that he is unable to locate any lexicographic definitions (either express or implied) with reasonable clarity, deliberateness, and precision. Because the Examiner is unable to locate any lexicographic definitions with reasonable clarity, deliberateness, and precision, the Examiner concludes that Applicant is not his/her own lexicographer. (Id.)
35 U.S.C. § 112 6th Paragraph
A second exception to giving words in the claims their ordinary and customary meaning is when a claimed phrase is interpreted in accordance with 35 U.S.C. § 112 6th paragraph. See MPEP § 2181 et seq.
The Examiner finds that because the Examined Claims do not recite “step,” “means” or a claim term used as a substitution for “means” (i.e. a generic placeholder for “means”), the Examined Claims fail Prong (A) as set forth in MPEP §2181. Because the eighteen (18) Examined Claims fail Prong (A) as set forth in MPEP §2181 I., the Examiner concludes that all Examined Claims do not invoke 35 U.S.C. §112, 6th paragraph. See also Ex parte Miyazaki, 89 USPQ2d 1207, 1215-16 (B.P.A.I. 2008)(precedential).
Claim Rejections – 35 U.S.C. § 112
35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23 and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 23 recites the limitation "the physical sub-block" in line 2; claim 24 recites the limitation "the cores" in line 3; and claim 28 recites the limitation "the cores" in line 2. There is insufficient antecedent basis for this limitation in the claim.
The Examiner recommends Applicant replace “the cores” with – the plurality of cores –.
Claim Rejections – 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 17 and 29-34 are rejected under 35 U.S.C. 103 as obvious over Hasenplaugh et al. (U.S. Patent No. 7,725,657)(“ Hasenplaugh”) in view of Herdich et al. (U.S. Publication No. 2013/0263902) (“Herdich”).
With respect to the limitations of claim 17, and
[17] [a] processing device comprising:
a plurality of cores, a first core of the plurality of cores comprising execution circuitry to simultaneously execute instructions;
In this regard, the Examiner finds that Hasenplaugh discloses a plurality of cores (Hasenplaugh at Figure 1; core 20 and graphics engine 25,; see also processing cores 574a and 574b of Figure 4) having a first core of the plurality of cores comprising execution circuitry to simultaneously execute instructions (i.e., a first core can execute instructions independently of, and therefore simultaneously with, the graphics engine 25 – see, e.g., Id at claim 6 – “a processor having a first core and a graphics engine to independently execute instructions…”)
registers to store a first waymask corresponding to a first class of service (CLOS) and a second waymask corresponding to a second CLOS, the first waymask comprising a first plurality of bits and the second waymask comprising a second plurality of bits, the bits in the first and second plurality of bits to indicate cache ways of the L3 cache to be allocated to the first and second CLOS, respectively; and;
In this regard, the Examiner finds that Hasenplaugh discloses registers (169, Hasenplaugh at Figure 2) storing a first waymask corresponding to a first class of service (CLOS) and a second waymask corresponding to a second CLOS, the first waymask comprising a first plurality of bits and the second waymask comprising a second plurality of bits, the bits in the first and second plurality of bits to indicate cache ways of the L3 cache to be allocated to the first and second CLOS, respectively (id at c.5, ll.2-4 – there is a waymask for each priority level (i.e., class of service), and each waymask includes a bit for each way of the last level cache (LLC) 100; id. at c.5, ll.28-29 – there are two priority levels (and therefore, two waymasks, each associated with one of the priority levels)).
a cache controller coupled to the plurality of cores to provide access to the L3 cache using the cache ways indicated by the first waymask and/or the second waymask.
In this regard, the Examiner finds that Hasenplaugh discloses a cache controller (QoS controller 65, Hasenplaugh at Figure 1; or cache controller shown in Figure 2) coupled to the plurality of cores to provide access to the L3 cache using the cache ways indicated by the first waymask and/or the second waymask. (Id. at c.4, ll.48-51 – cache controller provides access to the LLC cache 100; also see Figure 3 – cache allocation is indicated by the first and/or second waymask when way-based allocation is enabled – i.e., the “Y” branch from block 210).
an interconnect fabric to couple the plurality of cores to a Level 3 (L3) cache
In this regard, Hasenplaugh discloses the system utilizing a shared “last level cache” (LLC), rather than an L3 cache, as claimed. (Hasenplaugh at c.4, ll.48-51 – cache controller provides access to the LLC cache 100; also see Figure 3 – cache allocation is indicated by the first and/or second waymask when way-based allocation is enabled – i.e., the “Y” branch from block 210).
Hasenplaugh discloses the limitations, as previously set forth, except for specifically calling for an interconnect fabric coupling the plurality of cores to a Level 3 (L3) cache, as claimed.
However, an interconnect fabric coupling the plurality of cores to a Level 3 (L3) cache is known in the art. The Examiner finds that Herdich, for example, teaches discloses a power-efficient processor architecture. In particular, Herdrich teaches a processor architecture (Herdich at Figure ) that includes multiple processing cores (510, 520) that are coupled to an LLC (550) via a ring interconnect (530). Notably, Herdrich teaches the ring interconnect can also be a fabric architecture, and the LLC is an L3 cache. (Id. at ¶ 0048).
The Examiner finds that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the interconnect fabric to couple the plurality of cores to an L3 cache as described in Herdich in the system of Hasenplaugh (in which Hasenplaugh discloses processing cores (20, 25 of Figure 1) being connected to a last level cache (50)).
A person of ordinary skill in the art would be motivated to incorporate the interconnect fabric to couple the plurality of cores to an L3 cache, since it provides a mechanism to utilize a conventional means for couple processing cores to last level (i.e., L3) caches.
Moreover, the Examiner asserts that applying a known technique to a known device ready for improvement would yield predictable results. That is, it would have been recognized by one of ordinary skill in the art that applying the known technique taught by Herdich to the processing device of Hasenplaugh would have yielded predicable results and resulted in an improved system, namely, providing the interconnect fabric to couple the plurality of cores to an L3 cache, in Hasenplaugh to provide a mechanism to utilize a conventional means for couple processing cores to last level (i.e., L3) caches.
With respect to the limitations of claim 29, Hasenplaugh and Herdich teaches and/or renders obvious
[29] wherein the first core is to provide a first logical processor to execute a thread, the first logical processor comprising a first portion of the execution circuitry:
In this regard, Hasenplaugh discloses the system comprising the first core providing a first logical processor to execute a thread, the first logical processor comprising a first portion of the execution circuitry. (Hasenplaugh at claim 1).
With respect to the limitations of claim 30, Hasenplaugh and Herdich teaches and/or renders obvious
[30] wherein the cache controller is to map a first transaction associated with the first CLOS to a first plurality of cache ways in accordance with the first waymask and is to map a second transaction associated with the second CLOS to a second plurality of cache ways in accordance with the second waymask.
In this regard, Hasenplaugh discloses the cache controller mapping a first transaction associated with the first CLOS to a first plurality of cache ways in accordance with the first waymask and mapping a second transaction associated with the second CLOS to a second plurality of cache ways in accordance with the second waymask (Hasenplaugh at c.4, ll.48-51 – cache controller provides access to the LLC cache 100; also see id. at Figure 3 – cache allocation is indicated by the first and/or second waymask when way-based allocation is enabled – i.e., the “Y” branch from block 210; also see id. at c.5, ll.2-12 – there is a waymask for each priority level (i.e., class of service), and each waymask includes a bit for each way of the last level cache (LLC) 100; also see id. at c.5, ll.28-29 – there are two priority levels (and therefore, two waymasks, each associated with one of the priority levels)).
With respect to the limitations of claim 31, Hasenplaugh and Herdich teaches and/or renders obvious
[31] wherein the registers are to store a third waymask corresponding to a third CLOS, the third waymask comprising a third plurality of bits to indicate third cache ways of the L3 cache to be allocated to the third CLOS, the third CLOS to be associated with I/O data received from one or more I/O devices, wherein the cache controller is to directly store the I/O data in the L3 cache using the third cache ways.
In this regard, Hasenplaugh discloses registers (169, Hasenplaugh at Figure 2) storing a third waymask corresponding to a third class of service (CLOS), the third waymask comprising a third plurality of to indicate cache ways of the L3 cache to be allocated to the third CLOS, respectively (id at c.5, ll.2-4 – there is a waymask for each priority level (i.e., class of service), and each waymask includes a bit for each way of the last level cache (LLC) 100; id. at c.5, ll.28-29 – there are two priority levels (and therefore, two waymasks, each associated with one of the priority levels)).
In addition, Hasenplaugh discloses the CLOS being associated with one or more I/O devices (id. at Figure 5) and the cache controller (QoS controller 65, Hasenplaugh at Figure 1; or cache controller shown in Figure 2) being coupled to the plurality of cores to provide access to the L3 cache using the cache ways indicated by the third. (Id. at c.4, ll.48-51 – cache controller provides access to the LLC cache 100; also see Figure 3 – cache allocation is indicated by the first and/or second waymask when way-based allocation is enabled – i.e., the “Y” branch from block 210). From this perspective, the cache controller (QoS controller 65, Hasenplaugh at Figure 1; or cache controller shown in Figure 2) directly stores the I/O data from I/O devices in the LLC cache using the third cache ways. (Id. at c.7, ll.19-48 for I/O device providing I/O data).
Moreover, Herdrich teaches a processor architecture (Herdich at Figure ) that includes multiple processing cores (510, 520) that are coupled to an LLC (550) via a ring interconnect (530). Notably, Herdrich teaches the ring interconnect can also be a fabric architecture, and the LLC is an L3 cache. (Id. at ¶ 0048).
The Examiner finds that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the interconnect fabric to couple the plurality of cores to an L3 cache as described by Herdich and store the I/O data into the L3 cache using the third cache ways of Hasenplaugh.
A person of ordinary skill in the art would be motivated to incorporate the interconnect fabric to couple the plurality of cores to an L3 cache and store the I/O data into the L3 cache using the third cache ways, since it provides a mechanism to utilize a conventional means for couple processing cores to last level (i.e., L3) caches.
Moreover, the Examiner asserts that applying a known technique to a known device ready for improvement would yield predictable results. That is, it would have been recognized by one of ordinary skill in the art that applying the known technique taught by Herdich to the processing device of Hasenplaugh would have yielded predicable results and resulted in an improved system, namely, providing the interconnect fabric to couple the plurality of cores to an L3 cache and store the I/O data into the L3 cache using the third cache ways, in Hasenplaugh to provide a mechanism to utilize a conventional means for couple processing cores to last level (i.e., L3) caches.
With respect to the limitations of claims 32-34, Hasenplaugh and Herdich teaches and/or renders obvious
[32] wherein the cache controller is to read packet header information of a data packet including the I/O data received from the one or more I/O devices to determine that the I/O data included in the data packet is to be directly stored in the L3 cache using the third cache ways (claim 32);
[33] wherein the cache controller is to read packet header information of a data packet including the I/O data received from the one or more I/O devices, wherein if the packet header information includes a first indication, the cache controller is to directly write the 1/O data to the L3 cache and if the packet header information includes a second indication, the cache controller is to cause the 1/O data to be written to a different memory (claim 33);
[34] wherein the different memory comprises a system memory coupled to the processing device (claim 34);
In this regard, Hasenplaugh discloses the cache controller (QoS controller 65, Hasenplaugh at Figure 1; or cache controller shown in Figure 2) directly storing the I/O data from I/O devices in the LLC cache using the third cache ways. (Id. at c.4, ll.48-51 – cache controller provides access to the LLC cache 100; also see Figure 3 – cache allocation is indicated by the first and/or second waymask when way-based allocation is enabled – i.e., the “Y” branch from block 210; also see id. at c.7, ll.19-48 for I/O device providing I/O data). Hasenplaugh discloses the cache controller (QoS controller 65, Hasenplaugh at Figure 1; or cache controller shown in Figure 2) reading header information of the data packet including data received from one or more of the I/O devices including indications whether to store I/O data in one or more memories 575, 585 of the processing cores 574a and 574b, 584a and 584b of Figure 4, respectively. (Id. at c.4, l.24 – c.5, l.4; see Figures 2, 4, 5).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hasenplaugh et al. (U.S. Patent No. 7,725,657)(“ Hasenplaugh”) in view of Herdich et al. (U.S. Publication No. 2013/0263902) (“Herdich”) as applied to claims 17 and 29-34 above, and in further view of Man et al. (U.S. Publication No. 2014/0089688)(“Man”).
With respect to the limitations of claim 24, and
[24] further comprising: power management circuitry to independently control a frequency and a voltage of each of the cores and a serial interconnect.
Hasenplaugh and Herdich discloses the limitations, as previously set forth, except for specifically calling for power management circuitry to independently control a frequency and a voltage of each of the cores and a serial interconnect.
However, power management circuitry to independently control a frequency and a voltage of each of the cores and a serial interconnect is known in the art. The Examiner finds that Man for example, teaches a system for sharing power between domains in a processor package. In particular, Man teaches a multi-core processing system that includes power management circuitry to independently control a frequency and a voltage of each of the cores (i.e., power control unit (PCU) 140, Man at Figure 1; also see id. at ¶ 0033 – the PCU can enable one or more of the cores of the CPU to operate at different frequency and/or voltage levels) and a serial interconnect (see id. at Figure 7 and ¶ 0061 – bus interface 1105 can be a serial interconnect).
The Examiner finds that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the power management circuitry to independently control a frequency and a voltage of each of the cores and a serial interconnect as described by Man in the system of Hasenplaugh and Herdich.
A person of ordinary skill in the art would be motivated to incorporate power management circuitry to independently control a frequency and a voltage of each of the cores and a serial interconnect, since it provides a mechanism to facilitate optimal power consumption and performance of the cores; and a serial interface is a conventional means for coupling higher level cache to a memory controller, as illustrated in Figure 7 of Man.
Allowable Subject Matter
Claims 18-23 and 25-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-23
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, as set forth above, the prior art of record teaches the most salient features of a processing device comprising a plurality of cores, an interconnect fabric registers and a cache controller. Specifically, Hasenplaugh and Herdich teaches and/or renders obvious a processing device of claim 17.
Allowability of dependent claim 18 is indicated because none of the prior art of record teaches or fairly suggests the device further comprising a serial interconnect to couple the plurality of cores to a link having a first link width comprising a first number of lanes; and link management circuitry to reduce the first link width to a second link width comprising a second number of lanes fewer than the first number of lanes, as claimed.
Claims 19-23 are similarly deemed as having allowable subject matter based on their dependency from dependent claim 18, respectively.
Claims 25-28
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 25, as set forth above, the prior art of record teaches the most salient features of a processing device comprising a plurality of cores, an interconnect fabric registers and a cache controller. Specifically, Hasenplaugh, Herdich and Man teaches and/or renders obvious a processing device of claim 24. In particular, Man teaches the processing device of claim 24, further comprising:
a multi-die package (processor 100; Man at Figure 1);
a first die (CPU 120) comprising the plurality of cores (125, 130) mounted on the multi-die package; and
a second die (PCH 160) coupled to the first die over an on-package link (190).
Man does not appear to teach the second die being arranged so as to “couple the first die to a system memory interconnect and one or more I/O interconnects,” as claimed. Rather, as shown in Figure 1 of Man, the second die (160) is not shown as coupling the first die (120) to a system memory interconnect and one or more I/O interconnects.
Thus, allowability of dependent claim 25 is indicated because none of the prior art of record teaches or fairly suggests the device comprising the second die being arranged so as to couple the first die to a system memory interconnect and one or more I/O interconnects, as claimed.
Claims 26-28 are similarly deemed as having allowable subject matter based on their dependency from dependent claim 25, respectively.
Conclusion
Applicant is respectfully reminded that any suggestions or examples of claim language provided by the Examiner are just that—suggestions or examples—and do not constitute a formal requirement mandated by the Examiner. To be especially clear, any suggestion or example provided in this Office Action (or in any future office action) does not constitute a formal requirement mandated by the Examiner.
Should Applicant decide to amend the claims, Applicant is also reminded that—like always—no new matter is allowed. The Examiner therefore leaves it up to Applicant to choose the precise claim language of the amendment in order to ensure that the amended language complies with 35 U.S.C. § 112(a).
Independent of the requirements under 35 U.S.C. § 112(a), Applicant is also respectfully reminded that when amending a particular claim, all claim terms must have clear support or antecedent basis in the specification. See 37 C.F.R. § 1.75(d)(1) and MPEP § 608.01(o). Should Applicant amend the claims such that the claim language no longer has clear support or antecedent basis in the specification, an objection to the specification may result. Therefore, in these situations where the amended claim language does not have clear support or antecedent basis in the specification and to prevent a subsequent ‘Objection to the Specification’ in the next office action, Applicant is encouraged to either (1) re-evaluate the amendment and change the claim language so the claims do have clear support or antecedent basis or, (2) amend the specification to ensure that the claim language does have clear support or antecedent basis. See again MPEP § 608.01(o) (¶3). Should Applicant choose to amend the specification, Applicant is reminded that—like always—no new matter in the specification is allowed. See 35 U.S.C. § 132(a). If Applicant has any questions on this matter, Applicant is encouraged to contact the Examiner via the telephone number listed below.
Applicant is reminded of the obligation to apprise the Office of any prior or concurrent proceedings in which the ‘809 Patent is or was involved, such as interferences or trials before the Patent Trial and Appeal Board, other reissues, reexaminations, or litigations and the results of such proceedings.
In accordance with MPEP § 1406, the Examiner has reviewed and considered the prior art cited or ‘of record’ in the original prosecution of the ‘809 Patent. Applicant is reminded that a listing of the information cited or ‘of record’ in the original prosecution of the ‘809 Patent need not be resubmitted in this reissue application unless Applicant desires the information to be printed on a patent issuing from this reissue application.
Applicant is further reminded of the continuing obligation under 37 C.F.R. §1.56 to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN J RALIS whose telephone number is (571)272-6227. The examiner can normally be reached on Monday-Friday 8:30am-5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on 571-272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Stephen J. Ralis/Primary Examiner, Art Unit 3992 Conferees:
/Luke S. Wassum/
Primary Examiner, Art Unit 3992
/H.B.P/Hetul PatelSupervisory Patent Examiner, Art Unit 3992
SJR
08/06/2026
1 In a newly filed Application Data Sheet, please clarify if the instant ‘056 Div Reissue Application is also a reissue application of the ‘809 Patent.
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