DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/5/26 has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-7 is/are rejected is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20120185668) in view of Bueb (US 20230176776).
With respect to claim 1, the Joo reference teaches a memory controller comprising:
an interface configured to receive a first memory request from a host; (e.g. fig 2, memory interface unit 90) and
a processor (e.g. CPU 3) configured to:
fetch the first memory request in a queue storing the first memory request, (paragraph 44, where the first queue buffer 13 temporarily stores and outputs the missed virtual address VA1. The first queue buffer 13 processes missed virtual address data on a first-in-first-out (FIFO) basis. In certain embodiments, the first queue buffer 13 may also store and output access identification (ID) corresponding to a missed virtual address)
compare a destination address of the first memory request with a first stored destination address of a block request, among one or more stored destination addresses in a storage, (paragraph 48, where when the page number PN2 of the virtual address VA2 output from the first queue buffer 13 matches the frame number FN2 in the TLB 12, the second TLB lookup logic 15 translates the virtual address VA2 into the physical address PA2 and outputs the physical address PA2. When the page number PN2 of the virtual address VA2 matches the frame number FN2, it is referred to as a "TLB hit"; and paragraph 36, where pages PN0-PNn may be arranged in a sequence of adjacent blocks of virtual addresses)
associate the first memory request with the first stored destination address in the storage. (paragraph 48, where when the page number PN2 of the virtual address VA2 output from the first queue buffer 13 matches the frame number FN2 in the TLB 12, the second TLB lookup logic 15 translates the virtual address VA2 into the physical address PA2 and outputs the physical address PA2. When the page number PN2 of the virtual address VA2 matches the frame number FN2, it is referred to as a "TLB hit")
However, the Joo reference does not explicitly teach associate the memory request with the first stored destination address in the storage by: binding the first memory request with the block request based on a match between the destination address of the first memory request and the first stored destination address in the storage, and storing the first memory request in association with the first stored destination address in the storage, wherein the destination address and the one or more stored destination addresses are logical block addresses, and process one or more entries in the storage based on the first memory request; (emphasis added) and wherein the block request is based on a second memory request that is fetched by the processor before the first memory request.
The Bueb reference teaches it is conventional to have:
binding the first memory request with the block request based on a match between the destination address of the first memory request and the first stored destination address in the storage, (paragraph 14, where the host system may determine a mapping between a set of logical address ranges and a set of identifiers (IDs). That is, each ID in the set may correspond to a different logical address range. The host system may utilize the mapping to determine an ID for each of a first command and a second command based on the mapping. Matching IDs between commands may indicate that the commands belong to the same L2P table portion; and where if the ID for the first command matches the ID for the second command, the host system may group the first command together with the second command in the command queue) and
storing the first memory request in association with the first stored destination address in the storage, wherein the destination address and the one or more stored destination addresses are logical block addresses, and process one or more entries in the storage based on the first memory request; (paragraph 14, where the host system may determine a mapping between a set of logical address ranges and a set of identifiers (IDs); and where if the ID for the first command matches the ID for the second command, the host system may group the first command together with the second command in the command queue. Grouping the first command and the second command together may ensure that the memory system executes the first command and the second command within a short time interval (e.g., time interval below a threshold) and because the first command and the second command may belong to the same L2P mapping portion) and
wherein the block request is based on a second memory request that is fetched by the processor before the first memory request. (paragraph 38, where the host system 105 may compare parameters (e.g., a block size or a block number) of different commands of the set of commands [i.e. a ‘block request’] to determine which commands of the set are associated with a same L2P table portion; and paragraph 14, where grouping the first command and the second command together may ensure that the memory system executes the first command and the second command within a short time interval (e.g., time interval below a threshold) and because the first command and the second command may belong to the same L2P mapping portion [i.e. the first command is performed before the second command performed within a short time interval within one another which is analogous to “a second memory request that is fetched by the processor before the first memory request” as claimed])
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Joo reference to have binding the first memory request with the block request based on a match between the destination address of the first memory request and the first stored destination address in the storage, and storing the first memory request in association with the first stored destination address in the storage, wherein the destination address and the one or more stored destination addresses are logical block addresses, and process one or more entries in the storage based on the first memory request; and wherein the block request is based on a second memory request that is fetched by the processor before the first memory request, as taught by the Bueb reference.
The suggestion/motivation for doing so would have been to allow a memory system to perform less L2P mapping transfers when compared to other methods, which may decrease latency of the system and increase the efficiency of the system. (Bueb, paragraph 38)
Therefore it would have been obvious to combine the Joo and Bueb references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 3, the combination of the Joo and Bueb references teaches the memory controller of claim 1, wherein the processor is configured to add a new entry in the storage corresponding to the first memory request based on a determination that the destination address of the memory request is missing among the one or more stored destination addresses in the storage. (Joo, paragraph 44, where first queue buffer 13 temporarily stores and outputs the missed virtual address VA1. The first queue buffer 13 processes missed virtual address data on a first-in-first-out (FIFO) basis. In certain embodiments, the first queue buffer 13 may also store and output access identification (ID) corresponding to a missed virtual address [i.e. missed virtual addresses are added to the queue in a FIFO manner])
With respect to claim 4, the combination of the Joo and Bueb references teaches the memory controller of claim 1, wherein the processor is configured to process the one or more entries in the storage to generate a block input/output (IO) request for accessing a storage device, and wherein the block IO request is configured to access one or more memory requests. (Joo, paragraph 49, where the first selector 17, in response to the first selection signal SEL1, selects one of a plurality of physical addresses, for example, PA2, PA3, and PPA1 and outputs a selected physical address to the memory 110; and the first selection signal SEL1 may be used to control the first selector 17 in order to selectively output the physical address PA3 after the physical addresses PA2 and PPA1 of the physical addresses PA2, PA3, and PPA1 are output)
With respect to claim 5, the combination of the Joo and Bueb references teaches the memory controller of claim 1, wherein the one or more stored destination addresses correspond to a third memory request fetched by the processor. (Joo, paragraph 49, where the first selector 17, in response to the first selection signal SEL1, selects one of a plurality of physical addresses, for example, PA2, PA3, and PPA1 and outputs a selected physical address to the memory 110; and the first selection signal SEL1 may be used to control the first selector 17 in order to selectively output the physical address PA3 after the physical addresses PA2 and PPA1 of the physical addresses PA2, PA3, and PPA1 are output)
With respect to claim 6, the combination of the Joo and Bueb references teaches the memory controller of claim 1, further comprising a plurality of queues, each storing one or more memory requests, wherein the plurality of queues are configured to store a plurality of memory requests according to a traffic class defined based on one or more characteristics of a memory access. (Joo, paragraph 44, where the first queue buffer 13 temporarily stores and outputs the missed virtual address VA1. The first queue buffer 13 processes missed virtual address data on a first-in-first-out (FIFO) basis; and paragraph 55, where the second queue buffer 21 temporarily stores and outputs the write virtual address WVA1. The second queue buffer 21 processes data on a FIFO basis like the first queue buffer 13)
With respect to claim 7, the combination of the Joo and Bueb references teaches the memory controller of claim 1, further comprising a plurality of queues, each storing one or more memory requests,
wherein a first queue, among the plurality of queues, is configured to comprise a first group of memory requests corresponding to a first traffic class, wherein a second queue, among the plurality of queues, is configured to comprise a second group of memory requests corresponding to a second traffic class, and wherein the first traffic class and the second traffic class are defined based on one or more characteristics of a memory access. (Joo, paragraph 44, where the first queue buffer 13 temporarily stores and outputs the missed virtual address VA1. The first queue buffer 13 processes missed virtual address data on a first-in-first-out (FIFO) basis; and paragraph 55, where the second queue buffer 21 temporarily stores and outputs the write virtual address WVA1. The second queue buffer 21 processes data on a FIFO basis like the first queue buffer 13)
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20120185668) in view of in view of Bueb (US 20230176776) as shown in the rejections above, and further view of Chhabra (US 20160179702).
With respect to claim 2, the combination of the Joo and Bueb references does not explicitly teach the memory controller of claim 1, further comprising a plurality of queues, each storing one or more memory requests, wherein the processor is further configured to fetch the one or more memory requests in each of the plurality of queues in a round robin manner.
The Chhabra reference teaches it is conventional to have a plurality of queues, each storing one or more memory requests, wherein the processor is further configured to fetch the one or more memory requests in each of the plurality of queues in a round robin manner. (paragraph 48, where one advantage of selecting the memory links in a round-robin order can be to enable each of the memory links to be selected equally. Another advantage of using the round-robin selection scheme to select the memory links can be to maintain an order of the requests and responses as they are received at the queues. Another advantage of using the round-robin selection scheme can be to enable each memory link to remain in the order of selection when the queue of the memory link is empty during previous arbitration cycles)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Joo and Bueb references to have wherein a plurality of queues, each storing one or more memory requests, wherein the processor is further configured to fetch the one or more memory requests in each of the plurality of queues in a round robin manner, as taught by the Chhabra reference.
The suggestion/motivation for doing so would have been to enable each of the memory links to be selected equally; and maintain an order of the requests and responses as they are received at the queues. (Chhabra, paragraph 48)
Therefore it would have been obvious to combine the Joo, Bueb, and Chhabra references for the benefits shown above to obtain the invention as specified in the claim.
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20120185668) in view of Bueb (US 20230176776) as shown in the rejections above, and further in view of Ki (US 20220113915).
With respect to claim 8, the combination of the Joo and Bueb references does not explicitly teach the memory controller of claim 1, wherein the first memory request is a compute express link (CXL) request.
The Ki reference teaches it is conventional to have wherein the first memory request is a compute express link (CXL) request. (paragraph 90, where CXL may be used to transfer input data from the host 424 to the working memory 408, In some embodiments, a potential advantage of using CXL to transfer input data (e.g., DL vectors) is that the coherency of CXL may allow the data to be transferred in a passive manner, e.g., on demand by the NPU 406 (and/or any of the virtual NPUs 406-1, 406-N))
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of the Joo and Bueb references to have wherein the first memory request is a compute express link (CXL) request, as taught by the Ki reference.
The suggestion/motivation for doing so would have been to enable coherency within the memories. (Ki, paragraph 90)
Therefore it would have been obvious to combine the Joo, Bueb, and Ki references for the benefits shown above to obtain the invention as specified in the claim.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 7-9 of the remarks) and amendments with respect to the claims have been considered, and are not persuasive. The Applicant argues that Bueb does not disclose, teach, or suggest that “the first command may be fetched after the second command is fetched and a block request is generated by the second command” and “Bueb describes that the first and second commands are in the same queue at the same sequence (e.g., at the same timing)”. The Bueb reference teaches (paragraph 38) where the host system 105 may compare parameters (e.g., a block size or a block number) of different commands of the set of commands to determine which commands of the set are associated with a same L2P table portion. The Bueb reference further teaches (paragraph 14) grouping the first command and the second command together may ensure that the memory system executes the first command and the second command within a short time interval (e.g., time interval below a threshold) and because the first command and the second command may belong to the same L2P mapping portion. Thus, based on the citations above, the Beub reference teaches a “block request” performed by the commands; and that a first command is performed before the second command as they are performed within a short time interval within one another which is analogous to “a second memory request that is fetched by the processor before the first memory request” as claimed. Therefore, the Examiner has maintained the rejections for the reasons set forth above, and contends the prior art of record teaches the invention as broadly and instant claimed.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Alexander (US 20130339650), which teaches issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
4. CLOSING COMMENTS
Conclusion
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137