Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/25/2023, 7/18/2024, 3/27/2025, and 2/12/2026 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (CN 101692595 A).
Regarding Independent Claim 1, Li teaches,
A power supply circuit (See Fig. 1) comprising:
a plurality of direct current direct current (DCDC) converter circuits (Fig. 1, Figure 1 shows the forward-flyback converter); and
a pulse width modulation (PWM) controller (Fig. 1, 180) operatively connected to the plurality of DCDC converter circuits, wherein the PWM controller (Fig. 1, 180) is configured to:
obtain a current voltage of a power amplifier (Fig. 1, 190), obtain a reference voltage for the power amplifier (Fig. 1, 190), generate PWM control signals (Fig. 1, signals from 180) for the plurality of DCDC converter circuits based on a difference between the current voltage and the reference voltage, and provide the PWM control signals (Fig. 1, 180 receives signals from 190 and provide control signals) to the plurality of DCDC converter circuits (See Fig. 1), wherein each DCDC converter circuit of the plurality of DCDC converter circuits comprises:
a transformer (Fig. 1, 140), a primary active clamping circuit (Fig. 1, 120) connected to a primary end of the transformer (Fig. 1, 140), and a secondary resonance converter circuit (Fig. 1, 150 and 160) connected to a secondary end of the transformer (Fig. 1, 140), and wherein the secondary resonance converter circuit comprises a diode (Fig. 1, D2) configured to provide a regeneration current from the secondary end of the transformer (Fig. 1, 140) to an output end of the secondary resonance converter circuit.
Regarding claim 2,
The power supply circuit of claim 1, wherein the secondary resonance converter circuit (Fig. 1, 150 and 160) comprises a resonance circuit (Fig. 1, inductor from 140 and C1) for resonance with a leakage inductance by an inductor of the secondary end of the transformer (Fig. 1, inductor from 140), and wherein the resonance circuit comprises a resonance capacitor (Fig. 1, C1).
Regarding claim 7,
The power supply circuit of claim 1, wherein the primary active clamping circuit (Fig. 1, 120) comprises a first field effect transistor (FET) (Fig. 1, Q1) and a clamp FET (Fig. 1, Q2) for zero-voltage switching (ZVS), wherein the first FET is configured to operate based on the PWM control signal, and wherein the clamp FET is configured to operate based on an inverse signal of the PWM control signal to the clamp FET (See Fig. 6 for control signals of Q1 and Q2).
Regarding claim 9,
The power supply circuit of claim 1, wherein the plurality of DCDC converter circuits (See Fig. 1) are connected in parallel to the PWM controller (Fig. 1, 180), wherein duty cycles of the PWM control signals are equal, and wherein a size of the duty cycles is related to a number of the plurality of DCDC converter circuits (Fig. 1, this is the function typical for interleaved power converters).
Regarding claim 10,
The power supply circuit of claim 9, wherein the PWM control signals (Fig. 1, signals from 180) have different phases, and wherein, based on phases of the PWM control signals that are sequentially aligned within one period (See paragraph [0051]), a phase difference between two adjacent PWM control signals (See Fig. 6 for the control signals) is related to the number of the plurality of DCDC converter circuits (Fig. 1, this is the function typical for interleaved power converters).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 – 6 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Ming-Ching et al. (US 6239989 B1), hereinafter Ming-Ching.
Regarding claim 3, Li is silent regarding:
The power supply circuit of claim 2, wherein the secondary resonance converter circuit comprises a second field effect transistor (FET) and a delay circuit configured to delay a turn-on of the second FET.
Ming-Ching discloses:
The power supply circuit of claim 2, wherein the secondary resonance converter circuit comprises a second field effect transistor (FET) (Fig. 7, SR1 and SR2 are FETs) and a delay circuit configured to delay a turn-on of the second FET (Fig. 7, SR1 and SR2 have an implicit delay for the turn-on.
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Regarding claim 4, Li is silent regarding:
The power supply circuit of claim 3, wherein the secondary resonance converter circuit comprises a synchronous rectifier between the delay circuit and the resonance capacitor.
Ming-Ching discloses:
The power supply circuit of claim 3, wherein the secondary resonance converter circuit (Fig. 7, SR1 and SR2) comprises a synchronous rectifier (Fig. 7, SR1) between the delay circuit and the resonance capacitor (Fig. 7, Cr).
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Regarding claim 5,
The power supply circuit of claim 4, wherein the diode (Fig. 1, D2) is further configured to: clamp a spike voltage that occurs when the second FET is turned off, and pass the regeneration current from the secondary end of the transformer to the output end of the secondary resonance converter circuit (Fig. 1, voltage clamping happens due to the position of D2).
Regarding claim 6, Li is silent regarding:
The power supply circuit of claim 5, wherein the synchronous rectifier further comprises a transistor configured to operate based on a synchronous rectifier (SR) control signal, wherein the SR control signal is generated based on a PWM control signal for a DCDC converter circuit, and wherein the DCDC converter circuit comprises the synchronous rectifier.
Ming-Ching discloses:
The power supply circuit of claim 5, wherein the synchronous rectifier (Fig. 7, SR1) further comprises a transistor (Fig. 7, SR1 is a MOS field effect transistor) configured to operate based on a synchronous rectifier (SR) control signal (Fig. 7, signal controlling SR1), wherein the SR control signal is generated based on a PWM control signal for a DCDC converter circuit (Fig. 7, control signal), and wherein the DCDC converter circuit comprises the synchronous rectifier (Fig. 7, SR1).
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Claims 8, 11, 12, and 17 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Kenington et al. (US 7706467 B2), hereinafter Kenington.
Regarding claim 8, Li is silent regarding:
The power supply circuit of claim 1, wherein, within one period, one control signal among the PWM control signals is activated, and wherein an output of the DCDC converter circuit corresponding to the one control signal among the plurality of DCDC converter circuits is provided to the power amplifier as a drain voltage.
Kenington discloses:
The power supply circuit of claim 1, wherein, within one period, one control signal among the PWM control signals is activated, and wherein an output of the DCDC converter circuit corresponding to the one control signal among the plurality of DCDC converter circuits is provided to the power amplifier as a drain voltage (Fig. 6, 60 supplies energy to the power amplifier as a drain voltage).
Li and Kenington are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a power supply unit in Li‘s design in order to supply energy to the power amplifier as a drain voltage in accordance with Kenington‘s design.
Regarding claim 11, Li discloses:
An electronic device (See Fig. 1) comprising:
a field programmable gate array (FPGA) comprising a digital predistortion (DPD) circuit, a power amplifier;
a plurality of direct current direct current (DCDC) converter circuits (Fig. 1, Figure 1 shows the forward-flyback converter); and
a pulse width modulation (PWM) controller (Fig. 1, 180) operatively connected to the FPGA, the power amplifier, and the DCDC converter circuits, wherein the PWM controller (Fig. 1, 180) is configured to:
obtain a current voltage of the power amplifier (Fig. 1, 190), obtain a reference voltage for the power amplifier (Fig. 1, 190) from the DPD circuit, generate PWM control signals (Fig. 1, signals from 180) for the plurality of DCDC converter circuits based on a difference between the current voltage and the reference voltage, and provide the PWM control signals (Fig. 1, 180 receives signals from 190 and provide control signals) to the plurality of DCDC converter circuits (See Fig. 1), wherein each DCDC converter circuit of the plurality of DCDC converter circuits comprises:
a transformer (Fig. 1, 140), a primary active clamping circuit (Fig. 1, 120) connected to a primary end of the transformer (Fig. 1, 140), and a secondary resonance converter circuit (Fig. 1, 150 and 160) connected to a secondary end of the transformer (Fig. 1, 140), and wherein the secondary resonance converter circuit comprises a diode (Fig. 1, D2) configured to provide a regeneration current from the secondary end of the transformer (Fig. 1, 140) to an output end of the secondary resonance converter circuit.
Li is silent regarding:
a field programmable gate array (FPGA) comprising a digital predistortion (DPD) circuit, a power amplifier;
Kenington discloses:
a field programmable gate array (FPGA) (See Fig. 7) comprising a digital predistortion (DPD) circuit (Fig. 7, 50), a power amplifier (Fig. 7, 10);
Li and Kenington are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a digital predistortion circuit in Li‘s design in order to improves RF power amplifier (PA) efficiency and linearity in accordance with Kenington‘s design.
Regarding claim 12,
The electronic device of claim 11, wherein the secondary resonance converter circuit (Fig. 1, 150 and 160) comprises a resonance circuit (Fig. 1, inductor from 140 and C1) for resonance with a leakage inductance by an inductor of the secondary end of the transformer (Fig. 1, inductor from 140), and wherein the resonance circuit comprises a resonance capacitor (Fig. 1, C1).
Regarding claim 17,
The electronic device of claim 11, wherein the primary active clamping circuit (Fig. 1, 120) comprises a first field effect transistor (FET) (Fig. 1, Q1) and a clamp FET (Fig. 1, Q2) for zero-voltage switching (ZVS), wherein the first FET is configured to operate based on the PWM control signal, and wherein the clamp FET is configured to operate based on an inverse signal of the PWM control signal to the clamp FET (See Fig. 6 for control signals of Q1 and Q2).
Regarding claim 18,
The electronic device of claim 11, wherein, within one period, one control signal among the PWM control signals is activated, and wherein an output of the DCDC converter circuit corresponding to the one control signal among the plurality of DCDC converter circuits is provided to the power amplifier as a drain voltage.
Kenington discloses:
The power supply circuit of claim 11, wherein, within one period, one control signal among the PWM control signals is activated, and wherein an output of the DCDC converter circuit corresponding to the one control signal among the plurality of DCDC converter circuits is provided to the power amplifier as a drain voltage (Fig. 6, 60 supplies energy to the power amplifier as a drain voltage).
Li and Kenington are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a power supply unit in Li‘s design in order to supply energy to the power amplifier as a drain voltage in accordance with Kenington‘s design.
Regarding claim 19,
The electronic device of claim 11, wherein the plurality of DCDC converter circuits (See Fig. 1) are connected in parallel to the PWM controller (Fig. 1, 180), wherein duty cycles of the PWM control signals are equal, and wherein a size of the duty cycles is related to a number of the plurality of DCDC converter circuits (Fig. 1, this is the function typical for interleaved power converters).
Regarding claim 20,
The electronic device of claim 19, wherein the PWM control signals (Fig. 1, signals from 180) have different phases, and wherein, based on phases of the PWM control signals that are sequentially aligned within one period (See paragraph [0051]), a phase difference between two adjacent PWM control signals (See Fig. 6 for the control signals) is related to the number of the plurality of DCDC converter circuits (Fig. 1, this is the function typical for interleaved power converters).
Claims 13 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Kenington in view of Ming-Ching et al. (US 6239989 B1), hereinafter Ming-Ching.
Regarding claim 13,
The electronic device of claim 12, wherein the secondary resonance converter circuit comprises a second field effect transistor (FET) and a delay circuit configured to delay a turn-on of the second FET.
Ming-Ching discloses:
The power supply circuit of claim 12, wherein the secondary resonance converter circuit comprises a second field effect transistor (FET) (Fig. 7, SR1 and SR2 are FETs) and a delay circuit configured to delay a turn-on of the second FET (Fig. 7, SR1 and SR2 have an implicit delay for the turn-on.
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Regarding claim 14,
The electronic device of claim 13, wherein the secondary resonance converter circuit comprises a synchronous rectifier between the delay circuit and the resonance capacitor.
Ming-Ching discloses:
The power supply circuit of claim 3, wherein the secondary resonance converter circuit (Fig. 7, SR1 and SR2) comprises a synchronous rectifier (Fig. 7, SR1) between the delay circuit and the resonance capacitor (Fig. 7, Cr).
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Regarding claim 15,
The electronic device of claim 14, wherein the diode (Fig. 1, D2) is further configured to: clamp a spike voltage that occurs when the second FET is turned off, and pass the regeneration current from the secondary end of the transformer to the output end of the secondary resonance converter circuit (Fig. 1, voltage clamping happens due to the position of D2).
Regarding claim 16,
The electronic device of claim 15, wherein the synchronous rectifier further comprises a transistor operating based on a synchronous rectifier (SR) control signal, wherein the SR control signal is generated based on a PWM control signal for a DCDC converter circuit, and wherein the DCDC converter circuit comprises the synchronous rectifier.
Ming-Ching discloses:
The power supply circuit of claim 5, wherein the synchronous rectifier (Fig. 7, SR1) further comprises a transistor (Fig. 7, SR1 is a MOS field effect transistor) configured to operate based on a synchronous rectifier (SR) control signal (Fig. 7, signal controlling SR1), wherein the SR control signal is generated based on a PWM control signal for a DCDC converter circuit (Fig. 7, control signal), and wherein the DCDC converter circuit comprises the synchronous rectifier (Fig. 7, SR1).
Li and Ming-Ching are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a FET in Li‘s design in order to function as diodes and field effect transistors with a turn-on delay in accordance with Ming-Ching‘s design.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE E PINERO whose telephone number is (703)756-4746. The examiner can normally be reached M-F 8:00 AM - 5:00 PM (ET).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843