Prosecution Insights
Last updated: October 02, 2026
Application No. 18/238,459

COMPUTING PLATFORM, METHOD, AND APPARATUS FOR SPIKING NEURAL NETWORK LEARNING AND SIMULATION

Final Rejection §102
Filed
Aug 26, 2023
Priority
May 19, 2022 — CN 202210541154.6 +1 more
Examiner
NILSSON, ERIC
Art Unit
2151
Tech Center
2100 — Computer Architecture & Software
Assignee
Zhejiang University
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
430 granted / 520 resolved
+27.7% vs TC avg
Strong +18% interview lift
Without
With
+17.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
24 currently pending
Career history
535
Total Applications
across all art units

Statute-Specific Performance

§101
27.2%
-12.8% vs TC avg
§103
41.8%
+1.8% vs TC avg
§102
14.5%
-25.5% vs TC avg
§112
8.5%
-31.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 520 resolved cases

Office Action

§102
DETAILED ACTION This action is in response to claims filed 11 June 2026 for application 18238459 filed 26 August 2023. Currently claims 1, 3, 6-9 and 11 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 7-9 and 11 are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Fang et al. (Encoding, model, and architecture: systematic optimization for spiking neural network in FPGAs). Regarding claim 7, Fang discloses: A method for SNN learning and simulation, comprising following steps: step S1: judging whether there is a need to read a network structure from a file, and if yes, directly performing step S5 to construct a network after the network structure is read; and if not, building the network structure anew, setting a network running time, and performing step S2 (Fig 6); step S2: constructing an input layer, and adopting different processing manners for input data according to different input manners selected (§3.2 discloses parts of a SNN including input nodes for an input layer, Fig 6 SNN specification); step S3: constructing a neuron layer in the form of neuron groups, defining a model used by each neuron group, a number of neurons comprised in the model, and specific model details, converting a differential equation of the neurons, and adding a difference equation obtained after conversion to a calculation graph (§3.2 discloses parts of a SNN including input nodes for an input layer, “Equation 18 to 23 provide an explicit way to update the state of SNN based on difference equations, hence it is convenient to implement in FPGAs.” P5§3.2 ¶3, eq18-23 disclose difference equations, “A computation graph is generated from the inference model. Each node indicates a stage in the layer-wise pipeline. Edge direction indicates data dependency. Node’s attributes include hyperparameter such as type, input/output size etc. of corresponding layer.” P7 §4.3 ¶2); step S4: constructing a connection layer, selecting a synapse type, initializing connection weights at the same time, integrating information required to be passed to post-synaptic neurons after connection weight calculation, and adding the integrated information to the calculation graph (§3.2 discloses parts of a SNN including neurons and synapses, “Equation 18 to 23 provide an explicit way to update the state of SNN based on difference equations, hence it is convenient to implement in FPGAs.” P5§3.2 ¶3, eq18-23 disclose synapses and connections weights, A LIF neuron can be made by setting some parameters to 0, “A computation graph is generated from the inference model. Each node indicates a stage in the layer-wise pipeline. Edge direction indicates data dependency. Node’s attributes include hyperparameter such as type, input/output size etc. of corresponding layer.” P7 §4.3 ¶2); step S5: constructing a network, assigning IDs representing categories and parent classes to each neuron group and connection in sequence, and then generating a specific calculation graph based on the IDs (“A computation graph is generated from the inference model. Each node indicates a stage in the layer-wise pipeline. Edge direction indicates data dependency. Node’s attributes include hyperparameter such as type, input/output size etc. of corresponding layer.” P7 §4.3 ¶2); and step S6: simulating operation of the network, the neurons changing with time and settings of a neuron model, performing step-by-step calculation according to the calculation graph, and storing a trained network structure and parameters (“Each 𝑖𝑡𝑒𝑟𝑎𝑡𝑖𝑜𝑛 is defined as executing equation 18 to 23 once to update SNN states. 𝑇𝑖 is the cycles required by the 𝑖𝑡ℎ layer to update the for one step, and 𝐹𝑟𝑒𝑞 is the system clock frequency. At lower level, the resources in each module (i.e. synapse, matrix multiplication and convolution and thresholding) are shared by neurons in the same layer in a time multiplexed way.” P7 §4.2 ¶2). in step S6, adding a monitor to monitor parameters of specified neurons, displaying the parameters visually, and storing displayed information (Fig 1 time encoding by LIF neuron). Regarding claim 8, Fang discloses: The method for SNN learning and simulation of claim 7, wherein, when the input layer is constructed in step S2, if the input data is given spike data, using the input data is directly as spike input; if an encoding manner is given, encoding the input data according to different encoding manners and then inputting the input data; and otherwise, constructing different constant input currents or quadrature input currents as input according to the input data §3.2 discloses parts of a SNN including input nodes for an input layer, “In SNN, static data e.g. images have to be converted as spike trains in an encoding window 𝑇𝑒 for processing. Larger 𝑇𝑒 provides better precision, but at the cost of longer computation time. To evaluate the effectiveness of proposed coding method and SNN model, we studied the trade-off between𝑇𝑒 and accuracy.” P7 §5.1 ¶1). Regarding claim 9, Fang discloses: The method for SNN learning and simulation of claim 7, wherein the synapse type in step S4 comprises a chemical synapse and an electrical synapse, and calculation formulas of different synapse types are added to the connection layer to construct connections (§3.2 eq 18-23 and the notation parameters that can be set to zero disclose different types of neurons and synapses such as those in a LIF neuron). Regarding claim 11, Fang discloses: An apparatus for SNN learning and simulation, comprising a non-volatile memory, and one or more processors, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the method for SNN learning and simulation of claim 7 (p9 §6 various computer devices can be used to implement the SNN, “We tested the three networks on CPU, GPU, embedded GPU, and neuromorphic chip, and results are shown in Table 3” §5.3 ¶2). Response to Arguments Applicant’s arguments, see pp6-10, filed 11 June 2026, with respect to the rejections under 35 USC 102, 103 and 112b of claims 1-6 have been fully considered and are persuasive. The rejections under 35 USC 102, 103 and 112b of claims 1-6 have been withdrawn. Applicant's arguments filed 11 June 2026 have been fully considered but they are not persuasive. The arguments presented do not directly apply to claim 7 as claim 7 does not recited setting a current and/or voltage nor a greyscale image. Fang discloses a monitor of a neuron in Figure 1. No specific argument has been presented for why this is not disclosed other than a statement that it is not disclosed. Allowable Subject Matter Claims 1, 3 and 6 are allowed. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC NILSSON whose telephone number is (571)272-5246. The examiner can normally be reached M-F: 7-3. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)-272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC NILSSON/Primary Examiner, Art Unit 2151
Read full office action

Prosecution Timeline

Aug 26, 2023
Application Filed
Mar 13, 2026
Non-Final Rejection mailed — §102
Jun 11, 2026
Response Filed
Jul 15, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+17.6%)
3y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 520 resolved cases by this examiner. Grant probability derived from career allowance rate.

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