DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 9/17/2026 has been entered.
Claims 1-20 and 22 are presented for examination. Claims 1-20 have been amended. Claims 22 has been added. Claim 21 has been cancelled.
Applicant’s amendments to the claims have overcome 112 rejections previously set forth in the Final Office Action mailed 6/18/2026.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding to Claim 1, the amended limitation “identify, using the processor, responsive to identification of the change to the pattern, at least one portion of plurality of memory devices to allocate for a given action of the actions” lacks support from the specification. At the Remarks, Applicant stated that “for example at least at paragraphs [0010], [0020], [0022]-[0026], [0032], [0034]-[0039], [0057], [0062], and [0069]-[0072] of the present application” can be used as support for the amendments made (see 1st paragraph of page 13 from the Remarks). Among these paragraphs,
Paragraphs [0010], [0020], [0022], [0036]-[0038] and [0057] do not even describe change to the pattern, and thus these paragraphs are not support for the amended limitation mentioned above.
Paragraphs [0023]-[0024], [0026], [0032] do mention about detecting or identifying difference or diversion or change of patterns among two pluralities of messages; however, when incorporating each feature from these paragraphs into the amended claim 1, one with ordinary skill in the art would find that the corresponding steps/process from these paragraphs are applied to the claimed second plurality of messages instead of the claimed first plurality of messages (note: the amended limitation mentioned above states that “identify … to allocate for a given action of the actions” wherein such claimed “the actions” according to current claim 1 is defined or required as “identify, actions for each message of the first plurality of messages, the actions including at least one of updates to the plurality of datasets or access of the plurality of datasets”). In this way, these paragraphs are not support for the amended limitation mentioned above.
Paragraphs [0034], [0039], [0069] do describe feature of identifying portion of memory devices to allocate for given action associated with claimed first plurality of message; however, such identification is performed based on or in response to the pattern instead of “change to the pattern” as required. In this way, these paragraphs are not support for the amended limitation mentioned above.
Paragraphs [0025], [0035] [0072] do describe feature of identifying portion of memory devices for given action associated with claimed first plurality of messages in response to change in the pattern; however, the identified portion of memory devices from these paragraphs are deallocated instead of to be allocated. In this way, these paragraphs are not support for the amended limitation mentioned above.
Paragraphs [0039] [0062], [0070]-[0071] at most discuss identifying the change to the pattern without discussing identifying portion of memory devices to allocate for action associated with claimed first plurality of messages. In this way, these paragraphs are not support for the amended limitation mentioned above.
Thereby, none of these paragraphs from the specification provide sufficient evidence to support the amended limitation mentioned above. In addition, examiner did not find any other sufficient descriptions from the specification to support the amended limitation mentioned above. In this way, this particular amended limitation is new matter.
Claims 2-9 and 22 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition,
For claim 6, the amended limitation “process, using the processor, using the at least one portion of the plurality of memory devices, at least one message of a third plurality of messages” is new matter. As explained at the rejection of claim 1 above, the specification describes particular feature of deallocating a portion of memory devices in response to identifying change to the pattern (that such pattern after change is identified based on characteristics of the claimed second plurality of messages, and such pattern before the change is determined as pattern associated with the claimed first plurality of messages, i. e., the change to the pattern here is based on comparison between characteristics of claimed first and second pluralities of messages) and using such deallocated portion of memory devices to process claimed second plurality of messages. However, the current claim 6 now requires using such deallocated portion of memory devices to process claimed third plurality of messages instead of claimed second plurality of messages (note: one with ordinary skill in the art would understand that the specification does support a feature of deallocating a portion of memory devices to be allocated for processing claimed third plurality of messages; however, such particular portion of memory devices should be identified in response to identification of particular change to the pattern based on comparison between characteristics of third and first/second pluralities of messages). In this way, the amended limitation mentioned above is new matter.
Regarding to Claim 10, Claim 10 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 11-17 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition, claim 15 is rejected under the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 18, Claim 18 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 19-20 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition, claim 20 is rejected under the same reason set forth in the rejection of Claim 6 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding to Claim 1, the intended meaning of amended limitation “identify, using the processor, responsive to identification of the change to the pattern, at least one portion of plurality of memory devices to allocate for a given action of the actions” is not clear. As explained at the corresponding 112(a) rejection of claim 1 above, the specification does not support the amended limitation above and the specification does provide certain features including:
(1) identifying portion of memory devices to be allocated for claimed given action in response to the claimed pattern,
(2) identifying portion of memory devices to be deallocated for the claimed given action in response to the claimed change to the pattern
(3) identifying portion of memory device to be allocated for the claimed second plurality of messages, in response to the claimed change to the pattern.
It is not clear that Applicant intended to amend claim 1 as currently presented OR Applicant intended to amend claim to include one of the three features supported by the specification (but Applicant made some typos to result current amended limitation). For the purpose of examination, examiner interprets the amended limitation mentioned above as:
identify, using the processor, responsive to identification of the change to the pattern, at least one portion of plurality of memory devices to deallocate for a given action of the actions
Claims 2-9 and 22 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition,
For claim 6, the intended meaning of amended limitations “processing, by the one or more circuits using the processor, using the at least one portion of the plurality of memory devices, at least one message a third plurality of messages” is not clear. Similar as explained at the 112 (b) rejection of claim 1 above, it is not clear that Applicant intended to amend claim 6 as currently presented OR Applicant intended to amend claim to include features that supported by the specification but Applicant made some typos to result current amended limitation. For the purpose of examination, examiner interprets the amended limitation mentioned above as:
processing, by the one or more circuits using the processor, using the at least one portion of the plurality of memory devices, at least one message the second plurality of messages.
Regarding to Claim 10, Claim 10 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 11-17 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition, claim 15 is rejected under the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 18, Claim 18 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 19-20 are rejected for failing to cure the deficiency from their respective parent claim by dependency. In addition, claim 20 is rejected under the same reason set forth in the rejection of Claim 6 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-16, 18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Baderdinni et al. (US 20130124780 A1, hereafter Baderdinni).
Regarding to claim 1, Kotte discloses: A system (see [0005]), comprising:
a plurality of memory devices storing a plurality of datasets, each memory device of the plurality of memory devices comprising a physical medium for storing the plurality of datasets (see Fig.1, [0042] and [0045]; “storage medium 130 includes a plurality of flash memory devices” and “Storage medium 130 is divided into a number of addressable and individually selectable blocks, such as selectable portion 131 …. where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some implementations (e.g., using some types of flash memory), the smallest individually accessible unit of a data set”); and
a device in communication with the plurality of memory devices and a host (see Fig. 1 and [0047]; “storage controller 124 includes a management module 121, a host interface 129, a storage medium interface (I/O) 128 … Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 130 though connections 103”. Also see [0043]; “Computer system 110 is sometimes called a host or host system”), the device comprising:
one or more circuits comprising a processor and memory, and the one or more circuits (see Figs. 1, 2A, [0048]-[0049] and [0058]-[0068]; “Management module 121 typically includes one or more processing units (CPUs) 122 for executing modules, programs and/or instructions stored in memory 206 and thereby performing processing operations”) configured to:
receive, from the host, a first plurality of messages pertaining to the plurality of datasets (see [0059]; “I/O receiving module 210 that is used for receiving from a host a plurality of input/output (I/O) requests (e.g., read requests and/or write requests)”. Also see [0044] and [0050]-[0051] for the I/O requests mentioned at [0059] are I/O requests/messages pertaining to the datasets of storage medium 130);
determine, using the processor, responsive to receipt of the first plurality of messages, an amount of information include in each dataset of the plurality of datasets (see [0078] and [0088]; “tracking a total number of write requests to write data of size less than a predefined small-size threshold” and “tracking a total number of write requests to write data of size greater than a predefined large-size threshold”. In order to perform such two tracking, it is required to determine corresponding amount/size of data or information to be written, i.e., amount/size of data included in each of the datasets, then comparing such amount/size of data or information to the corresponding threshold value. Note: claimed “an amount of information included in each dataset” is broad and such claimed amount is not necessary to be interpreted as total amount or size of information inside each dataset. Also see [0089]; “if a storage device with an advertised capacity of 1 terabyte (TB) is divided into m regions, each region will be (1 TB)/m in size”);
identify, using the processor, based on characteristics of the first plurality of messages, actions for each message of the first plurality of messages, the actions including at least one of updates to the plurality of datasets or accesses of the plurality of datasets (see [0100]; “to receive from the host a plurality of I/O requests, as described above with respect to FIG. 2A. The I/O requests specify operations (sometimes called storage operations or memory operations) to be performed with respect to logical addresses in a plurality of regions in a logical address space of a host”. Also see [0061]-[0064]. There are at least four types of different operations/actions of reading, writing, erasing, garbage collection to be specified and then determined for performing);
update, using the processor, based on the amount of information and the actions, a table located in the memory to reflect receipt of the first plurality of messages (see [0066]; “history table 224 that includes a collection of data structures (e.g., region data structures 244, FIG. 2B), each data structure storing data for a respective region of a plurality of regions in a logical address space of a host”);
determine, using the processor, responsive to updating the table, a pattern associated with the first plurality of messages, the pattern indicating total number of messages included in the first plurality of messages (see [0018]-[0019], [0076], [0083]; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region” and “hot region flag 264 that is used for tracking whether a total number of write requests to the region has exceeded a write threshold”. Note: current claim only requires determine a pattern that indicating total number of messages included in the claimed first plurality of messages without specifying what kind of messages to be counted for such total number and whether the pattern indicating just numeric value of such total number of message OR the pattern indicates such state/status of such total number of messages, and thus a BRI of such claimed invention can be a total number of xx type of messages included in the claimed first plurality of message, and thus the either one of hot region flag, sequential read count or the combination of these two is still reasonable to be considered as claimed “the pattern indicating total number of messages included in the first plurality of messages);
receive, from the host, a second plurality of messages pertaining to the plurality of datasets (see [0124]; “subsequent to maintaining the history of I/O request patterns in the region for the predetermined time period, maintains (618) a second history of I/O request patterns in the region for a next instance of the predetermined time period (i.e., a period of time immediately following the predetermined period of time, and having the same duration as the predetermined period of time) … The embodiments described herein for maintaining the history of I/O request patterns in the region for the predetermined time period are equally applicable to maintaining a second history of I/O request patterns in the region for a next instance of the predetermined time period”. There is a second plurality of I/O requests or messages received, and such second plurality of I/O requests are messages are handled as same as the first plurality of I/O requests or messages received before this second plurality of I/O requests or messages as explained above);
monitor, using the processor, responsive to receipt of a second plurality of messages, the pattern based on characteristics of the second plurality of messages (see [0093] from Kotte; “if a region (e.g., region 310-1, FIG. 3) is not marked with a hot region indicator, in some embodiments, subsequent write requests to that region are written to an active block (sometimes referred to as an active “cold block,” as opposed to an active hot block)”. Also see [0124]; “subsequent to maintaining the history of I/O request patterns in the region for the predetermined time period, maintains (618) a second history of I/O request patterns in the region for a next instance of the predetermined time period (i.e., a period of time immediately following the predetermined period of time, and having the same duration as the predetermined period of time) … The embodiments described herein for maintaining the history of I/O request patterns in the region for the predetermined time period are equally applicable to maintaining a second history of I/O request patterns in the region for a next instance of the predetermined time period”).
Kotte does not disclose:
identify, using the processor, a change to the pattern; and
identify, using the processor, responsive to identification of the change to the pattern, at least one portion of plurality of memory devices to allocate for a given action of the actions.
However, Baderdinni discloses:
receive, a first I/O request pertaining to the plurality of datasets; determine a pattern associated with the first I/O request; receive a second I/O request pertaining to the datasets; monitor, using the processor, responsive to receipt of the second I/O request, the patterns based on characteristics of the second I/O request; identify, using the processor, a change to the pattern (see [0022]; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold”. The description of “as different data is access over time” from [0022] implies there are different I/O requests or messages are received and processed over time, i.e., there is at least first I/O request or message and second/subsequent I/O request/message received at different time points, identifying change to the patterns indicating the hotness of a given data, i.e., I/O request or message number to access this given data, associated with corresponding I/O requests or messages); and
identify, using the processor, responsive to identification of the change to the pattern, at least one portion of plurality of memory devices to allocate for a given action of the actions (see [0022]; “data access patterns may change, causing previously cold data to become hot and previously hot data to become cold. A tiered data storage system must therefore migrate data from the slow tier to the fast tier as previously cold data becomes hot. Because the fast tier is relatively small, data which has become cold over time may need to be migrated to the slow tier to free capacity on the fast tier”. In response to the patten indicating hotness of a given data changes, the corresponding data is migrated to corresponding tier, i.e., the portion of memory devices having the corresponding data allocated for previous/former I/O requests is deallocated).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the data accesses to hot and cold data from Kotte by including migrating corresponding data to corresponding tier in response to hotness of the corresponding data changes, and thus the combination of Kotte and Baderdinni would disclose the missing limitations from Baderdinni, since it would provide a mechanism of ensuring there is enough space at the fast tier to store hot data to maintain storage access efficiency (see [0002], [0022] from Baderdinni; “overall system performance is improved by moving data that is frequently accessed (hot data) to faster and more capable drives and at the same time moving less frequently accessed data (cold data) to less capable slow storage” and “Because the fast tier is relatively small, data which has become cold over time may need to be migrated to the slow tier to free capacity on the fast tier”).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein the total number of messages includes a first number of messages pertaining to the updates to the plurality of datasets (see [0018] and [0063] from Kotte; “hot region flag 264 that is used for tracking whether a total number of write requests to the region has exceeded a write threshold”) and a second number of messages pertaining to the accesses of the plurality of datasets (see [0019] and [0076] from Kotte; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region”).
Regarding to Claim 3, the rejection of Claim 2 is incorporated and further the combination of Kotte and Baderdinni discloses: identify, using the processor, based on characteristics of the second plurality of messages, actions for respective messages of the second plurality of message (see [0100] from Kotte; “to receive from the host a plurality of I/O requests, as described above with respect to FIG. 2A. The I/O requests specify operations (sometimes called storage operations or memory operations) to be performed with respect to logical addresses in a plurality of regions in a logical address space of a host”. Also see [0124] from Kotte and explanation at claim 1 above. As explained above, there are second plurality of I/O requests/messages received, and such second plurality of I/O requests/messages are handled as same as the first plurality of I/O requests/messages received to identify what kind of I/O actions is required for the received I/O requests/messages); and
identify, using the processor, responsive to identification of the change to the pattern, a second plurality of memory devices to divert at least one message of the second plurality of messages (see [0022] from Baderdinni; “data access patterns may change, causing previously cold data to become hot and previously hot data to become cold. A tiered data storage system must therefore migrate data from the slow tier to the fast tier as previously cold data becomes hot”. In response to detected hotness of data change, migrating corresponding data to corresponding tier of memory devices, and thus the new location/tier of memory devices is used to server the subsequent I/O requests/messages, i.e., claimed second plurality of messages).
Regarding to Claim 4, the rejection of Claim 2 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein the one or more circuits are further configured to: update, using the processor, responsive to a diversion of at least one message of a second plurality of messages, a second table located in the memory to reflect the diversion; determine, using the processor, based on the second table, that a number of diversion of exceeds a threshold; and execute, using the processor, responsive to determination that the number of diversions exceeds the threshold, one or more actions to address the number of diversions (see [0018], [0083] from Kotte and [0022] from Baderdinni; “maintaining the history of I/O request patterns in the region includes tracking whether a total number of write requests to the region has exceeded a write threshold”, “hot region flag 264 that is used for tracking whether a total number of write requests to the region has exceeded a write threshold” and “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold. A tiered data storage system must therefore migrate data from the slow tier to the fast tier as previously cold data becomes hot”. Updating at least the information related to tracking whether total number of write requests to region has exceeded a write threshold or hot region flag at the corresponding table in response to detect a cold data is accessed more frequently or a hot data is accessed less frequently, i.e., diversion of the subsequent/second plurality of I/O requests, when such cold data is accessed more than the write threshold or such hot data is accessed less than the write threshold discussed [0018] from Kotte, at least actions of hot region flag 264 is updated and migrating the corresponding data to corresponding tier are performed to address such diversions).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein the one or more circuits are further configured to:
detect, using the processor, a number of instances pertaining to utilization of the at least one portion of the plurality of memory devices by the one or more second actions (see [0093] from Kotte; “if a region (e.g., region 310-1, FIG. 3) is not marked with a hot region indicator, in some embodiments, subsequent write requests to that region are written to an active block (sometimes referred to as an active “cold block,” as opposed to an active hot block)”. Also see [0124]; “subsequent to maintaining the history of I/O request patterns in the region for the predetermined time period, maintains (618) a second history of I/O request patterns in the region for a next instance of the predetermined time period (i.e., a period of time immediately following the predetermined period of time, and having the same duration as the predetermined period of time) … The embodiments described herein for maintaining the history of I/O request patterns in the region for the predetermined time period are equally applicable to maintaining a second history of I/O request patterns in the region for a next instance of the predetermined time period”);
identify, using the processor, responsive to detection of the number of instances, a change to the pattern (see [0022] from Baderdinni; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold”. The description of “as different data is access over time” from [0022] implies there are a number of new instances of I/O requests are detected to use old data to cause the old data becomes hold data now).
Regarding to Claim 6, the rejection of Claim 5 is incorporated and further the combination of Kotte and Baderdinni discloses: deallocate, using the processor, responsive to identification of the change to the pattern, the at least one portion of the plurality of memory devices; and process, using the processor, using the at least one portion of the plurality of memory devices, at least one message of a third plurality of messages (see [0022] from Baderdinni; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold. A tiered data storage system must therefore migrate data from the slow tier to the fast tier as previously cold data becomes hot”. Migrating the corresponding data to corresponding tier based on hostess of data changes, i.e., deallocating the corresponding tier of memory device for the original data, to allow such deallocated tier of memory device to server/process new data associated with subsequent plurality of message).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: a first message of the first plurality of messages pertains to a first dataset of the plurality of datasets having a first amount of information; the first message of the first plurality of messages is associated with an update to the first dataset (see [0022] from Kotte; “maintaining the history of I/O request patterns in the region includes tracking a total number of write requests to write data of size less than a predefined small-size threshold”. Among the I/O requests received, there is one write/update request is related to a write/update operation to a dataset having data size less than the predefined small-size threshold); and
the one or more circuits are configured to reflect receipt of the first message of the first plurality of messages by:
updating, using the processor, a first entry of the table from a first value to a second value, wherein the second value accounts for receipt of the first message; and updating, using the processor, a second entry of the table from a third value to a fourth value, wherein the fourth value accounts for receipt of the first message (see [0022] and [0078] from Kotte; “maintaining the history of I/O request patterns in the region includes tracking a total number of write requests to write data of size less than a predefined small-size threshold” and “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold”. Among the I/O requests received, there is one write/update request is related to a write/update operation to a dataset having data size less than the predefined small-size threshold. In response to receive and handle such write/update request, the small write count 254 is incremented. Note: none of the claimed limitations of claim 7 now requires claimed first value is a number different from claimed third value and claimed second value is a number different from claimed fourth value).
Note: Also see [0078]-[0079] from Kotte; “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold; unaligned write count 256 that is used for tracking a total number of unaligned write requests to the region, wherein unaligned write requests are write requests not aligned with predefined page boundaries”. It is possible that one single write operation would cause both of small write count 254 and unaligned write count 256 are incremented, i.e., such single write operation is a writing operation that a dataset to be written has small size and such dataset is aligned with predefined page boundaries. In this way, the increment of small write count 254 can be considered as updating claimed third value to claimed fourth value and the increment of unaligned write count 256 can considered as updating claimed first value to claimed second value while such four values are not necessarily same.
Regarding to Claim 9, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein the table includes a plurality of portions (see Fig. 2B and [0071]-[0087] from Kotte; “History table 224 includes a collection of region data structures 244, that each store data associated with a respective region of a plurality of regions in a logical address space of a host” and “region data structure 244-i stores the following data (sometimes called history of I/O requests for a particular time period, for a particular region of the logical address space), or a subset or superset”. Note: claimed a plurality of portions now is a very broad concept, the different region data structures can be considered as such claimed a plurality of portions while each different count/information of one single region data structure 244-i can also be considered as such claimed a plurality of portions) and wherein the one or more circuits are configured to update, using the processor, the table located in the memory to reflect receipt of the plurality of messages by:
updating, using the processor, responsive to detection of a first message of the first plurality of messages indicating a first update to a first dataset of the plurality of datasets, a first portion of the plurality of portions to include an indication of receipt of the first message (see [0077] from Kotte; “sequential write count 252 that is used for tracking a total number of sequential write requests to the region”. There is a reasonable embodiment of detecting a I/O request is actually a first write/update operation among a number of sequential write requests);
updating, using the processor, responsive to detection of a second message of the first plurality of messages indicating a first access of a second dataset of the plurality of datasets, a second portion of the plurality of portions to include an indication of receipt of the second message (see [0076] from Kotte; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region”. There is a reasonable embodiment of detecting a I/O request is actually a first read operation among a number of sequential read requests);
updating, using the processor, based on an amount of information associated with at least one of the first message or the second message, a third portion of the plurality of portions to reflect an indication of at least one of the first message or the second message corresponding to the amount of information (see [0078] from Kotte; “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold”. There is a reasonable embodiment of the detected first write/update operation among a number of sequential write request is actually a write/update operation that writing a dataset has size of less than predefined small-size threshold); and
updating, using the processor, a fourth portion of the plurality of portions to indicate an indication of the first message and an indication of the second message (see [0074] from Kotte; “lowest LBA accessed 246 that is used for tracking a lowest logical block address (LBA) accessed in the region”. There is a reasonable embodiment of both of detected first write/update operation among a number of sequential write/update operations and detected first read operation among a number of sequential read operations are access with a lowest logical block address (LBA) accessed in the region. Note: none of the current claimed limitations would require claimed first dataset and claimed second dataset must be two different datasets. Even if Applicant intends to interprets such claimed first and second datasets are two different datasets, the claimed updating fourth portion to indicate an indication of the first message and an indication of the second message can be updating the same region data structure region 244-i of Fig. 2B from Kotte).
Regarding to Claim 10, Claim 10 is rejected for the same reason set forth in the rejection of Claim 1 above.
Regarding to Claim 11, Claim 12 is rejected for the same reason set forth in the rejection of Claim 2 above.
Regarding to Claim 12, Claim 12 is rejected for the same reason set forth in the rejection of Claim 3 above.
Regarding to Claim 13, Claim 13 is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 14, Claim 14 is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 15, Claim 15 is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 16, Claim 16 is rejected for the same reason set forth in the rejection of Claim 7 above.
Regarding to Claim 18, Claim 18 is a method claim corresponds to system Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above.
Regarding to Claim 19, Claim 19 is a method claim corresponds to system Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 20, Claim 20 is a method claim corresponds to system Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 21, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein identification of the change to the pattern is based on one or more differences between the characteristics of the first plurality of messages and the characteristics of the second plurality of messages, and wherein the one or more differences include at least one of: a difference between a rate at which the first plurality of messages were received and a rate at which the second plurality of messages are received; or a difference between the total number of number of messages included in the first plurality of messages and a total number of messages included in the second plurality of messages (see [0022] from Baderdinni; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold”. Also see [0018], [0083] and [0090] from Baderdinni; “if a total number of write requests to region 310-1 has exceeded a write threshold during a predetermined time period, region 310-1 is marked with a hot region indicator (e.g., using hot region flag 264, FIG. 2B)”).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Baderdinni et al. (US 20130124780 A1, hereafter Baderdinni) and further in view of Pellicone et al. (US 7571362 B2, hereafter Pellicone).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further the combination of Kotte and Baderdinni discloses: wherein the one or more circuits are further configured to:
execute, using the processor, one or more actions to process one or more messages of the first plurality of messages (see [0071] from Kotte; “the storage device gathers data as I/O requests are processed”. Also see [0018]-[0033] from Kotte; there are multiple different types of I/O requests or actions, and thus it is reasonable to conclude there is at least a third type of action from the I/O requests in addition to first type of actions and second type of actions. Note: it is understood that “sequential write requests”, “unaligned write requests”, “write requests to write data of size less than a predefined small-size threshold” and “write requests to write data of size greater than a predefined large-size threshold” can be different types of writing I/O requests or actions).
The combination of Kotte and Baderdinni does not disclose: detect, using the processor, responsive to execution of the one or more actions, at least one message of the one or more messages associated with a memory device of the plurality of memory devices that includes a bad block; and
update, using the processor, responsive to detection of the at least one message, a second table located in the memory corresponding to one or more memory devices of the plurality of memory devices with bad blocks from a first size to a second size to account for the memory device including the bad block.
However, Pellicone discloses: detect, using the processor, responsive to execution of the one or more actions, at least one message of the one or more messages associated with a memory device of the plurality of memory devices that includes a bad block (see claim 1; “determining, during operation of the non-volatile memory device, a failure of a block of cells previously not marked as bad”); and
update, using the processor, responsive to detection of the at least one message, a second table located in the memory corresponding to one or more memory devices of the plurality of memory devices with bad blocks from a first size to a second size to account for the memory device including the bad block (see claim 1; “updating the bad block address table in the embedded random access memory based at least in part on said determining of the failure of the block”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the history table 224 from the combination of Kotte and Baderdinni by including a bad block address table from Pellicone, and thus the combination of Kotte, Baderdinni and Pellicone would disclose the missing limitations from the combination of Kotte and Baderdinni, since it would provide additional table or data structure to show information of bad blocks to avoid accessing to these bad blocks (see claim 1 from Pellicone; “looking up the bad block address table copied in the embedded random access memory to determine whether a block of the first subset addressed by the user is bad and, if so, remapping access to a corresponding block of redundancy data storage cells”).
Regarding to Claim 17, Claim 17 is rejected for the same reason set forth in the rejection of Claim 8 above.
Response to Arguments
Applicant’s arguments, filed 9/17/2026, with respect to rejections of claims 1-20 and 22 under 35 U.S.C. 103 have been full considered. New grounds of rejections are made based on amended limitations from the independent claims.
Conclusion
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
