DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to Applicant’s Amendment filed on 3/25/2026.
Claims 1-21 are presented for examination. Claims 1-2, 4-11 and 13-20 have been amended. Claims 21 have been added.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding to Claim 1, the amended limitation “allocate to one or more second actions of the actions to provide additional portions of the plurality of memory devices to the one or more actions beyond what was originally allocated to the one or more second actions” lacks support from the specification. Such amended limitation requires there are two different portions memory devices are allocated to the second actions, i.e., “additional portions” and “originally allocated” portion. However, there is no support from the specification to describe such feature. At the Remarks, Applicant stated that [0008]-[0012] and [0068]-[0070] of the present application provide support for the amendments (see 1st paragraph of page 13 from the Remarks). However, [0008]-[0012] does not discuss anything about allocating additional resources or memory devices. [0008]-[0012] at most discuss “a controller to toggle write coalescing (e.g., allocate and deallocated memory space) based on predicted utilization”. Such allocation and deallocation of memory space is not necessary to include feature of allocating additional resources. [0069] does discuss feature of allocating deallocated resources to certain write requests; however, nothing from [0068]-[0070] requires or implies such “write requests” have resource “what was originally allocated to”. [0068] does discusses “a second portion of the table 130 may pertain to messages that pertain to a second array 203”; however, nothing from [0068]-[0070] requires or implies such “second portions” “pertain to messages” are resources that already or originally allocated to certain actions or requests. In this way, the features related to there was resource “what was originally allocated to the one or more second actions” in addition to “additional portions of the plurality of memory devices” lack support from the specification and are new matter.
Claims 2-9 and 21 are rejected for failing to cure the deficiency from their respective parent claim by dependency.
Regarding to Claim 10, Claim 10 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 11-17 are rejected for failing to cure the deficiency from their respective parent claim by dependency.
Regarding to Claim 18, Claim 18 is rejected under the same reason set forth in the rejection of Claim 1 above.
Claims 19-20 are rejected for failing to cure the deficiency from their respective parent claim by dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4, 7, 9-11, 13, 16, 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Pan (US 20140359226 A1).
Regarding to claim 1, Kotte discloses: A system (see [0005]), comprising:
a plurality of memory devices storing a plurality of datasets, each memory device of the plurality of memory devices comprising a physical medium for storing the plurality of datasets (see Fig.1, [0042] and [0045]; “storage medium 130 includes a plurality of flash memory devices” and “Storage medium 130 is divided into a number of addressable and individually selectable blocks, such as selectable portion 131 …. where each page or word line is typically an instance of the smallest individually accessible (readable) portion in a block. In some implementations (e.g., using some types of flash memory), the smallest individually accessible unit of a data set”); and
a device in communication with the plurality of memory devices and a host (see Fig. 1 and [0047]; “storage controller 124 includes a management module 121, a host interface 129, a storage medium interface (I/O) 128 … Host interface 129 provides an interface to computer system 110 through data connections 101. Similarly, storage medium I/O 128 provides an interface to storage medium 130 though connections 103”. Also see [0043]; “Computer system 110 is sometimes called a host or host system”), the device comprising:
one or more circuits comprising a processor and memory, and the one or more circuits (see Figs. 1, 2A, [0048]-[0049] and [0058]-[0068]; “Management module 121 typically includes one or more processing units (CPUs) 122 for executing modules, programs and/or instructions stored in memory 206 and thereby performing processing operations”) configured to:
receive, from the host, a plurality of messages pertaining to the plurality of datasets (see [0059]; “I/O receiving module 210 that is used for receiving from a host a plurality of input/output (I/O) requests (e.g., read requests and/or write requests)”. Also see [0044] and [0050]-[0051] for the I/O requests mentioned at [0059] are I/O requests/messages pertaining to the datasets of storage medium 130);
determine, using the processor, responsive to receipt of the plurality of messages, an amount of information include in each dataset of the plurality of datasets (see [0078] and [0088]; “tracking a total number of write requests to write data of size less than a predefined small-size threshold” and “tracking a total number of write requests to write data of size greater than a predefined large-size threshold”. In order to perform such two tracking, it is required to determine corresponding amount/size of data or information to be written, i.e., amount/size of data included in each of the datasets, then comparing such amount/size of data or information to the corresponding threshold value. Note: claimed “an amount of information included in each dataset” is broad and such claimed amount is not necessary to be interpreted as total amount or size of information inside each dataset. Also see [0089]; “if a storage device with an advertised capacity of 1 terabyte (TB) is divided into m regions, each region will be (1 TB)/m in size”);
identify, using the processor, based on characteristics of the plurality of messages, actions for each message of the plurality of messages, the actions including at least one of updates to the plurality of datasets or accesses of the plurality of datasets (see [0100]; “to receive from the host a plurality of I/O requests, as described above with respect to FIG. 2A. The I/O requests specify operations (sometimes called storage operations or memory operations) to be performed with respect to logical addresses in a plurality of regions in a logical address space of a host”. Also see [0061]-[0064]. There are at least four types of different operations/actions of reading, writing, erasing, garbage collection to be specified and then determined for performing);
update, using the processor, based on the amount of information and the actions, a table located in the memory to reflect receipt of the plurality of messages (see [0066]; “history table 224 that includes a collection of data structures (e.g., region data structures 244, FIG. 2B), each data structure storing data for a respective region of a plurality of regions in a logical address space of a host”);
determine, using the processor, responsive to updating the table, a pattern associated with the plurality of messages, the pattern indicating at least one of: a first number of messages pertaining to the updates to the plurality of datasets; a second number of messages pertaining to the accesses of the plurality of datasets; a third number of messages corresponding to a given amount of information; or a fourth number of messages included in the plurality of messages (see [0065], [0071]; “maintaining a history of I/O request patterns (e.g., one or more histories of I/O request patterns)” and “stores the history of I/O request patterns and/or determinations based on the history of I/O request patterns in history table 224”. Also see [0018]-[0033] for different determined patterns. Among these descriptions, at least one of “tracking whether a total number of write requests to the region has exceeded a write threshold” from [0018], “tracking a total number of sequential write requests to the region” from [0020], “tracking a total number of unaligned write requests to the region” from [0021] can be considered as claimed first number of messages pertaining to updates of the plurality of datasets (note: a writing operation can be considered as a updating operation), at least one of “tracking a total number of sequential read requests from the region” from [0019] and “tracking a total number of write requests to write data of size greater than a predefined large-size threshold” from [0023] can be considered as claimed second number of message pertaining to accesses of the plurality of datasets, at least “tracking a total number of write requests to write data of size less than a predefined small-size threshold” from [0022] can be considered as claimed third number of messages corresponding to a given amount of information).
Kotte does not disclose:
identify, based at least one the pattern, at least one portion of the plurality of memory devices to (i) deallocate from one or more first actions of the actions and (ii) allocate to one or more second actions of the actions to provide additional portions of the plurality of memory devices to the one or second actions beyond what was originally allocated to the one or more second actions.
However, Pan discloses: identify, based at least one the pattern, at least one portion of the plurality of memory devices to (i) deallocate from one or more first actions of the actions and (ii) allocate to one or more second actions of the actions to provide additional portions of the plurality of memory devices to the one or second actions beyond what was originally allocated to the one or more second actions (see [0039]; “the first write cache utilization 114-1 of the write cache of the first storage volume is overutilized (100% utilization) and second write cache utilization 114-2 of the write cache of the second storage volume is underutilized (50% utilization) … some write cache resources may be reallocated from the underutilized second storage volume to the overutilized first storage volume”. Also see [0019]; “write cache resources may be dynamically adjusted such that write cache from storage volumes with low utilization or workload associated with write requests may be reallocated to storage volumes with high utilization or workload”. Note: it is understood that the reallocation discussed at [0039] would require deallocating the corresponding resources and then reallocating such corresponding resources; in addition, since the it is overutilized, the re-allocated resources are works as additional resource beyond what was originally allocated).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify tracking patterns of I/O operations from Kotte by including tracking patterns of I/O operations indicating underutilized and overutilized I/O workload for balancing purpose from Pan, and thus the combination of Kotte and Pan would disclose the missing limitations from Kotte, since it would provide a mechanism of helping “improve the performance of storage systems with techniques to adjust the allocation of cache resources” (see [0011] from Pan).
Regarding to Claim 2, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: wherein the pattern indicates the first number of messages pertaining to the updates to the plurality of datasets (see [0018] and [0063] from Kotte; “hot region flag 264 that is used for tracking whether a total number of write requests to the region has exceeded a write threshold”) and the pattern indicates the second number of messages pertaining to the accesses of the plurality of datasets (see [0019] and [0076] from Kotte; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region”).
Regarding to Claim 4, the rejection of Claim 2 is incorporated and further the combination of Kotte and Pan discloses: wherein the one or more circuits are further configured to: update, using the processor, responsive to a diversion of at least one message of a second plurality of messages, a second table located in the memory to reflect the diversion (see [0076]- [0077] from Kotte; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region; sequential write count 252 that is used for tracking a total number of sequential write requests to the region”. Note: none of the claimed language here excludes the interpretation of claimed “a second plurality of messages” here being a subset of claimed “a plurality of messages” from claim 1. Also see Fig. 2B and [0071]-[0072] from Kotte; the region data structure 244-i containing sequential read count 250 and sequential write count 252 as claimed a second table. None: none of the claimed language here excludes the interpretation of claimed a second table being a portion of claimed “a table” from claim 1);
determine, using the processor, based on the second table, that a number of diversions exceeds a threshold (see [0082] from Kotte; “sequential region flag 262 that is used for tracking whether a total number of sequential I/O requests to the region has exceeded a sequential request threshold”. In order to set this sequential region flag, the related system is required to make a determination to determine whether total number of sequential I/O requests to the region has exceeded a sequential request threshold or not.); and
execute, using the processor, responsive to determination that the number of diversions exceeds the threshold, one or more third actions to address the number of diversions (see [0082] from Kotte; “sequential region flag 262 that is used for tracking whether a total number of sequential I/O requests to the region has exceeded a sequential request threshold”. Executing actions of setting this sequential region flag 262 in response to determining the number of sequential requests to the region, i.e., claimed number of diversions, exceeds threshold).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: a first message of the plurality of messages pertains to a first dataset of the plurality of datasets having a first amount of information; the first message of the plurality of messages is associated with an update to the first dataset (see [0022] from Kotte; “maintaining the history of I/O request patterns in the region includes tracking a total number of write requests to write data of size less than a predefined small-size threshold”. Among the I/O requests received, there is one write/update request is related to a write/update operation to a dataset having data size less than the predefined small-size threshold); and
the one or more circuits are configured to reflect receipt of the first message of the plurality of messages by:
updating, using the processor, the first number of messages from a first value to a second value, wherein the second value accounts for receipt of the first message; and updating, using the processor, the third number of messages from a third value to a fourth value, wherein the fourth value accounts for receipt of the first message (see [0022] and [0078] from Kotte; “maintaining the history of I/O request patterns in the region includes tracking a total number of write requests to write data of size less than a predefined small-size threshold” and “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold”. Among the I/O requests received, there is one write/update request is related to a write/update operation to a dataset having data size less than the predefined small-size threshold. In response to receive and handle such write/update request, the small write count 254 is incremented. Note: none of the claimed limitations of claim 7 now requires claimed first value is different from claimed third value and claimed second value is different from claimed fourth value).
Note: Also see [0078]-[0079] from Kotte; “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold; unaligned write count 256 that is used for tracking a total number of unaligned write requests to the region, wherein unaligned write requests are write requests not aligned with predefined page boundaries”. It is possible that one single write operation would cause both of small write count 254 and unaligned write count 256 are incremented, i.e., such single write operation is a writing operation that a dataset to be written has small size and such dataset is aligned with predefined page boundaries. In this way, the increment of small write count 254 can be considered as updating claimed third value to claimed fourth value and the increment of unaligned write count 256 can considered as updating claimed first value to claimed second value while such four values are not necessarily same.
Regarding to Claim 9, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: wherein the table includes a plurality of portions (see Fig. 2B and [0071]-[0087] from Kotte; “History table 224 includes a collection of region data structures 244, that each store data associated with a respective region of a plurality of regions in a logical address space of a host” and “region data structure 244-i stores the following data (sometimes called history of I/O requests for a particular time period, for a particular region of the logical address space), or a subset or superset”. Note: claimed a plurality of portions now is a very broad concept, the different region data structures can be considered as such claimed a plurality of portions while each different count/information of one single region data structure 244-i can also be considered as such claimed a plurality of portions) and wherein the one or more circuits are configured to update, using the processor, based on the amount of information and the actions, the table located in the memory to reflect receipt of the plurality of messages by:
updating, using the processor, responsive to detection of a first message of the plurality of messages indicating a first update to a first dataset of the plurality of datasets, a first portion of the plurality of portions to include an indication of receipt of the first message (see [0077] from Kotte; “sequential write count 252 that is used for tracking a total number of sequential write requests to the region”. There is a reasonable embodiment of detecting a I/O request is actually a first write/update operation among a number of sequential write requests);
updating, using the processor, responsive to detection of a second message of the plurality of messages indicating a first access of a second dataset of the plurality of datasets, a second portion of the plurality of portions to include an indication of receipt of the second message (see [0076] from Kotte; “sequential read count 250 that is used for tracking a total number of sequential read requests from the region”. There is a reasonable embodiment of detecting a I/O request is actually a first read operation among a number of sequential read requests);
updating, using the processor, based on an amount of information associated with at least one of the first message or the second message, a third portion of the plurality of portions to reflect an indication of at least one of the first message or the second message corresponding to the amount of information (see [0078] from Kotte; “small write count 254 that is used for tracking a total number of write requests to write data of size less than a predefined small-size threshold”. There is a reasonable embodiment of the detected first write/update operation among a number of sequential write request is actually a write/update operation that writing a dataset has size of less than predefined small-size threshold); and
updating, using the processor, a fourth portion of the plurality of portions to indicate an indication of the first message and an indication of the second message (see [0074] from Kotte; “lowest LBA accessed 246 that is used for tracking a lowest logical block address (LBA) accessed in the region”. There is a reasonable embodiment of both of detected first write/update operation among a number of sequential write/update operations and detected first read operation among a number of sequential read operations are access with a lowest logical block address (LBA) accessed in the region. Note: none of the current claimed limitations would require claimed first dataset and claimed second dataset must be two different datasets. Even if Applicant intends to interprets such claimed first and second datasets are two different datasets, the claimed updating fourth portion to indicate an indication of the first message and an indication of the second message can be updating the same region data structure region 244-i of Fig. 2B from Kotte).
Regarding to Claim 10, Claim 10 is rejected for the same reason set forth in the rejection of Claim 1 above.
Regarding to Claim 11, Claim 12 is rejected for the same reason set forth in the rejection of Claim 2 above.
Regarding to Claim 13, Claim 13 is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 16, Claim 16 is rejected for the same reason set forth in the rejection of Claim 7 above.
Regarding to Claim 18, Claim 18 is a method claim corresponds to system Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above.
Regarding to Claim 21, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: the one or more first actions corresponding to one of the first number of messages or the second number of messages; the one or more second actions corresponding to a different one of the first number of messages or the second messages (see [0018]-[0033] from Kotte. Among [0018]-[0033], there are multiple different types of actions, such as “sequential read requests”, “sequential write requests”, “unaligned write requests”, “ write requests to write data of size less than a predefined small-size threshold”, “write requests to write data of size greater than a predefined large-size threshold”, at least the pair of “sequential write requests” and “sequential read requests”, the pair of “sequential write requests” and “write requests to write data of size greater than a predefined large-size threshold”, the pair of “unaligned write requests to the region” and “write requests to write data of size less than a predefined small-size threshold” can be considered as the pair of claimed “first actions” and “second actions”); and the one or more circuits configured to: detect, based at least one the pattern, that a first number of occurrences of the one or more second actions exceeds a second number of occurrences of the one or more first actions; and identify the at least one portion responsive to detection that the first number of occurrences of the one or more second actions exceeds the second number of occurrences of the one or more first actions (see [0039] from Pan; “the first write cache utilization 114-1 of the write cache of the first storage volume is overutilized (100% utilization) and second write cache utilization 114-2 of the write cache of the second storage volume is underutilized (50% utilization) … some write cache resources may be reallocated from the underutilized second storage volume to the overutilized first storage volume”. Also see [0019] from Pan; “write cache resources may be dynamically adjusted such that write cache from storage volumes with low utilization or workload associated with write requests may be reallocated to storage volumes with high utilization or workload”. Note: it is understood that the I/O requests associated high utilization in generally would contain greater number of occurrences of I/O requests associated with low utilization).
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Pan (US 20140359226 A1) and further in view of Minopoli et al. (US 20210406203 A1, hereafter Minopoli).
Regarding to Claim 3, the rejection of Claim 2 is incorporated and further the combination of Kotte and Pan discloses: wherein the one or more circuits are further configured to:
receive, from the host, a second plurality of messages pertaining to the plurality of datasets; identify, using the processor, based on characteristics of the second plurality of messages, actions for respective messages of the second plurality of messages (see [0124] from Kotte; “subsequent to maintaining the history of I/O request patterns in the region for the predetermined time period, maintains (618) a second history of I/O request patterns in the region for a next instance of the predetermined time period (i.e., a period of time immediately following the predetermined period of time, and having the same duration as the predetermined period of time) … The embodiments described herein for maintaining the history of I/O request patterns in the region for the predetermined time period are equally applicable to maintaining a second history of I/O request patterns in the region for a next instance of the predetermined time period”. There are second plurality of I/O requests/messages are received, and such second plurality of I/O requests/messages are handled as same as the first plurality of I/O requests/messages received before this second plurality of I/O requests/messages as explained at the rejection of claim 1 above).
The combination of Kotte and Pan does not disclose: detect, using the processor, based on the pattern, a difference between the plurality of messages and the second plurality of messages; and
identify, using the processor, responsive to detection of the difference, a second plurality of memory devices to divert at least one message of the second plurality of messages.
However, Minopoli discloses: detect, using the processor, based on the pattern, a difference between the plurality of requests and the second plurality of requests; and identify, using the processor, responsive to detection of the difference, a second plurality of memory devices to divert at least one requests of the second plurality of requests (see [0050]-[0051] and [0087]-[0088]; “certain file systems may exhibit particular command traffic patterns, which may be handled most efficiently by particular types of memory” and “selectively divert command traffic associated with determinable write patterns to a portion of the hybrid memory system 204 that is best suited to handling a particular type of file system writes. For example, the controller 206 may be configured to divert LFS writes to memory resource 208-N, which may be a NAND memory, and/or the controller 206 may be configured to divert SSR writes to memory resource 208-1, which may be a low latency emerging memory resource”. Diverting different requests to proper memory devices based on different patterns associated with the different request).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the handling of I/O operations from the combination of Kotte and Pan by including handing different I/O operations based on different patterns associated with the different I/O operations from Minopoli, and thus the combination of Kotte, Pan and Minopoli would disclose the missing limitations from the combination of Kotte and Pan, since it would provide a method of selectively diverting file system writes to portions of memory system that are best suited to handling the command traffic diverted (see [0087] from Minopoli).
Regarding to Claim 12, Claim 12 is rejected for the same reason set forth in the rejection of Claim 3 above.
Claims 5-6, 14-15 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Pan (US 20140359226 A1) and further in view of Baderdinni et al. (US 20130124780 A1, hereafter Baderdinni).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: wherein the one or more circuits are further configured to:
monitor, using the processor, responsive to receipt of a second plurality of messages, the pattern based on characteristics of the second plurality of messages; detect, using the processor, a number of instances pertaining to utilization of the at least one portion of the plurality of memory devices by the one or more second actions (see [0093] from Kotte; “if a region (e.g., region 310-1, FIG. 3) is not marked with a hot region indicator, in some embodiments, subsequent write requests to that region are written to an active block (sometimes referred to as an active “cold block,” as opposed to an active hot block)”. Also see [0124]; “subsequent to maintaining the history of I/O request patterns in the region for the predetermined time period, maintains (618) a second history of I/O request patterns in the region for a next instance of the predetermined time period (i.e., a period of time immediately following the predetermined period of time, and having the same duration as the predetermined period of time) … The embodiments described herein for maintaining the history of I/O request patterns in the region for the predetermined time period are equally applicable to maintaining a second history of I/O request patterns in the region for a next instance of the predetermined time period”).
The combination of Kotte and Pan does not disclose: identify, using the processor, responsive to detection of the number of instances, a change to the pattern.
However, Baderdinni discloses: identify, using the processor, responsive to detection of the number of instances, a change to the pattern (see [0022]; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold”. The description of “as different data is access over time” from [0022] implies there are a number of new instances of I/O requests are detected to use old data to cause the old data becomes hold data now).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the classifications of hot and cold data based on the region access threshold from the combination of Kotte and Pan by including data accessing pattern change of the previous cold data become hot data from Baderdinni, and thus the combination of Kotte, Pan and Baderdinni would disclose the missing limitations from the combination of Kotte and Pan, since it would provide a flexible system to allow adjustment on data access pattern (see [0022] from Baderdinni).
Regarding to Claim 6, the rejection of Claim 5 is incorporated and further the combination of Kotte, Pan and Baderdinni discloses: deallocate, using the processor, responsive to identification of the change to the pattern, the at least one portion of the plurality of memory devices from the one or more second actions (see [0022] from Baderdinni and [0093]-[0094] from Kotte; “As different data is accessed over time, data access patterns may change, causing previously cold data to become hot and previously hot data to become cold” and “data associated with hot regions are grouped together (e.g., on hot blocks) and data associated with cold regions are grouped together (e.g., on cold blocks)”. Due to the previous cold data/region become current hot data/region, then at the new combination system, such previous cold data/region is deallocated from the groups of cold regions and allocated to the group of hot regions); and
process, using the processor, using the at least one portion of the plurality of memory devices, at least one message of the second plurality of messages during one or more third actions different than the one or more second actions (see [0093]-[0094] from Kotte; “subsequent write requests to that region are written to an active hot block”. Note: although the subsequent write requests are still write type of requests, such write requests are subsequent to the previous write requests, and thus such subsequent write requests are different than the previous write requests).
Regarding to Claim 14, Claim 14 is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 15, Claim 15 is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 19, Claim 19 is a method claim corresponds to system Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 20, Claim 20 is a method claim corresponds to system Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kotte et al. (US 20150347028 A1-IDS recorded, hereafter Kotte) in view of Pan (US 20140359226 A1) and further in view of Pellicone et al. (US 7571362 B2, hereafter Pellicone).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further the combination of Kotte and Pan discloses: wherein the one or more circuits are further configured to:
execute, using the processor, one or more third actions to process one or more messages of the plurality of messages (see [0071] from Kotte; “the storage device gathers data as I/O requests are processed”. At least one of the I/O requests as claimed one or more third actions are processed/executed. Also see [0018]-[0033] from Kotte; there are multiple different types of I/O requests or actions, and thus it is reasonable to conclude there is at least a third type of action from the I/O requests in addition to first type of actions and second type of actions. Note: it is understood that “sequential write requests”, “unaligned write requests”, “write requests to write data of size less than a predefined small-size threshold” and “write requests to write data of size greater than a predefined large-size threshold” can be different types of writing I/O requests or actions).
The combination of Kotte and Pan does not disclose: detect, using the processor, responsive to execution of the one or more third actions, at least one message of the one or more messages associated with a memory device of the plurality of memory devices that includes a bad block; and
update, using the processor, responsive to detection of the at least one message, a second table located in the memory corresponding to one or more memory devices of the plurality of memory devices with bad blocks from a first size to a second size to account for the memory device including the bad block.
However, Pellicone discloses: detect, using the processor, responsive to execution of the one or more third actions, at least one message of the one or more messages associated with a memory device of the plurality of memory devices that includes a bad block (see claim 1; “determining, during operation of the non-volatile memory device, a failure of a block of cells previously not marked as bad”); and
update, using the processor, responsive to detection of the at least one message, a second table located in the memory corresponding to one or more memory devices of the plurality of memory devices with bad blocks from a first size to a second size to account for the memory device including the bad block (see claim 1; “updating the bad block address table in the embedded random access memory based at least in part on said determining of the failure of the block”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the history table 224 from the combination of Kotte and Pan by including a bad block address table from Pellicone, and thus the combination of Kotte, Pan and Pellicone would disclose the missing limitations from the combination of Kotte and Pan, since it would provide additional table or data structure to show information of bad blocks to avoid accessing to these bad blocks (see claim 1 from Pellicone; “looking up the bad block address table copied in the embedded random access memory to determine whether a block of the first subset addressed by the user is bad and, if so, remapping access to a corresponding block of redundancy data storage cells”).
Regarding to Claim 17, Claim 17 is rejected for the same reason set forth in the rejection of Claim 8 above.
Response to Arguments
Applicant’s arguments, filed 3/25/2026, with respect to prior art rejections of claims 1-20 have been full considered. New grounds of rejection are made based on new amended limitations from the independent claims. In additional, some of Applicant’s arguments not persuasive. Such as, Applicant stated that “tracking write requests to a region does not discloses a pattern between ‘a first number of messages pertaining to the updates to the plurality of datasets and “a second number of messages pertaining to the accesses of the plurality of datasets”” (see 1st paragraph of page 13 from the Remarks). In response to such argument,
1. Applicant is suggested to review claim 1 again to distinguish difference “a pattern between” A and B (i.e., feature that Applicant argued. It is understood that a pattern between A and B in generally means a relationship pattern between A and B) and “the pattern indicating at least one of” A or B (i.e., feature that claim 1 requires. It is understood that a pattern indicating at least one of A or B in generally means a pattern indicating pattern of A or pattern of B).
2. write requests to one with ordinary skill in the art are understood as requests to write data or value to certain dataset (and thus there is update to the dataset). In this way, “tracking whether a total number of write requests to the region has exceeded a write threshold” is reasonable to be considered as a pattern indicates claimed “a first number of messages pertaining to the updates to the plurality of datasets”.
3. Applicant is suggested to review the Office Action since Examiner only used the feature of tracking write requests from Kotte to map to claimed “a first number of messages pertaining to the updates to the plurality of datasets” without using such feature to disclose claimed “a second number of messages pertaining to the accesses of the plurality of datasets” (see 1st paragraph of page 6 from the non-Final Office Action), and thus it is not clear the reason Applicant still argued the second number of message limitation with tracking write requests from Kotte.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kakadia et al. (US 20150222560 A1) discloses: if a queue is being underutilized, resources (e.g., memory space, data packet processing resources, etc.) may be redistributed to another queue that is being overutilized (see [0094]).
Osborne (US 20030093631 A1) discloses: wherein the memory port has a memory port protocol allowing a processor write request to be preempted by a processor read request (see claim 8)
Mott et al. (US 20080120450 A1) discloses: generates a high-priority preempt signal when the RX DATA signal indicates that the associated command is a read command and a low-priority preempt signal when the RX DATA signal indicates that the associated command is a write command (see [0045]).
Karr et al. (US 20230393742 A1) discloses: The pre-emptive transmission of the indication may cause the storage device 356 b to suspend an ongoing write operation (or prevent storage device 356 b from starting a new write operation) in anticipation of receiving and performing the one or more read operations (see [0328]).
Ramalingam et al. (US 9851905 B1) discloses: employs concurrent memory operations for read operation preemption and includes transaction control logic configured to resume a suspended write operation concurrently with at least a portion of the transfer of read data from a non-volatile memory for a read operation which preempted the write operation (see abstract).
Lee et al. (US 20090234987 A1) discloses: if a high volume of read requests are received, resources allocated for use by a write transaction table can be reassigned to the read transaction table and vice versa (see [0067]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
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