Prosecution Insights
Last updated: April 19, 2026
Application No. 18/239,332

SIGNAL PROCESSOR AND SIGNAL PROCESSING METHOD

Non-Final OA §102
Filed
Aug 29, 2023
Examiner
ZEE, EDWARD
Art Unit
2435
Tech Center
2400 — Computer Networks
Assignee
TDK Corporation
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
812 granted / 895 resolved
+32.7% vs TC avg
Moderate +10% lift
Without
With
+10.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
14 currently pending
Career history
909
Total Applications
across all art units

Statute-Specific Performance

§101
10.4%
-29.6% vs TC avg
§103
25.5%
-14.5% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 895 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This is in response to the correspondence filed on 11/29/23. Claims 1-16 are still pending and have been considered below. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6-8 and 12-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lathrop et al. (2021/0406648). Claim 1: Lathrop et al. discloses a signal processor comprising: an input unit configured to receive a first analog signal [page 3, paragraph 0039] ; an analog-digital converter configured to convert the first analog signal to a first digital signal [page 3, paragraph 0039] ; a control circuit configured to detect the first analog signal or the first digital signal and to output a control signal for extracting a part of the first analog signal or the first digital signal ( control signals that configure interconnections) [page 3, paragraphs 0044-0045] ; and a reservoir unit configured to receive at least a part of the first digital signal and to operate in synchronization with at least a part of the control signal ( components can be clocked and synchronous) [page 2, paragraph 0032 | page 3, paragraph 0040] . Claim 6: Lathrop et al. discloses t he signal processor according to claim 1, wherein the number of signals input to the reservoir unit in a predetermined period in accordance with the control signal from the control circuit is equal to or less than short-term memory property of the reservoir unit [pages 11-12, paragraphs 0107-0109] . Claim 7: Lathrop et al. discloses t he signal processor according to claim 1, wherein the input unit additionally receives a second analog signal [page 5, paragraphs 0059 & 0062] . Claim 8: Lathrop et al. discloses t he signal processor according to claim 1, wherein the reservoir unit performs reservoir computing one time in synchronization with every output of the control signal [page 2, paragraph 0032 | page 3, paragraph 0040] . Claim 12: Lathrop et al. discloses t he signal processor according to claim 1, wherein the control circuit outputs the control signal when a change per unit time of the first analog signal or the first digital signal is equal to or greater than a set value [page 10, paragraphs 0098-0099] . Claim 13: Lathrop et al. discloses the signal processor according to claim 1, wherein the reservoir unit operates in synchronization with at least a part of the control signal and performs learning based on an input signal [page 15, paragraphs 0130-0131] , and wherein an output condition of the control signal at the time of learning is the same as an output condition of the control signal at the time of inference [page 15, paragraph 0131-0132] . Claim 14: Lathrop et al. discloses the signal processor according to claim 1, wherein the reservoir unit is realized as a state machine by logical circuits [page 15, paragraph 0131-0132] , and wherein an operation signal of the state machine is synchronized with at least a part of the control signal and the reservoir unit performs reservoir computing one time based on the operation signal [page 2, paragraph 0032 | page 3, paragraph 0040] . Claim 15: Lathrop et al. discloses t he signal processor according to claim 1, wherein the reservoir unit is realized as a physical reservoir including elements or circuits [page 15, paragraphs 0131-0132] , and wherein an input signal is input to the physical reservoir in synchronization with at least a part of the control signal and the reservoir unit performs reservoir computing one time based on the input signal [page 2, paragraph 0032 | page 3, paragraph 0040] . Claim 16: Lathrop et al. discloses a signal processing method comprising: detecting a first analog signal or a first digital signal to which the first analog signal is converted [page 3, paragraph 0039] ; outputting a control signal for extracting a part of the first analog signal or the first digital signal when the first analog signal or the first digital signal satisfies a setting condition [page 9, paragraph 0092] ; and performing inference through reservoir computing with a signal extracted using the control signal as an input [page 15, paragraph 0131-0132] . Allowable Subject Matter Claims 2-5 and 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT EDWARD ZEE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1686 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 9AM-5PM EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Amir Mehrmanesh can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-3351 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EDWARD ZEE/ Primary Examiner, Art Unit 2435
Read full office action

Prosecution Timeline

Aug 29, 2023
Application Filed
Mar 12, 2026
Non-Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+10.1%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 895 resolved cases by this examiner. Grant probability derived from career allow rate.

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