DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-16, in the reply filed on 17 December 2025 is acknowledged.
Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 17 December 2025.
Information Disclosure Statement
Information disclosure statement filed 29 August 2023 has been fully considered.
Claim Objections
Claim 10 is objected to because of the following informalities:
Claim 10 recites the limitation, “further comprising a gate spacer located on first side of the gate structure.” This appears to contain a typographical error and may be corrected as, “further comprising a gate spacer located on the first side of the gate structure.”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang et al. (US Patent Application Publication 2021/0134721, hereinafter Chiang ‘721) of record in view of Yu et al. (US Patent Application Publication 2021/0384316, hereinafter Yu ‘316).
With respect to claim 1, Chiang ‘721 teaches (FIG. 29) a semiconductor structure substantially as claimed, comprising:
a transistor comprising a gate structure (96 and 98), a first source/drain region (90) present on a first side of the gate structure and a second source/drain region (90) present on a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure ([0044, 0057]);
a dielectric cap (91 and 92) located on a first surface of the second source/drain region (90) ([0053]); and
a backside source/drain contact structure (120 and 122) located on a second surface of the second source/drain region (90), wherein the second surface of the second source/drain region is opposite the first surface of the second source/drain region ([0066, 0071]).
Thus, Chiang ‘721 is shown to teach all the features of the claim with the exception of an off-centered frontside gate contact structure having a first portion located directly above, and in direct physical contact with, the gate structure of the transistor, and a second portion off-set relative to the gate structure and located directly on the dielectric cap.
However, Yu ‘316 teaches (FIG. 15C) a gate-all-around (GAA) transistor comprising an off-centered frontside gate contact structure (290-3) having a first portion located directly above, and in direct physical contact with, a gate structure (220) of the transistor, and a second portion off-set relative to the gate structure and located directly on a dielectric cap (270) ([0033]) in a method that prevents or reduces damage to gate spacers, increased parasitic capacitance, unwanted electrical shorts, or leakage due to loss of gate spacers ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor structure of Chiang ‘721 further comprising an off-centered frontside gate contact structure having a first portion located directly above, and in direct physical contact with, the gate structure of the transistor, and a second portion off-set relative to the gate structure and located directly on the dielectric cap as taught by Yu ‘316 in a method that prevents or reduces damage to gate spacers, increased parasitic capacitance, unwanted electrical shorts, or leakage due to loss of gate spacers.
With respect to claims 2-4, Chiang ‘721 and Yu ‘316 teach the device as described in claim 1 above, but primary reference Chiang ‘721 does not explicitly teach the additional limitations further comprising a gate cap pillar located adjacent to the off-centered frontside gate contact structure and on the gate structure; wherein the gate cap pillar is located on a first side of the first portion of the off-centered frontside gate contact structure and the dielectric cap is located on a second side of the first portion of the off-centered frontside gate contact structure; and wherein the gate cap pillar is composed of a dielectric material that is compositionally different from a dielectric material that provides the dielectric cap.
However, Yu ‘316 teaches (FIG. 15C) a gate cap pillar (portion of 250) located adjacent to the off-centered frontside gate contact structure (290-3) and on the gate structure (220); wherein the gate cap pillar is located on a first side of the first portion of the off-centered frontside gate contact structure and the dielectric cap (270) is located on a second side of the first portion of the off-centered frontside gate contact structure; and wherein the gate cap pillar is composed of a dielectric material that is compositionally different from a dielectric material that provides the dielectric cap ([0022, 0027]) in a method that prevents or reduces damage to gate spacers, increased parasitic capacitance, unwanted electrical shorts, or leakage due to loss of gate spacers ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor structure of Chiang ‘721 and Yu ‘316 further comprising a gate cap pillar located adjacent to the off-centered frontside gate contact structure and on the gate structure; wherein the gate cap pillar is located on a first side of the first portion of the off-centered frontside gate contact structure and the dielectric cap is located on a second side of the first portion of the off-centered frontside gate contact structure; and wherein the gate cap pillar is composed of a dielectric material that is compositionally different from a dielectric material that provides the dielectric cap as taught by Yu ‘316 in a method that prevents or reduces damage to gate spacers, increased parasitic capacitance, unwanted electrical shorts, or leakage due to loss of gate spacers.
With respect to claim 9, Chiang ‘721 teaches further comprising a backside interconnect structure (124) in direct contact with the backside source/drain contact structure (120 and 122) ([0048]).
With respect to claim 15, Chiang ‘721 teaches wherein the transistor is a nanosheet transistor, and the nanosheet transistors comprises a nanosheet stack comprising a plurality of vertically stacked and spaced apart semiconductor channel material nanosheets (54), wherein the gate structure (96 and 98) wraps around a portion of each of the semiconductor channel material nanosheets of the plurality of vertically stacked and spaced apart semiconductor channel material nanosheets ([0018]).
With respect to claim 16, Chiang ‘721 teaches wherein the second source/drain region (90) is a replacement source/drain region ([0044]).
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chiang ‘721 and Yu ‘316 as applied to claim 1 above, and further in view of Engel et al. (US Patent Application Publication 2023/0369222, hereinafter Engel ‘222).
With respect to claim 5, Chiang ‘721 and Yu ‘316 teach the device as described in claim 1 above with the exception of the additional limitation further comprising a frontside source/drain contact structure directly contacting the first source/drain region.
However, Engel ‘222 teaches (FIG. 4) a gate-all-around (GAA) transistor comprising backside (408) and frontside (216) source/drain contact structures directly containing the source/drain regions (214) to provide multiple access points to provide current to said source/drain regions ([0033-0034, 0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor structure of Chiang ‘721 and Yu ‘316 further comprising a frontside source/drain contact structure directly contacting the first source/drain region as taught by Engel ‘222 to provide multiple access points to provide current to said source/drain regions.
With respect to claims 6-8, Chiang ‘721, Yu ‘316, and Engel ‘222 teach the device as described in claim 5 above, but primary reference Chiang ‘721 does not explicitly teach the additional limitations further comprising a middle-of-the-line (MOL) dielectric layer partially embedding both the frontside source/drain contact structure and the off-centered frontside gate contact structure; further comprising a frontside back-end-of-the-line (BEOL) structure located on the MOL dielectric layer, wherein the frontside BEOL structure comprises initial interconnect levels including metal vias and metal lines; and wherein a first metal via/metal line combination is electrically connected to the frontside source/drain contact structure and a second first metal via/metal line combination is electrically connected to the off-centered frontside gate contact structure.
However, Chiang ‘721 teaches a middle-of-the-line (MOL) dielectric layer (100) ([0062]). When combined with Yu ‘316 and Engel ‘222, said middle-of-the-line (MOL) dielectric layer would partially embed both the frontside source/drain contact structure and the off-centered frontside gate contact structure. Chiang ‘721 further teaches a frontside back-end-of-the-line (BEOL) structure (138) located on the MOL dielectric layer (100), wherein the frontside BEOL structure comprises initial interconnect levels including metal vias and metal lines ([0064]). When combined with Yu ‘316 and Engel ‘222, a first metal via/metal line combination would be electrically connected to the frontside source/drain contact structure and a second first metal via/metal line combination would electrically connected to the off-centered frontside gate contact structure to provide signals to the gate-all-around (GAA) transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor structure of Chiang ‘721, Yu ‘316, and Engel ‘222 further comprising a middle-of-the-line (MOL) dielectric layer partially embedding both the frontside source/drain contact structure and the off-centered frontside gate contact structure; further comprising a frontside back-end-of-the-line (BEOL) structure located on the MOL dielectric layer, wherein the frontside BEOL structure comprises initial interconnect levels including metal vias and metal lines; and wherein a first metal via/metal line combination is electrically connected to the frontside source/drain contact structure and a second first metal via/metal line combination is electrically connected to the off-centered frontside gate contact structure as taught by Chiang ‘721 to provide signals to the gate-all-around (GAA) transistor.
Allowable Subject Matter
Claims 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the semiconductor structure of claim 10 in the combination of limitations as claimed, noting particularly the limitation, “wherein the recessed gate spacer has a height that is less than the gate spacer.” Chiang ‘721 teaches gate spacers (82); however, said gate spacers are the same height. None of the other prior art references made of record cure this deficiency in combination with the other elements of the claim including at least the off-centered frontside gate contact structure.
Claims 11-14 are indicated as containing allowable subject matter based merely upon their dependency from claim 10 indicated as containing allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Song et al. (US Patent 11,152,347) teaches an off-centered frontside gate contact structure;
Yun et al. (US Patent Application Publication 2024/0063122) teaches a gate-all-around (GAA) transistor having front- and back-side contacts; and
Mignot et al. (US Patent Application Publication 2024/0332182) teaches GAA transistor comprising an asymmetric gate contact over a source/drain contact.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893