DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The Information Disclosure Statements filed on 30 August 2023 and 21 April 2025 have been considered by the examiner.
Claim Interpretation
No claims interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 10, 11, and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mohl et al. (Pub. No. US 2006/0101237).
Claim 1:
Mohl et al. disclose a synchronous data flow (SDF) manager circuit comprising [pars. 0037, 0130 – “Example embodiments of the present invention may increase the computational capability of a system, for example, by implementing a data flow machine in hardware, wherein higher parallelism may be obtained.” … “Thus, not only synchronous data flow machines may be constructed, but also static and dynamic data flow machines.”]:
first circuitry to perform a first access of one or more first registers during a runtime of an application which is modeled with a SDF graph which comprises:
multiple nodes each to represent a respective task of the application, and one or more channels each to communicate via a first node of the multiple nodes [par. 0038 – “An example embodiment of the present invention provides a method for generating descriptions of digital logic from high-level source code specifications, wherein at least part of the source code specification may be compiled into a multiple directed graph representation comprising functional nodes with at least one input or one output, and connections indicating the interconnections between the functional nodes. Moreover, hardware elements may be defined for each functional node of the graph, wherein the hardware elements may represent the functions defined by the functional nodes. Additional hardware elements may be defined for each connection between the functional nodes, wherein the additional hardware elements may represent transfer of data from a first functional node to a second functional node. A firing rule for each of the functional nodes of the graph may be defined. The firing rule may define a condition for the functional node to provide data at its output and to consume data at its input.”],
wherein the one or more first registers each correspond to a different respective channel of the one or more channels, and where the first access is to determine, for each channel of the one or more channels, whether the channel is currently able to accommodate an execution of a first task of the application [pars. 0095 - 0099, 0122, 0129-0130 – “A specification for a general firing rule may comprise: 1) the conditions for each input of the node in order for the node to consume the input data, 2) the conditions for each output of the node in order for the node to produce data at the output, and 3) the conditions for executing the function of the node. The conditions may depend on the values of input data, existence of valid data at inputs or outputs, the result of the function applied to the inputs or the state of the function, but may depend on any data available to the system.” … “Instead, the data flow machine may be implemented directly by replacing nodes with combinatorial logic and arcs with registers or other fast memory elements that may be accessed (e.g., independently) in parallel.” … “Another approach is illustrated in FIG. 4a, where each node 401 is provided with additional signal lines for providing correct data at every time instant. The first additional lines carry "valid" signals 402, which may indicate that previous nodes have stable data at their outputs. Similarly, the node 401 may provide a "valid" signal 403 to a subsequent node in the data path when the data at the output of node 401 is stable. By this procedure, each node may be able to determine the status of the data at its inputs.” … “The use of a "valid" signal may enable representation of the existence or non-existence of data on an arc. Thus, not only synchronous data flow machines may be constructed, but also static and dynamic data flow machines. The "valid" signal may not have to be implemented as a dedicated signal-line, it may be implemented in several other ways, such as, choosing a special data value to represent a "null"-value. As for the stall signal, there are many other possible signaling schemes. For brevity, the rest of this document will only refer to stall and valid signals. It is more simple to extend the function of example embodiments of the present invention to other signaling schemes.”];
wherein the first circuitry is further to perform, based on the first access, a second access of a second register which corresponds to the first node, wherein the second access is to provide a value of a first status parameter of the second register, the value to identify whether the first task is currently qualified to be executed [par. 0093 – “Each node may be provided with a firing rule, which may define a condition for the node to provide data at its output. This may allow this situation to be handled more efficiently.”]; and
second circuitry to perform a third access of the second register based on a request to identify a next task to be executed [pars. 0130-0131 – “Moreover, second additional lines carry a "stall" signal 404, which may indicate to a previous node that the current node 401 is not prepared to receive any additional data at its inputs. Similarly, the node 401 may also receive a "stall" line 405 from a subsequent node in the data path. By the use of stall lines it may be possible to temporarily stop the flow of data in a specific path. This may be increasingly important in cases in which a node at some time instances performs time-consuming data processing with indeterminate delay, such as loops or memory accesses. The use of a stall signal is a one example embodiment of the present invention. However, several other signals may be used, depending on the protocol chosen. Examples include "data consumed", "ready-to-receive", "acknowledge" or "not-acknowledge"-signals, and signals based on pulses or transitions rather than a high or low signal. Other signaling schemes are also possible.” … “With the existence of a specific stall signal, it may be possible to achieve higher efficiency. The stall signal may enable a node to know that even if the arc below is full at the moment, it may be able to accept an output token at the next clock cycle. Without a stall signal, the node may have to wait until there is no valid data on the arc below before it can fire. That is, for example, an arc will be empty at least every other cycle. This may decrease efficiency.”], the second circuitry further to generate a reply to the request based on the first status parameter [pars. 0050, 0099, 0102 – “The at least one first function may be performed based on at least one firing rule. The at least one second hardware element may perform at least one second function associated with a respective connection between nodes in the graph.” … “The conditions may depend on the values of input data, existence of valid data at inputs or outputs, the result of the function applied to the inputs or the state of the function, but may depend on any data available to the system.” … “For example, assume that the node has two inputs, T and F. The condition controlling the node may be received on an input C and the result may be provided at the output R. The firing rule below may produce data at the output of the node, for example, even if there are only data available at one input.”].
Claim 2 (as applied to claim 1 above):
Mohl et al. disclose,
wherein the reply is to indicate a failure to identify any task as currently being qualified to be executed [pars. 0130, 0133 – “By the use of stall lines it may be possible to temporarily stop the flow of data in a specific path. This may be increasingly important in cases in which a node at some time instances performs time-consuming data processing with indeterminate delay, such as loops or memory accesses.” … “This circuitry may ensure that the register will retain its data if the destination node is not prepared to accept the data; and signal this to the source node.”].
Claim 3 (as applied to claim 1 above):
Mohl disclose,
wherein, based a failure to identify any node as currently being qualified to be executed, the second circuitry is to delay a generation of the reply until a node is identified as being qualified to be executed [pars. 0130, 0133 – “By the use of stall lines it may be possible to temporarily stop the flow of data in a specific path. This may be increasingly important in cases in which a node at some time instances performs time-consuming data processing with indeterminate delay, such as loops or memory accesses.” … “This circuitry may ensure that the register will retain its data if the destination node is not prepared to accept the data; and signal this to the source node.”].
Claim 10:
Claim 10 rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 11 (as applied to claim 10 above):
Claim 11 rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis.
Claim 15:
Claim 15 rejected for the same reasons set forth in the rejection of claim 1 above, mutatis mutandis [pars. 0024-0028].
Claim 16 (as applied to claim 15 above):
Claim 16 rejected for the same reasons set forth in the rejection of claim 2 above, mutatis mutandis.
Claim 17 (as applied to claim 15 above):
Claim 17 rejected for the same reasons set forth in the rejection of claim 3 above, mutatis mutandis.
Allowable Subject Matter
Claim 4-9, 12-14, and 18-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
28 September 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139
