Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 6, 2026 has been entered.
Response to Amendment
Amendments to claims 1 and 11 submitted on July 6, 2026, are acknowledged and have since been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 6, 8, 10-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20220238674 A1) in further view of Sugimoto (US 20160064550 A1).
Regarding Claim 1, Zhang teaches a power semiconductor device (1100, shown Fig. 12) comprising:
a semiconductor body (260),
at least one source region (920) in the semiconductor body,
a gate electrode (1224) at the semiconductor body,
a gate insulator (410 and 1226) between the semiconductor body and the gate electrode (shown Fig. 12), and
at least one well region (614) at the at least one source region and at the gate insulator (shown Fig. 12),
wherein the gate insulator has a varying dielectric capacitance (an inherent characteristic due to the different material portions, see also [0032] describing a portion 410 and material selection comprising silicon dioxide and [0034] describing layer 1226 being composed of a different material than that of portion 410), the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator at a specific location thereof (a dielectric capacitance is inherently a quotient of these physical characteristics as defined by the specification), the at least one well region is in direct contact only with the first gate insulator regions and not with the second gate insulator region (shown Fig. 12) and as seen in cross-section, the gate insulator is composed of two first gate insulator regions (1226) and of a central, second gate insulator region (410), wherein the first gate insulator regions are in direct contact with the at least one well region (shown Fig. 12) and the second gate insulator region comprising silicon dioxide is in contact only with the semiconductor body (shown Fig. 12).
Zhang further suggests that a material of the first gate insulator (formed of portion 1122, see also [0034]) may be selected to accommodate a specific capacitance and dielectric constant that is “desired for a given application.” However, Zhang is silent regarding a specific material selection implemented for the first gate insulator and does not explicitly teach the semiconductor body comprising a drift region.
Sugimoto teaches a semiconductor device (200, shown Fig. 2) analogous to that of Zhang comprising a semiconductor body (12), at least one source region (30) in the semiconductor body, a gate electrode (18) at the semiconductor body, a gate insulator (16) between the semiconductor body and the gate electrode, and at least one well region (32) at the at least one source region and at the gate insulator (shown Fig. 2), wherein the gate insulator has a varying dielectric capacitance (see Sugimoto: [0036]) the dielectric capacitance is larger at the at least one well region than in remaining regions of the gate insulator to improve switching behavior while maintaining lower on-state resistance (see Sugimoto: [0041] which describes “a high gate threshold level and a low channel resistance”), and seen in cross-section, the gate insulator is composed of two first gate insulator regions (16c) having the larger dielectric capacitance (see [0036] describing HfO2) and of a central, second gate insulator region having a smaller dielectric capacitance (SiO2), wherein the first gate insulator regions comprise a high-k material (HfO2) having a relative dielectric constant higher than silicon dioxide, and the second gate insulator region comprises silicon dioxide, and wherein the semiconductor body comprises a drift region (34).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement the high-k dielectric material HfO2 as the first gate insulator regions over the well regions of Zhang and a drift region within the semiconductor body of Zhang as this configuration enables a high gate threshold level with low channel resistance (see Sugimoto: [0041]).
As applied to Zhang, this modification would teach the first gate insulator regions comprising a high-k material having a relative dielectric constant higher than silicon dioxide, the second gate insulator region comprising silicon dioxide, the dielectric capacitance being larger at the at least one well region (hafnium oxide having a higher dielectric constant than silicon dioxide, corresponding to first gate insulator regions 1226 of Zhang) than in remaining regions of the gate insulator (corresponding to the second gate insulator region 410 of Zhang) to improve switching behavior while maintaining lower on-state resistance (as described in Sugimoto: [0041]), wherein the semiconductor body comprises a drift region, wherein the first gate insulator regions comprising the high-k material are in direct contact with the at least one well region, and the second gate insulator region comprising silicon dioxide is in contact only with the drift region (as applied to Zhang, see Zhang: Fig. 12).
Regarding Claim 2, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein at least one of:
the semiconductor body is of a wide bandgap material or of silicon carbide (see [0026]), and
the power semiconductor device is a field-effect transistor (see Zhang: [0026]) or an insulated gate bipolar transistor.
Regarding Claim 3, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1 wherein the gate insulator comprises a first material (silicon dioxide) and a second material (hafnium oxide, as modified by Sugimoto), the second material has a higher relative dielectric constant than the first material, and wherein the second material is a continuous layer completely extending between the gate electrode and the semiconductor body (shown Zhang: Fig. 12).
Regarding Claim 6, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 3 wherein the gate insulator is of constant geometric thickness (see Zhang: [0034]) and the first material and the second material are located next to one another in a common plane (shown Fig. 12), and wherein the first material and the second material are in direct contact with the semiconductor body (shown Fig. 12).
Regarding Claim 8, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein the gate electrode is of planar configuration so that the gate electrode is located on a top side of the semiconductor body and the top side is of planar fashion (shown Fig. 12, see also Zhang: [0026] which describes a “planar MOSFET” configuration).
Regarding Claim 10, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein the first gate insulator regions are located at edges of the gate electrode and the second gate insulator region is located at a middle portion of the gate electrode (shown Fig. 12).
Regarding Claim 11, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1 wherein the drift region and the at least one source region are of a first conductivity type (n-type), and the at least one well region is of a second conductivity type different from the first conductivity type (p-type), and wherein, as seen in a cross-section, the first gate insulator regions are in contact with the at least one source region and with the at least one well region as well as with the drift region (shown Zhang: Fig. 12), and wherein the first gate insulator regions comprising the high-k material are in direct contact with the at least one source region and with the at least one well region (shown Zhang: Fig. 12).
Regarding Claim 12, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein a proportion of the second gate insulator region along an interface of the gate electrode facing the semiconductor body is between 20% and 80% inclusive of an overall extent of said interface (shown Fig. 12), wherein, as seen in cross-section, the first gate insulator regions are located along said interface symmetrically around the second gate insulator region (shown Fig. 12).
Regarding Claim 13, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein the dielectric capacitance of the first gate insulator regions is greater than the dielectric capacitance of the second gate insulator region (see Sugimoto: [0036] for relative dielectric constants and [0007] further describing that capacitance is determined by thickness and dielectric constant of the gate insulating film).
Sugimoto further teaches a separate embodiment (shown Fig. 1) wherein a relative thickness of first gate insulator regions (16a, shown Fig. 1) is different than the thickness of a second gate insulator region (16b, shown Fig. 1) such that a theoretical threshold level Vth may further be tuned (see Sugimoto: [0026]).
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Sugimoto shows that dielectric capacitance is a result-effective variable because it reveals that tuning the thickness and dielectric constant of the gate insulating film allows for raising a gate voltage to a potential substantially equal to the theoretical threshold level, thus achieving a high gate threshold level and a low channel resistance (see Sugimoto: [0008]).
A person who has ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal dielectric capacitance of the first gate insulator regions and the second gate insulator region. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.”(see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, through routine optimization, the dielectric capacitance of the first gate insulator regions being at least 1.4 times to 6 times the dielectric capacitance of the second gate insulator region would be obvious to one of ordinary skill in the art.
Regarding Claim 14, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1 wherein an overall geometric thickness of the gate insulator is between 10 nm and 1.5 microns (see [0028] giving an exemplary thickness of 30 nm to 60 nm for portion 410 and [0034] describing portions 1226 having equal thickness).
Regarding Claim 15, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1 further comprising at least two source regions (920) wherein, as seen in cross-section, the gate electrode is located between two of the at least two source regions (shown Fig. 12) and the first gate insulator regions comprising the high-k material are located adjacent to each of the at least two source regions (see Fig. 12).
Zhang further suggests that contacts would be formed in FEOL processes to complete the planar MOSFET (see [0035]) but does not explicitly show a source electrode formed to contact the at least two source regions.
Sugimoto further teaches a source electrode (14) which is in electric contact with the at least two of the source regions, the source electrode covers the gate electrode on a side remote from the semiconductor body so that the source electrode is a common electrode for the at least two source regions (shown Sugimoto: Fig. 2).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a common source contact as taught by Sugimoto to the device of Zhang as this would enable any number of desired transistors to be electrically connected in parallel.
Regarding Claim 16, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein the high- k material of the first gate insulator regions (hafnium oxide, as modified by Sugimoto) is selected from the group consisting of Y203, ZrO2, HfO2, La2O3, Ta2Os, and TiO2.
Regarding Claim 17, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein the high- k material of the first gate insulator regions forms a continuous layer completely extending between the gate electrode and the semiconductor body (see Zhang: Fig. 12).
Regarding Claim 20, Zhang as modified by Sugimoto teaches the power semiconductor device according to claim 1, wherein a ratio between the relative dielectric constant of the high-k material and the relative dielectric constant of silicon dioxide is greater than 5 (see Sugimoto: [0036]).
When there is a design need or market pressure to solve a problem and there are a finite
number of identified, predictable solutions, a person of ordinary skill has good reason to pursue the
known options within their technical grasp. If this leads to the anticipated success, it is likely the product
not of innovation but of ordinary skill and common sense. In that instance the fact that a combination
was obvious to try might show that it was obvious under §103. See also MPEP 2144.05.
More specifically to this case, Sugimoto shows that dielectric constant of a high-k material is a result-effective variable because it reveals that tuning the dielectric constant of regions of the gate insulating film allows for raising a gate voltage to a potential substantially equal to the theoretical threshold level, thus achieving a high gate threshold level and a low channel resistance (see Sugimoto: [0008]).
A person who has ordinary skill in the art using this prior art teaching, therefore, would anticipate and predict the optimal material selection to accommodate a desired dielectric constant of the first gate insulator regions and the second gate insulator region. Furthermore, a modification of this kind may be patentable "if it ‘produce[s] a new and unexpected result which is different in kind and not merely in degree from the results of the prior art.” (see Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). The original disclosure does not describe such a result of unexpected advantageous properties.
As such, through routine optimization, a material selection accommodating a ratio between the relative dielectric constant of the high-k material and the relative dielectric constant of silicon dioxide to be between 1.2 and 5 would be obvious through routine optimization.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/C.P.B./Examiner, Art Unit 2893 /Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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