Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 4-5, 7 and 9 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 16, 2026.
Claim Interpretation
The term “dielectric capacitance” is defined in the instant application as a local dielectric capacitance proportional to the quotient of total dielectric constant and a local geometric thickness in paragraph [0012], expressed by the equation:
C
d
i
e
l
e
c
t
r
i
c
=
ϵ
ϵ
0
t
Wherein
ϵ
is relative dielectric constant,
ϵ
0
is known as the vacuum permittivity and t is geometric thickness. Given that the elected invention drawn to claim 1 and Fig. 1 comprises a dielectric layer with uniform thickness and vacuum permittivity is constant, the equation is simplified to:
C
d
i
e
l
e
c
t
r
i
c
∝
ϵ
Wherein the local dielectric capacitance is directly proportional to the dielectric constant of the dielectric material at different gate insulating regions.
Referring to the elected device of Fig. 1, a geometric thickness of the first and second gate insulator regions (41 and 42) are the same, while the dielectric constants of the materials are high-k and low-k respectively. Examiner notes that the high-k material M2 of gate insulator region 41 is further defined as the region having “the larger dielectric capacitance” and the low-k material (i.e., silicon dioxide) M1 of gate insulator region 42 is defined as the regions having “the smaller dielectric capacitance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 8, 10, and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang (US 20220238674 A1).
Regarding Claim 1, Zhang teaches a power semiconductor device (1100, shown Fig. 12) comprising:
a semiconductor body (260),
at least one source region (920) in the semiconductor body,
a gate electrode (1224) at the semiconductor body,
a gate insulator (410 and 1226) between the semiconductor body and the gate electrode (shown Fig. 12), and
at least one well region (614) at the at least one source region and at the gate insulator (shown Fig. 12),
wherein the gate insulator has a varying dielectric capacitance (an inherent characteristic due to the different material portions, see also [0032] describing a portion 410 and material selection comprising silicon dioxide and [0034] describing layer 1226 being composed of a different material formed similarly to that of portion 410, such as silicon nitride), the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator at a specific location thereof (as is the definition of dielectric capacitance), the dielectric capacitance is larger at the at least one well region (silicon nitride having a higher dielectric constant than silicon dioxide) than in remaining regions of the gate insulator (when a portion 410 is formed having a lower dielectric constant), and seen in cross-section, the gate insulator is composed of two first gate insulator regions having the larger dielectric capacitance (portions 1226, shown Fig. 12) and of a central, second gate insulator region (410) having the smaller dielectric capacitance,
the at least one well region is in direct contact only with the first gate insulator regions and not with the second gate insulator region (shown Fig. 12).
Regarding Claim 2, Zhang teaches the power semiconductor device according to claim 1, wherein at least one of:
the semiconductor body is of a wide bandgap material or of silicon carbide (see [0026]), and
the power semiconductor device is a field-effect transistor (see [0026]) or an insulated gate bipolar transistor.
Regarding Claim 3, Zhang teaches the power semiconductor device according to claim 1 wherein the gate insulator comprises a first material (silicon dioxide) and a second material (silicon nitride), the second material has a higher relative dielectric constant than the first material, and wherein the second material is a continuous layer completely extending between the gate electrode and the semiconductor body (shown Fig. 12).
Regarding Claim 6, Zhang teaches the power semiconductor device according to claim 3 wherein the gate insulator is of constant geometric thickness (see [0034]) and the first material and the second material are located next to one another in a common plane (shown Fig. 12), and wherein the first material and the second material are in direct contact with the semiconductor body (shown Fig. 12).
Regarding Claim 8, Zhang teaches the power semiconductor device according to claim 1, wherein the gate electrode is of planar configuration so that the gate electrode is located on a top side of the semiconductor body and the top side is of planar fashion (shown Fig. 12, see also [0026] which describes a “planar MOSFET” configuration).
Regarding Claim 10, Zhang teaches the power semiconductor device according to claim 1, wherein the first gate insulator regions are located at edges of the gate electrode and the second gate insulator region is located at a middle portion of the gate electrode (shown Fig. 12).
Regarding Claim 12, Zhang teaches the power semiconductor device according to claim 1, wherein a proportion of the second gate insulator region along an interface of the gate electrode facing the semiconductor body is between 20% and 80% inclusive of an overall extent of said interface (shown Fig. 12), wherein, as seen in cross-section, the first gate insulator regions are located along said interface symmetrically around the second gate insulator region (shown Fig. 12).
Regarding Claim 13, Zhang teaches the power semiconductor device according to claim 1, wherein the dielectric capacitance of the first gate insulator regions is greater than the dielectric capacitance of the second gate insulator region. Further, Zhang teaches that a material of the first gate insulator regions may be silicon nitride and a material of the second gate insulator region may be silicon dioxide, wherein the generally accepted dielectric constants are 7.5 and 3.9 respectively (see also reference from EESemi.com: Table 1). Furthermore, the dielectric capacitance is directly proportional to the dielectric constant of the selected materials, which exhibit a uniform thickness, and thus the first gate insulator regions would have a local dielectric capacitance about 1.9 times greater than that of the second gate insulator region, which is within a range of 1.4 times and at most 6 times the dielectric capacitance of the second gate insulator region.
Regarding Claim 14, Zhang teaches the power semiconductor device according to claim 1 wherein an overall geometric thickness of the gate insulator is between 10 nm and 1.5 microns (see [0028] giving an exemplary thickness of 30 nm to 60 nm for portion 410 and [0034] describing portions 1226 having equal thickness).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 20220238674 A1) in further view of Lichtenwalner (US 20220013650 A1).
Regarding Claim 11, Zhang teaches the power semiconductor device according to claim 1 wherein the at least one source region are of a first conductivity type (n-type), and the at least one well region is of a second conductivity type different from the first conductivity type (p-type), and wherein, as seen in a cross-section, the first gate insulator regions are in contact with the at least one source region and with the at least one well region
Zhang does not explicitly teach a drift region in the semiconductor body, however implementing drift regions in MOSFET devices is common in the art. For example, Lichtenwalner teaches a power semiconductor device analogous to the device of Zhang wherein the power semiconductor device (shown Fig. 4) comprises a semiconductor body (250), at least two source regions (240), well regions (230), a gate electrode (270), a gate dielectric layer (260), a source electrode (290), and further comprises a drift region (220, comprising an n-type dopant to match the source regions, see also [0104]).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement an n-doped drift layer within the semiconductor substrate of Zhang as taught by Lichtenwalner as this would further improve breakdown characteristics and exhibit increased reliability (see Lichtenwalner: [0103]).
As applied to Zhang, this would further teach that the only region of the semiconductor body, with which the second gate insulator region is in contact with, is the drift region (see also Lichtenwalner: Fig. 4), and wherein the first gate insulator is further in contact with the drift region.
Regarding Claim 15, Zhang teaches the power semiconductor device according to claim 1 further comprising at least two source regions (920) wherein, as seen in cross-section, the gate electrode is located between two of the at least two source regions (shown Fig. 12).
Zhang further suggests that contacts would be formed in FEOL processes to complete the planar MOSFET (see [0035]) but does not explicitly show a source electrode formed to contact the at least two source regions.
Lichtenwalner teaches a power semiconductor device analogous to the device of Zhang wherein the power semiconductor device (shown Fig. 4) comprises a semiconductor body (250), at least two source regions (240), well regions (230), a gate electrode (270), a gate dielectric layer (260) and a source electrode (290) which is in electric contact with the at least two of the source regions, the source electrode covers the gate electrode on a side remote from the semiconductor body so that the source electrode is a common electrode for the at least two source regions (shown Fig. 4).
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to implement a common source contact as taught by Lichtenwalner to the device of Zhang as this would enable any number of desired transistors to be electrically connected in parallel (see also [0007]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Lichtenwalner (US 20210336022 A1) teachs a method of controlling an interfacial gate dielectric wherein a gate dielectric (170 and 280, see Fig. 6E) comprises first portions (280a and 280b) disposed at lateral edges and corresponding to source regions (140) and a central second portion (170) disposed over a JFET region of the device.
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/C.P.B./Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893