Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for the examination.
§ 101 2. 35 U.S.C. 101 reads as follows
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 3, 9-12, 13, 17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to Claims 1, 13, 17 , have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, “ identifying a change to a next core allocation that assigns process uniformly across the physical cores ”, “ determining a time that a process of a software application can be moved” and “ identifying a pinned core of the process request” recite a mental process since “determining” and “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claims 2, have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ identifying a pinned core of the process request ”, recite a mental process since “identifying” is functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time, overwriting the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time, overwriting the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claim 3 have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ determining the time that the process”, “ determining one or more interruption time periods having a likelihood of a minimal number of process requests”, recite a mental process since “ determining” is functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time, enabling a change from one core to a different core during an interruption time period of the one or more interruption time periods” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time, enabling a change from one core to a different core during an interruption time period of the one or more interruption time periods”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claim 5 have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ determining the time that the process of the software application can be moved to the next core allocation comprises: determining that the time falls at a prescribed time of day, week, or month ”, “ determining a time that a process of a software application can be moved” recite a mental process since “determining” and “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claims 9-12 have been rejected under 35 USC 101 for abstract idea without significantly more.
Under Step 2A, Prong 1, the “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target length of time for a time period ”, “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target usage amount” , “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target usage amount”, “tracking core utilization of the physical cores of the computing system; and maintaining information of core utilization of the physical cores, wherein identifying the change to the next core allocation according to the allocation pattern is triggered by temperature information” recite a mental process since “determining”, “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
8. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application. See MPEP 2106.05(d). Thus, the claim is not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) and further in view of Iwasa( US 20210117219 A1)
As to claim 1, Reed teaches maintaining a virtual to physical core mapping of physical cores of a computing system( the amount of resources (e.g., processor cores and/or memory) , para[0401], ln 9-14/ A “current resource map” is created and maintained by each hyper-kernel instance. This map describes the current mapping between the virtual resource map and the physical resource map from the point of view of each node., para[0061], ln 1-6)
;
and updating the virtual to physical core mapping for the process of the software application at the determined time( For each entry in the virtual resource map, a definition of the physical resources currently assigned to the virtual resources is maintained. Initially (e.g., at boot time), the current resource map is a copy of the initial virtual resource map. The hyper-kernel modifies the current resource map over time as it observes the characteristics of the resource load and dynamically changes the mapping of physical resources to virtual resources (and vice-versa). For example, the definition of the location of the Ethernet controller eth27 in the virtualized machine may at different times refer to different hardware controllers. The current resource map is used by the hyper-kernel to dynamically modify the virtual hardware resource mappings, such as the virtual memory subsystem, as required, para[0061], ln 3-17).
Horev teaches identifying a change to a next core allocation according to an allocation pattern that assigns processes uniformly across the physical cores ( Adjusting to a Configuration Changes When new compute cores are added to the storage system, part of the shards are removed from their current compute cores and added to new compute cores, so as to adjust the storage system to the compute resource addition. The shards to be removed from current compute cores may be determined by the age of the shards, as will be explained hereinafter. The removed shards may be uniformly and randomly distributed across the new compute cores, para[0062] to para[0064]/ Each shard that is assigned to a compute core is associated with an age, which is defined by the time it was assigned to a specific compute core, or—the time during which the shard is being hosted by the current compute core. Relocation of shards among compute cores will prefer relocating older shards over newer shards, so as not to disrupt, too frequently, the same storage operations being handled by the relocated shard, para[0071]/ Relocating a shard may be associated with some penalty of postponing queued storage operations waiting to be handled by the shard. Therefore, the following measures are taken in order to mitigate transient metrics fluctuations of CPU load: limiting the number of shards removed from a compute core within a time window, taking into account the age of the shards, and redistributing shards in a random manner, para[0069]/ compute workload imposed on the storage system is logically sharded into multiple units called shards. A shard can be regarded as a portion of the total compute workload of the storage system, para[0032]/ Relocation of shards is performed for offloading busy compute cores, or to balance the workload across compute cores, or when the configuration of the storage system is changed and there is a need to divide the existing shards across a larger or a smaller number of compute cores, para[0041]/ Shards of sharded tasks and non-sharded tasks are dynamically assigned to compute cores of the compute nodes of the storage system, para[0037], ln 1-3).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed with Horev to incorporate the above feature because this reduces the load imposed on the compute core by reallocating at least one background task shard of the one or more background task shards to another compute core of the storage system.
Palermo teaches determining a time that a process of a software application can be moved to the next core allocation, wherein the process of the software application is configured with core pinning(The VNF (Virtual Network Function=Virtual Application) can be moved from H to L cores depending on pre-determined indicator (also can refer to as “busy indicator”). The 2nd set of cores can operate at low frequency. CPU config could be either H or L from start (although some implementations may force initial H core setting), para[0216], ln 4-11/ while VNF2 was originally using the L cores 1906, VNF2 is moved at a later time to use a combination of both the L cores 1906 and the H cores 1908, para[0229], ln 6-12/ / In some aspects, in order to use L and/or H cores, a VNF can “pin” to a group of CPU cores (e.g., L cores, H cores, or a combination of L and H cores). As used herein, the term “pin” (or “pinning”) a VNF to processor cores indicates assigning CPU cores used for running/executing the VNF (e.g., virtual CPUs used for executing the VNF) to low or high priority processor cores of a hardware device. In some aspects, a VNF can be statically assigned specific H cores, or L cores, or a combination of both H and L cores at the time of starting the VM associated with the VNF. Additionally, a VNF can be dynamically “pinned” to H or L cores using a taskset (or similar) Linux command. Within the VNF, cores can be distributed/assigned to different functions as needed. For example, FortiGate VNF provides the following command within the VNF, listed in Table 4 below, to assign a core (core mask 0xE) to a package redistribution function, para[0235]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed and Horev with Palermo to incorporate the above feature because this allows a group of CPU cores to run at a higher deterministic frequency without major power increases, allows for extra capacity to support bursts of mobile subscribers' services using the same Edge, MEC Server.
Iwasa teaches determining a time that a process of a software application can be moved to the next core allocation(According to this service providing system, it is possible to complete re-allocation of the new occupied cores to the second virtual machine in a short period of time even in a case in which the computer resources allocated to the second virtual machine immediately after occurrence of a failure are used in a state in which multiple other virtual machines share the resources. Thus, it is possible to recover degradation of performance of the second virtual machine, which occurs due to sharing of the same computer resources, in a short period of time, para[0031]),
wherein the process of the software application is configured with core pinning( Specifically, because each processor (CPU) in the server incorporates a plurality of core circuits, or CPU cores for each chip, it is necessary to allocate the physical CPU cores to virtual CPU cores in units of cores, para[0007], ln 5-10/ Sf31B: Content in definition files of the corresponding virtual machines are updated such that CPU resources are newly dispensed and the physical CPU cores 11 and the virtual CPU cores 12 are fixedly occupied in a one-to-one relationship through the CPU pinning, para[0200]/ The occupied cores 11-X are provided with conditions by a CPU pinging method such that the allocated physical CPU cores 11 and the virtual CPU cores 12 can be used only in a one-to-one state, para[0120]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev and Palermo with Iwasa to incorporate the above feature because this allows a group of CPU cores to run at a higher deterministic frequency without major power increases, allows for extra capacity to enables economical balancing between scalability and reliability, quick provision of services, flexible resource allocation in accordance with demands for each service, and service deployment without restriction by the lifetimes of hardware.
As to claim 13, it is rejected for the same reason as to claim 1 above.
Claim(s) 2, 14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of Guttahalli(US 20160224389 A1).
As to claim 2, Iwasa teaches a process request of the software application( he resource request receiving unit 41 in the resource allocation system 40 receives a resource allocation request from the resource request unit 50 in Step S11 and provides instructions to the VM management unit 42 and the resource dispensing control unit 43, para[0110]/FIG. 2 follows a request from a resource request unit 50 and allocates physical resources 10-1 to 10-4 to be controlled to the respective virtual machines, para[0090], ln 105) ; identifying a pinned core of the process request and overwriting the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping( The occupied cores 11-X are provided with conditions by a CPU pinning method such that the allocated physical CPU cores 11 and the virtual CPU cores 12 can be used only in a one-to-one state. Thus, once an occupied core 11-X is allocated to one virtual CPU core 12, and it is not possible to allocate the occupied core 11-X to another virtual CPU core , para[0102]/ The resource dispensing control unit 43 performs resource dispensing control on the basis of a dispensing request from the resource request unit 50 and an instruction for setting CPU pinning from the VM management unit 42, para[0095], ln 9-15/ the resource dispensing control unit 43 selects more appropriate resources from among the allocatable resources, para[0117], ln 1-3/ selection is made such that the occupied cores 11-X are allocated to the virtual CPU cores 12 of the working systems ACT and the shared cores 11-Y are allocated to the virtual CPU cores 12 of the standby systems SBY in the embodiment. In a case in which the occupied cores 11-X are allocated, the occupied cores 11-X and the virtual CPU cores 12 are linked in one-to-one correspondence using the CPU pinning method, for example. Note that the resource allocations of the physical CPU cores 11 are actually performed and then conditions may be changed such that the allocated resources function as the occupied cores 11-X or the shared cores 11-Y, for example, para[0118]) for the same reason as to claim 2 above.
Guttahalli teaches intercepting a process request of the software application( such hypervisors 32 generally manage execution of the operating systems 30 on the physical resources (e.g., processors 22 and memory 24) by virtualizing the physical resources into virtualized hardware resources. For instance, a hypervisor 32 may intercept requests for resources from operating systems 30 to globally share and allocate resources. The hypervisor 32 may allocate physical processing cycles of shared processor 22 resources by way of virtual processors for a logical partition, para[0019], ln 9-20/ In general, a hypervisor may access a hardware page table (HPT) of each logical partition of the data processing system. Therefore, each logical partition may access its HPT even during the reallocation/optimization process, where the access may be transparent to the operating systems of the logical partition. In addition, for memory pages that are pinned for input/output (I/O) that may have physical addresses in translation control entity (TCE) tables associated with I/O adapters, the hypervisor may mediate to resolve any contention, since the hypervisor has information about the TCE table, and also the physical addresses of the memory pages that are pinned for I/O, para[0043], ln 5-21).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev and Palermo and Iwasa with Guttahalli to incorporate the above feature because this improves logical partition resource allocation management.
As to claim 14, it is rejected for the same reason as to claim 2 above.
As to claim 17, it is rejected for the same reasons as to claims 1 and 2 above.
Claim(s) 3, 15 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of HASHIMOTO( US 20070157209 A1).
As to claim 3, Hashimoto teaches determining the time that the process of the software application can be moved to the next core allocation comprises: determining one or more interruption time periods having a likelihood of a minimal number of process requests of the software application; and enabling a change from one core to a different core during an interruption time period of the one or more interruption time periods( In the case where the program which seizes the resource has a valid time, the resource contention program processing unit 2902 has a function for measuring an execution time of the program with a timer, and reallocating the resource to the program from which the resource is seized, after the valid time has passed. FIG. 34 is a flowchart showing the case of reallocating the resource to the program from which the resource is seized after the valid time of the program which seizes the resource passes. In the case where the program which seizes the resource has a valid time, the resource contention program processing unit 2902 holds that valid time. In the resource contention program processing unit 2902, a timer interrupt occurs at predetermined intervals (S3401), and the time indicated by the timer is updated (S3402). For example, when a program having a certain valid time is activated, the timer is reset and a timer interrupt occurs every 0.1 second. When the timer interrupt occurs, the time indicated at that time is updated to advance 0.1 second. In the case where the time indicated by the timer corresponds to the valid time of the program which has seized the resource (S3403), the resource contention program processing unit 2902 seizes the resource allocated for that program, and notifies the program that the resource is seized by calling the notifyRelease method (S3404), as well as reallocates, by the reserve method, a resource to the program which had been reserving that resource before the program has seized it, with reference to the processing program information held in the processing program information holding unit 2904 (S3405). In addition, the resource contention program distinguishing unit 2901 updates, based on the result, the resource management information held in the resource management information holding unit 2903 and the processing program information held in the processing program information holding unit 2904 (S3406), para[0166]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with HASHIMOTO to incorporate the above feature because this is possible to execute the application program by switching the program to an appropriate one.
As to claim 15, it is rejected for the same reason as to claim 3 above.
Claim(s) 4 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) in view of HASHIMOTO( US 20070157209 A1) and further in view of Reddy( US 9805130 B1).
As to claim 4, Reddy teaches determining one or more interruption time periods having a likelihood of a minimal number of process requests of the software application comprises: determining behavior patterns, from historical process requests of the software application, wherein the behavior patterns include numbers of requests during different periods of time in a day, week, or month; and identifying, from the behavior patterns, the one or more interruption time periods having the likelihood of the minimal number of process requests( he selection rules indicate a threshold value for a given data source. For example, the threshold value indicates the maximum number of search requests that the location search engine 220 should allocate to the given data source, e.g., during a certain duration of time such as an hour, a day, a month, etc., col 13, ln 1-25/ a selection rule is based on the latency of a data source. The latency represents the duration of time a data source requires to provide search results in response to a search request. For instance, as a data source receives an influx of a large number of search requests during a short period of time, a computer server of the data source may be constrained by the availability of computational resources to process the influx of search requests (e.g., saturated thread pools, high CPU or memory usage, delayed messages, or port exhaustion). Consequently, the latency of the computer server increases, which may result in a poor user experience because the user would need to wait a longer duration to receive search results after inputting a search request, col 14, ln 14-27).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo, Iwasa and HASHIMOTO with Reddy to incorporate the above feature because this selects a high quality data source from the available data sources.
Claim(s) 5, 16 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of Venkadasamy( US 20200174839 A1).
As to claim 5, Venkadasamy teaches determining the time that the process of the software application can be moved to the next core allocation comprises: determining that the time falls at a prescribed time of day, week, or month( For example, an application may have projected allocation increases 216 of four processor cores for existing instances and two new application instances over the next three months. If the application requires a minimum of four processor cores per application instance, the application may have a total allocation increase of 12 processor cores (i.e., four processor cores for existing application instances and eight processor cores for new application instances) over the next three months, para[0036], ln 12-23).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with Venkadasamy to incorporate the above feature because this provides mechanisms for efficiently allocating, configuring, and forecasting the use of infrastructure resources for use by applications.
As to claim 16, it is rejected for the same reason as to claim 5 above.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of Ananthakris(US 20190041967 A1).
As to claim 6, Ananthakris teaches updating the virtual to physical core mapping for the process of the software application at the determined time comprises: updating the virtual to physical core mapping of a particular physical core associated with a specified core amity for a software application( he register is partitioned into 8 bit fields, where each field indicates the virtual machine ID associated with a core belongs to. The size of this register can be expanded based on the number of processor cores. As an example, if VIMD_Core® is set to 0, VMID_Core1 set to 1 and VMID_Core2 set to 0, this implies that core0 and core2 are part of the same virtual machine. The mapping of physical core resources to virtual machine can be changed dynamically during run time, allowing for the dynamic reconfiguration of virtual machines based on workload demand., para[0135].
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with Ananthakris to incorporate the above feature because this allocates power budget to ensure fair allocation.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of SUMIDA( US 20110209157 A1).
As to claim 7, Sumida teaches the allocation pattern is sequential( The number of the processor core allocation patterns is determined by the number of the processor cores, and the number of the programs included in the congestion pattern. Specifically, the number of the processor core allocation patterns is N M where N is the number of the processor cores, and M is the number of the programs. Also, the process from step S0608 to a later-described step S0611 form a loop, and all the resource allocation patterns are sequentially selected in step S0608., para[0129], ln 8-20).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with Sumida to incorporate the above feature because this provides an optimal resource allocation pattern among the generated resource allocation patterns as a resource allocation pattern for the programs included in the group of programs based on the calculated total amount of processing.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) and further in view of PENZES(US 20130047166 A1).
As to claim 8, PENZES teaches the allocation pattern comprises assigning the process across the physical cores for a uniform aging of the physical cores( monitored (e.g., by PMU 200). For example, PMU 200 can monitor the aging difference between processor cores 106a and 106b. If the aging difference has exceeded a predetermined aging threshold, as determined by step 302, an instruction assigned to the first processor core (e.g., core 106a) is processed using the second processor core (e.g., core 106b) in step 304 so that cores 106a and 106b is age more evenly. In other words, instructions are reassigned so as to more evenly share the aging, para[0028], ln 6-16/ In an embodiment, PMU 200 monitors aging on processor cores 106 and instructs processor 104 to share the aging burden approximately, or relatively, equally among cores 106 when processing an application. PMU 200 can instruct processor 104 to rotate execution of an application using each, or a subset, of cores 106 so that the aging burden is approximately evenly distributed among cores 106. For example, PMU 200 can instruct processor 104 to rotate execution of an application using each of cores 106 so that a difference in aging among cores 106 does not exceed a predetermined (e.g., user-defined or manufacturer-defined) aging threshold. This can be useful, for example, during execution of multi-media applications (e.g., video games) that require continuous, resource-intensive calculations, which can age a single processor core if the burden is not shared with other core(s). As noted, in one embodiment, it is desirable to more evenly distribute the aging burden among the plurality of processor cores. However, one skilled in the art will recognize that the cores do not have to age exactly equally in order to utilize the benefits of the invention, para[0026])
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with PENZES to incorporate the above feature because this reduces the impact of high load and aging on processor cores in a processor.
Claim(s) 9, 10, 11, 12 are rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1 and further in view of Alverson( US 20230315191 A1).
As to claim 9, Alverson teaches identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target length of time for a time period(the request 116 indicates to switch to a different number of active cores 104 from the first core configuration 208, para[0060], ln 6-10/ ore configuration further includes deactivating one or more cores of the processor without rebooting, para[0024], ln 3-6/ In one or more implementations, at least one of the controller 106, the operating system 110, or an application 112 is configured to determine (or specify) which of the cores 104 to activate based on a number of cores 104 to be activated and based on optimizing for thermal conditions. By way of example, the controller 106, the operating system 110, or the application 112 references a table that specifies which cores 104 of the processor 102 to activate based on a number of active cores 104 and a type of optimization, e.g., thermal. Alternatively or in addition, the controller 106, the operating system 110, and/or the application 112 requests to switch from using cores 104 that are activated at a given time to instead using the cores 104 that are deactivated at the given time (and are potentially cooled down relative to the activated cores), e.g., by activating one or more of those deactivated cores, par[0050]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo and Iwasa with Alverson to incorporate the above feature because this allows a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.
As to claim 10, Alverson teaches identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target usage amount( para[0038], ln 1-20/ para[0050]/ para[0080]/ para[0040], ln 17-29) for the same reason as to claim 9 above.
A to claim 11, Alverson teaches identifying the change to the next core allocation according to the allocation pattern comprises: determining that temperature information satisfies a change condition( para[0038], ln 1-20/ para[0050]/ para[0080]/ para[0040], ln 17-29) for the same reason as to claim 9 above.
As to claim 12, Alverson teaches tracking core utilization of the physical cores of the computing system; and maintaining information of core utilization of the physical cores, wherein identifying the change to the next core allocation according to the allocation pattern is triggered by temperature information, a target length of time for a time period, or a target usage amount indicated by the information of core utilization( para[0038], ln 1-20/ para[0050]/ para[0080]/ para[0040], ln 17-29) for the same reason as to claim 9 above.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) in view of Guttahalli(US 20160224389 A1) and further in view of MULLER(US 20160350117 A1).
As to claim 18, Muller teaches temperature sensors coupled to the plurality of physical cores, wherein the allocator further comprises instructions for reading temperature from the temperatures sensors while tracking usage of the plurality of physical cores for maintaining the information of core utilization of the plurality of physical cores(For instance, where the computing device includes a plurality of processor cores, the automatically controlling assigning of the one or more instructions may comprise automatically reassigning the one or more instructions for processing to another processing core of the plurality of processor cores based, at least in part, on the separately monitored temperatures of the multiple logic units within one or more of the processor cores. As noted, in one or more implementations, each processor core comprises multiple logic units, and each logic unit (or selected logic units) may have associated therewith a temperature sensor in order to closely track the available thermal resources. In one or more enhanced embodiments, the reassigning may include automatically controlling reassigning of the one or more instructions to the another processor core based, at least in part, on the separately monitoring temperatures of the multiple logic units of multiple processor cores, including the another processor core, para[0054], ln 23-27/ With the sensed temperatures regularly updated in a database, such as in the above-illustrated look-up table, the instruction control interface may control instruction assignment based on temperatures of individual logic units within particular processor cores. Thus, fine-grain thermal control of instruction execution within one or more processor cores of the chip may be achieved. Note that the sensed temperature of the core logic units may also be stored in memory to, for instance, predict thermal trends within individual logic units of a processor core, or across the processor, para[0053]).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo, Iwasa and Guttahalli with Muller to incorporate the above feature because this increases in order to achieve increases in processor performance.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) in view of Guttahalli and further in view of Jain( US 20170199798 A1).
As to claim 19, Jain teaches counters coupled to the plurality of physical cores, wherein the counters track counts of certain operations, wherein the allocator further comprises instructions for reading the counts of the certain operations while tracking usage of the plurality of physical cores for maintaining the information of core utilization of the plurality of physical cores ( FIG. 17, the compute node may include four cores 1710, where each core includes four hardware threads. A unique PURR may correspond to each individual hardware thread, and be configured to monitor the processing activity and degree of usage of its corresponding hardware thread. In embodiments, the PURR may be configured to track (e.g., count) the number of jobs scheduled on a given hardware thread by the hypervisor. As an example, Logical CPU 3 of Core 2 may be determined to have a job count of 99, while Logical CPU 1 of Core 3 may have a job count of 65, as computed by each PURR respectively. Other methods of tracking the utilization of each core are also possible. In embodiments, monitoring the set of physical cores may include tracking processing time and processor utilization at block 1915. In certain embodiments, the processing time and processor utilization may be tracked using a set of processor utilization resource registers (PURRs). As described herein, a PURR may include a type of register configured to calculate and track processor time and utilization in a simultaneous multi-threading (SMT) environment. In embodiments, a single PURR may correspond to a single hardware thread, and be configured to track (e.g., count) the number of jobs scheduled on a given hardware thread by the hypervisor, para[0124], ln 2-17 to para[0128], ln 1-15).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo, Iwasa and Guttahalli with Jain to incorporate the above feature because this optimizes resource use by leveraging a metering capability at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts) and Resource usage can be monitored, controlled, and reported providing transparency for both the provider and consumer of the utilized service.
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over in view of Reed( US 20190149399 A1) in view of Horev(US 20220269426 A1) in view of Palermo( US 20200125389 A1) in view of Iwasa( US 20210117219 A1) in view of Guttahalli and further in view of Ramakrishna(US 20160028647 A1).
As to claim 20, Ramakrishna teaches the allocator interfaces with an operating system stored on the system memory( Moreover, in some implementations, the memory 510 or the non-transitory computer readable storage medium of the memory 510 stores the following programs, modules and data structures, or a subset thereof including an optional operating system 511, network resource data 520, subscriber/user profile data 530, an analytics module 540, a resource reallocation module 550, and an inter-client reallocation module 560, para[0047], ln 14-27).
It would have been obvious to one of the ordinary skill in the art before the effective filling date of claimed invention was made to modify the teaching of Reed, Horev, Palermo, Iwasa and Guttahalli with Ramakrishna to incorporate the above feature because this enables client device participation in the allocation of the network resource.
Response to the argument:
A. Applicant amendment filed on 05/12/2026 has been considered but they are not persuasive:
Applicant argued in substance that :
(1) “ In view of the foregoing, claims 1, 13, and 17 recite a specific technological improvement in operation of a computing system, such that the claims integrate any alleged judicial exception into a practical application and are therefore not directed to an abstract idea”.
(2) “ Kwon fails to teach or suggest "identifying a change to a next core allocation according to an allocation pattern that assigns processes uniformly across the physical cores," as recited in amended claim 1.”.
30. Examiner respectfully disagreed with Applicant's remarks:
B. As to the point (1), As to Claims 1, 13, 17 , have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, “ identifying a change to a next core allocation that assigns process uniformly across the physical cores ”, “ determining a time that a process of a software application can be moved” and “ identifying a pinned core of the process request” recite a mental process since “determining” and “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion. Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f). Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claims 2, have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ identifying a pinned core of the process request ”, recite a mental process since “identifying” is functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time, overwriting the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time, overwriting the pinned core of the process request with an allocated core indicated by the virtual to physical core mapping”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claim 3 have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ determining the time that the process”, “ determining one or more interruption time periods having a likelihood of a minimal number of process requests”, recite a mental process since “ determining” is functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time, enabling a change from one core to a different core during an interruption time period of the one or more interruption time periods” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time, enabling a change from one core to a different core during an interruption time period of the one or more interruption time periods”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claim 5 have been rejected under 35 USC 101 for abstract idea without significantly more. Under Step 2A, Prong 1, the “ determining the time that the process of the software application can be moved to the next core allocation comprises: determining that the time falls at a prescribed time of day, week, or month ”, “ determining a time that a process of a software application can be moved” recite a mental process since “determining” and “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to Claims 9-12 have been rejected under 35 USC 101 for abstract idea without significantly more.
Under Step 2A, Prong 1, the “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target length of time for a time period ”, “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target usage amount” , “ identifying the change to the next core allocation according to the allocation pattern comprises: determining that a core's usage has satisfied a target usage amount”, “tracking core utilization of the physical cores of the computing system; and maintaining information of core utilization of the physical cores, wherein identifying the change to the next core allocation according to the allocation pattern is triggered by temperature information” recite a mental process since “determining”, “identifying” are functions that can be reasonably performed in the human mind with the aid of pen and paper through observation, evaluation, judgment, opinion.
Under Prong 2, the additional element “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning; and updating the virtual to physical core mapping for the process of the software application at the determined time” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception, Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, the additional elements “ maintaining a virtual to physical core mapping of physical cores of a computing system, the process of the software application is configured with core pinning”-this generally have been a mental process although the software application could be a generic computer component described in its actual computer hardware and “updating the virtual to physical core mapping for the process of the software application at the determined time”- this is mere instructions to apply the mental process under mpep 2106.05(f), amounts to merely generally linking the use of the judicial exception to a particular technological environment or field or use, and is merely applying the judicial exception, therefore, does not amount to significantly more, hence, cannot provide an inventive concept.
As to the point (2), Horev teaches Adjusting to a Configuration Changes When new compute cores are added to the storage system, part of the shards are removed from their current compute cores and added to new compute cores, so as to adjust the storage system to the compute resource addition. The shards to be removed from current compute cores may be determined by the age of the shards, as will be explained hereinafter. The removed shards may be uniformly and randomly distributed across the new compute cores, para[0062] to para[0064]/ Each shard that is assigned to a compute core is associated with an age, which is defined by the time it was assigned to a specific compute core, or—the time during which the shard is being hosted by the current compute core. Relocation of shards among compute cores will prefer relocating older shards over newer shards, so as not to disrupt, too frequently, the same storage operations being handled by the relocated shard, para[0071]/ Relocating a shard may be associated with some penalty of postponing queued storage operations waiting to be handled by the shard. Therefore, the following measures are taken in order to mitigate transient metrics fluctuations of CPU load: limiting the number of shards removed from a compute core within a time window, taking into account the age of the shards, and redistributing shards in a random manner, para[0069]/compute workload imposed on the storage system is logically sharded into multiple units called shards. A shard can be regarded as a portion of the total compute workload of the storage system, para[0032]/ Relocation of shards is performed for offloading busy compute cores, or to balance the workload across compute cores, or when the configuration of the storage system is changed and there is a need to divide the existing shards across a larger or a smaller number of compute cores, para[0041]/ Shards of sharded tasks and non-sharded tasks are dynamically assigned to compute cores of the compute nodes of the storage system, para[0037], ln 1-3).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
US 20170315835 A1 teaches configuring of the first vm comprises pinging the first vm to run only on the subset 106 of cores.
US 20120159507 teaches A1 Referring to FIG. 8E, if one or more of the tasks having a parallel relationship therebetween are allocated to a different physical core from its preceding task, the stage adjuster 702 may match the pipeline stages of the tasks such that they can be executed at the same pipeline stage.
US 20140156901 A1 teaches The dimension is determined by the number of external pins of the input, as further described below, and the duration is determined and constrained by memory capacity of each one of the computational cores 100. The computational layer 1 and each one of the computational cores 100 are adaptively reconfigurable in time. The configuration at the computational cores 100 level is manifested by allocation of available cores for a specific sub-instruction, as described below in relation to FIG. 17B, while the other sub-instruction may be executed with different configuration of the computational cores.
US 20220058123 A1 teaches between a processing unit and a portion of the cache. As an example, if an application is running on core , and reading and writing a data from/to slice 1 is faster than from, e.g., slice 2 to slice 8, assuming a CPU socket with eight cores, an association may be determined, or created, between core 1 and slice 1.
US 20130081044 A1 teaches any processing cores remaining unallocated are allocated, one core per program at a time, among the application programs whose demand 130 for processing cores had not been met by the amounts of cores so far allocated to them by preceding iterations of this step (ii) within the given run of the algorithm 310.
US 20160011645 A1 teaches FIG. 12A shows a situation in which five tasks are relatively uniformly distributed in a first core Core_1 to a fourth core Core_4. It may be assumed that CPU driving voltage and driving clock of each of the first core Core_1 and the fourth core Core_4 is not high. When sampling is performed under the assumption, the CPU driving voltage and driving clock (VF) may be low and the number of runnable tasks may be five.
US 20120266179 A1 teaches If the first logical core typically has a higher workload than other logical cores, its higher workload, in many instances, can be distributed more-evenly across physical cores without having to reboot the processor.
US 20130047166 A1 teaches the processor to take action such that aging, temperature, and/or increased load are approximately evenly distributed across the processor cores, so that the processor can continue to efficiently process instructions.
US 20200195711 A1 teaches Disclosed below are different schemes that allow LB 101 to evenly or otherwise appropriately distribute load across NF servers or among cores in an NF server. The different schemes may include weighted round robin (static), traffic-based, model-based, feedback-based, or model and feedback-based.
US 20070300086 A1 teaches a first thread is assigned to the first processor core or to the second processor core based on the first data and the second data. According to some embodiments of 203, the processor core scheduler 106 assigns the first thread based on wear (or aging) of the first processor core 102 and the second processor core 104. In this regard, the first data and the second data may indicate that the second processor core 104 exhibits greater wear than the first processor core 102. Accordingly, in order to distribute processor core wear evenly throughout the processor die 101, the processor core scheduler 106 may assign the first thread to the first processor core 102 at 203.
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/LECHI TRUONG/Primary Examiner, Art Unit 2194
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