DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 08/31/2023 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Chow et al. (U.S. 6,828,775).
Regarding claim 1, Chow et al. (hereinafter, Ref~775) discloses (please see Fig. 3 and related text for details) a circuit (300 of Fig. 3), comprising:
an amplifier (310/312/314 of Fig. 3), including:
a voltage input circuit (310 of Fig. 3) having a first input (non-inverting terminal of 310 of Fig. 3), a second input (inverting terminal of 310 of Fig. 3), a first output (disposed at gate of 312 of Fig. 3), and a second output (disposed at the gate of 314 of Fig. 3) as seen;
an output driver (312/314 of Fig. 3) having a first input (gate of 312 of Fig. 3) coupled to the first output of the voltage input circuit, a second input (gate of 314 of Fig. 3) coupled to the second output of the voltage input circuit, a feedback input (e.g. see input from 350 provided for FORCE CURRENT path as seen from Fig. 3), and an output (320 of Fig. 3);
a first feedback circuit (e.g. centered by circuit 340 of Fig.3) having a first terminal (e.g., non-inverting terminal or inverting terminal of 340 of Fig. 3) coupled to the output of the output driver, and a second terminal (output terminal of 340 of Fig. 3) coupled (via resistor 318 of Fig. 3) to the second input of the voltage input circuit;
a sensing resistor (330 of Fig. 3) having a first terminal (disposed to the left of 330 of Fig. 3) coupled to the output of the output driver, and a second terminal (disposed to the right of 330 of Fig. 3); and
a first switch (350 of Fig. 3 can be read as the claimed switch OR at least it is functionally equivalent to it) having a first terminal (used by FORCE CURRENT TERMINAL of Fig. 3) coupled to the second terminal of the sensing resistor, and a second terminal (disposed between 350 and 318 of Fig. 3) coupled to the feedback input of the output driver, meeting claim 1.
Regarding claim 12, Ref~775 discloses the circuit of claim 1, wherein the first feedback circuit includes a current sensing circuit (circuit 340 of Fig. 3 ) having a first input coupled to the first terminal of the sensing resistor, a second input coupled to the second terminal of the sensing resistor, and an output (345 of Fig. 3) coupled to the second input of the voltage input circuit as seen, meeting claim 12.
Allowable Subject Matter
Claims 2-11 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 14-17 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “a first current generator having an input coupled to a first feedback terminal of the output driver, and an output; a first voltage generator having an input coupled to the output of the first current generator, and an output; and a first gate driver having a first input coupled to the output of the first voltage generator, a second input coupled to a second feedback terminal of the output driver, and an output coupled to the third input of the output driver” structurally and functionally interconnected with other limitations in the manner as cited in the claim(s).
Claims 18-20 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “wherein the first feedback circuit includes a sensing resistor having a first terminal coupled to the first terminal of the first feedback circuit, and a second terminal; a first switch having a first terminal coupled to the first terminal of the sensing resistor, and a second terminal coupled to the feedback input of the force amplifier; and a second switch having a first terminal coupled to the second terminal of the sensing resistor, and a second terminal coupled to the feedback input of the force amplifier” structurally and functionally interconnected with other limitations in the manner as cited in the claim(s).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843