DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Li et al (US20150036437).
Regarding claim 18, Li discloses a method of fabricating an electronic device(FIG 1 & 12; [0025-0027, 0033 & 0064-0065; 102 1200), the method comprising: forming a gate dielectric layer over a surface of a channel region of a semiconductor substrate(FIG 1; 112 over 104), the channel region including majority charge carriers of a second conductivity type(FIG 1; [0025 & 0033]; channel having charges carries of a second type); forming a gate structure with opposite first and second sidewalls over the gate dielectric layer(FIG 1;[0026]; 106 having first and second sidewall 124 160) implanting dopants of the second conductivity type under the first sidewall of the floating gate while blocking the dopants from the second sidewall of the floating gate(FIG 1; [0025-0027 & 0033] ; and implanting dopants of an opposite first conductivity type into the substrate adjacent the first and second sidewalls of the gate structure(FIG 1; [0026 & 0033] discloses 106 having high -k dielectric layer 112 that is formed on surface of 104, and adjacent to spacer 124 and 160, having conductivity type), thereby forming first and second source/drain regions (FIG 1; [0026 & 0033] having source and drain 116 and 120 having high doped in regions in substate opposite conductivity of substrate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of Hebert et al (US20020117714).
Regarding claim 1, Li discloses an electronic device(FIG 1), comprising a non-volatile memory cell including(102): a channel region having a first conductivity type between first and second source/drain regions having an opposite second conductivity type over a semiconductor substrate, the channel region touching the first source/drain region(FIG 1; [0025& 0033] discloses 190 between 120 and 116 having first type opposite of 120 and 116 over 104) ; a gate structure over the channel region(top), the gate structure including a gate dielectric layer over the channel region and a floating gate over the gate dielectric layer(112 and floating gate 160 over 112); and an enhanced channel region (116 extending).
However, LI does not disclose having the first conductivity type touching the second source/drain region and the channel region at a surface of the substrate.
In the same field of endeavor, Hebert discloses an enhanced channel region having the first conductivity type touching the second source/drain region and the channel region at a surface of the substrate (FIG 5; source and drain region 70A and 66B, and an enhanced channel region 66A having N type touching the source 70A and channel region at surface of substrate).
Li and Hebert are analogous art because they are all directed to a device comprising a MOS transistor comprising a body, a drain and a source and one of ordinary skill in the art would have had a reasonable expectation of success by modify Li to include Hebert because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Hebert in the teachings Li for the benefits avoiding a breakdown that causes undesirable current to flow between the drain and the body or the drain and source, which eventually will cause the device to a failure. (0003 Hebert).
Regarding claim 2, the combination of Li in view of Hebert disclose wherein: the enhanced channel region extends from under a first end of the floating gate toward an opposite second end of the floating gate at the surface of the substrate (FIG 1; 116 extending from one end of the floating gate toward an opposite second end of floating gate).
Regarding claim 9, the combination of Li in view of Hebert discloses wherein the first conductivity type is p-type and the second conductivity type is n-type (FIG 1; [0031-0033] first conductivity p-type ands second n-type).
Claim(s) 4, 7, 10 & 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of Hebert et al further in view of Harari et al (US5554553).
Regarding claim 4, the combination of Li in view of Hebert discloses comprising the non-volatile memory cell (FIG 1).
However, the combination Li in view of Hebert do not disclose a read circuit configured to identify a program state of the non-volatile memory cell as one of a first state, a second state, and a third state based on a cell voltage of the non-volatile memory cell, the first, second, and third states being different from one another.
In the same field of endeavor, Harari discloses a read circuit configured to identify a program state of the non-volatile memory cell as one of a first state, a second state, and a third state based on a cell voltage of the non-volatile memory cell, the first, second, and third states being different from one another (FIG 11e; col 25, lines 44 – lines 57 discloses reading circuit SA identifying three different states).
Li in view of Hebert and Harari are analogous art because they are all directed to a device comprising a MOS transistor comprising a body, a drain and a source and one of ordinary skill in the art would have had a reasonable expectation of success by modify Li in view of Hebert to include Harari because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Harari in the teachings Li in view of Hebert for the benefits a device with a memory transistor that can provide a technique for increasing the amount of information that can be stored in a given size of the memory cell. (; col 2, lines 42-44 Harari).
Regarding claim 7, the combination of Li in view of Hebert discloses comprising the non-volatile memory cell (FIG 1 & 11).
However, the combination Li in view of Hebert do not disclose a write circuit configured to selectively set a program state of the non-volatile memory cell to one of a first state, a second state, and a third state, the first, second, and third states being different from one another.
In the same field of endeavor, Harari discloses a write circuit configured to selectively set a program state of the non-volatile memory cell to one of a first state, a second state, and a third state, the first, second, and third states being different from one another (FIG 11e; col 25, lines 14- line 43 discloses writing circuit VPWL programming pulse generator having memory cell to be programmed into any one of the four conduction states different from each other).
Li in view of Hebert and Harari are analogous art because they are all directed to a device comprising a MOS transistor comprising a body, a drain and a source and one of ordinary skill in the art would have had a reasonable expectation of success by modify Li in view of Hebert to include Harari because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Harari in the teachings Li in view of Hebert for the benefits a device with a memory transistor that can provide a technique for increasing the amount of information that can be stored in a given size of the memory cell. (col 2, lines 42-44 Harari).
Regarding claim 10, the combination of Li in view of Hebert discloses comprising the non-volatile memory cell (Li FIG 1) is selectively programmable to change a program state of the non-volatile memory cell from a first state to: a second state; or a third state (Harari FIG 11e; col 25, lines 14- line 43 discloses writing circuit VPWL and VPBL programming pulse generator having memory cell to be programmed into any one of the four conduction states different from each other).
Regarding claim 12, the combination of Li in view of Hebert further in view of Harari disclose wherein: the non-volatile memory cell is selectively programmable to change the program state from the first state to the second state by applying a programming voltage signal to the second source/drain region; and the non-volatile memory cell is selectively programmable to change the program state from the first state to the third state by applying the programming voltage signal to the first source/drain region (FIG 11e discloses having it line VPBL and word line VPWL programming pulse generator, wherein pulses are applied to both selected word and bit line).
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al in view of Harari et al.
Regarding claim 13, Li discloses a non-volatile memory, comprising(FIG 1): a non-volatile memory cell with an asymmetric floating gate cell transistor selectively programmable(FIG 1; 102), the non-volatile memory cell comprising an asymmetrical channel region between a first source/drain region and a second source/drain region in a substrate under a floating gate(FIG 1; [0025& 0033] discloses 190 between 120 and 116 in 104 and under floating gate 160), the asymmetrical channel region having an enhanced channel region adjacent the first source/drain region at a surface of the substrate(116 extending).
However, Li does not disclose to change a program state from a first state to a second state or a third state and a read circuit configured to identify the program state of the non-volatile memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell.
In the same field of endeavor, Harari discloses to change a program state from a first state to a second state or a third state and a read circuit configured to identify the program state of the non-volatile memory cell as one of the first state, the second state, and the third state based on a cell voltage of the non-volatile memory cell (FIG 11e; col 25, lines 44 – lines 57 discloses reading circuit SA identifying three different states).
Li and Harari are analogous art because they are all directed to a device comprising a MOS transistor comprising a body, a drain and a source and one of ordinary skill in the art would have had a reasonable expectation of success by modify Li t to include Harari because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Harari in the teachings Li for the benefits a device with a memory transistor that can provide a technique for increasing the amount of information that can be stored in a given size of the memory cell. (col 2, lines 42-44 Harari).
Regarding claim 14, the combination of Li in view of Harari discloses comprising a write circuit configured to selectively change the program state from the first state to the second state by applying a programming voltage signal to the first source/drain region and to selectively change the program state from the first state to the third state by applying the programming voltage signal to the second source/drain region (Harari FIG 11e; col 25, lines 14- line 43 discloses writing circuit VPWL programming pulse generator having memory cell to be programmed into any one of the four conduction states different from each other by applying signal to s/d e.g., VPWL and VPBL).
Regarding claim 15, the combination of Li in view of Harari discloses wherein: the first source/drain region and the second source/drain region include majority charge carriers of a first conductivity type; and the asymmetrical channel region and the enhanced channel region include majority charge carriers of an opposite second conductivity type (FIG 1; [0025& 0033] discloses 190 between 120 drain and 116 source having first type opposite of 120 and 116 comprising charges).
Allowable Subject Matter
Claim 3, 5-6, 8, 11, 16-17 & 19-20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 11/12/2025 have been fully considered but they are not persuasive. The applicant has stated that in pages 8-10 “Moreover, the claim requires that the channel region and enhanced channel region both have a same (first) conductivity type. Because the source region 116 and channel region (substrate 104) have different conductivity types, the claim does not read on "116 extending" as currently relied upon”.
In response to the arguments presented above by the applicant, the examiner respectfully disagreed. For example, the examiner clearly has distinguished in the rejection of claim 1 that, Hebert discloses an enhanced channel region having the first conductivity type touching the second source/drain region and the channel region at a surface of the substrate (FIG 5; source and drain region 70A and 66B, and an enhanced channel region 66A having N type touching the source 70A and channel region at surface of substrate). Li discloses having a first and second type of conductivity e.g, (FIG 1; [0025& 0033] discloses 190 between 120 and 116 having first type opposite of 120 and 116 over 104), therefore since Li and Hebert directed to a device comprising a MOS transistor comprising a body, a drain and a source and one of ordinary skill in the art would have had a reasonable expectation of success by modify Li to include Hebert because they are from the same field of endeavor for the benefits of avoiding a breakdown that causes undesirable current to flow between the drain and the body or the drain and source, which eventually will cause the device to a failure. (0003 Hebert). Unless, a clear distinguish is made e.g., as cited in claim 3 “the channel region has a first majority charge carrier concentration of the majority charge carriers of the second conductivity type; and the enhanced channel region has a second majority charge carrier concentration of the majority charge carriers of the second conductivity type that is greater than the first majority charge carrier concentration”, the rejection Li et al in view of Hebert et al is maintained.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Jain et al (US10741719 FIG 5a; discloses p type substrate 14 and s/d having n type 24 and 25, and floating gate formed by 37 and 39).
Morton et al (US20070064494 FIG 1; [0076-0078] discloses gate 130, Source and drain 124 and extended 120 on p-type substrate 110)
Lin et al (US20210328034 11A-11E; [0060-0063] discloses source and drain, wherein the source regions extend. The source region 132 and drain region 138 are implant dopants of a second conductivity type into discrete surface portions of 10, wherein the second type is opposite of first conductivity type).
Grote et al (US10833174 2; claim 2 discloses extended drain regions into a first vertical component sidewall and into second vertical component sidewall, wherein a bottom portion has a greater concentrate of first conductivity type dopants than the vertical component)
Higashitani et al (US20090166704 FIG 7-8; discloses write and read circuits).
Gossner et al (US20060289933 FIG 4), Horch et al (US2006020120 FIG 1), Yun et al (US20060110880 FIG 5), Morton et al (US6548874 FIG 4B), & Lee et al (US20020028541 FIG 11B).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUNA A TECHANE/Primary Examiner, Art Unit 2827