CTNF 18/240,692 CTNF 86585 DETAILED ACTION This office action is in response to application 8/31/2023. Claims 1 – 20 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 – 6 and 8 – 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raman et al (US 20170109214, hereinafter Raman) , in view of Wang et al (US 20170315846, hereinafter Wang) , and further in view of Mo et al (USPAT 10754706, hereinafter Mo) . As per claim 1, Raman discloses: An accelerator device, comprising: a processing element array; a memory configured to store a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between the tasks within the fibers; (Raman figure 3 and [0045]: each of the task 304 and 306 are mapped to the claimed fiber including 1 or more tasks, and in the scenario where the fiber only includes 1 task, the dependency of tasks within the fiber is null.) and a command processor configured to perform operations including: dispatching a task from a fiber for execution by the processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved; (Raman [0045]: “A task may include state information that identifies whether the task is launched, ready, or finished… A task is in the ready state when all of its dependencies or prerequisites for execution have been met (e.g., all of its predecessors have finished execution), and is waiting to be assigned to the next available thread.”; figure 6 and [0051] – [0053]: “In determination block 602, the computing device may determine whether a ready queue is empty… In response to determining that the ready queue is not empty (i.e., determination block 602=“No”), the computing device may remove a ready task from the ready queue in block 606. In block 608 the computing device may execute the ready task.”) Raman did not explicitly disclose: enqueueing the fiber in a sleep queue while the task is dispatched and unexecuted by the processing element array; enqueueing the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array; and enqueuing a dependent fiber that depends from the fiber in the ready queue based on the fiber being enqueued in the check queue. However, Wang teaches: enqueueing the fiber in a sleep queue while the task is dispatched and unexecuted by the processing element array; (Wang figure 3 and [0067]: “a condition on which the executing state of the task changes to the interruptible sleep state is that a task resource is not ready and the task is waiting for the resource; a condition on which the interruptible sleep state of the task changes to the ready state is that the resource required by the task is readily available”.) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Wang into that of Raman in order to enqueue the fiber in a sleep queue while the task is dispatched and unexecuted by the processing element array. Raman [0047] teaches “as soon as the GPU task 306 b becomes ready for execution (in task scheduling, a task is said to be ready when all its predecessor tasks have finished execution), it is dispatched 406 to the GPU 402”. Wang figure 3 shows that task in executing state (dispatched state as claimed) can be placed in interruptible sleep state when resource is not ready for the task, such combination would allow tasks that are dispatched to a resource be placed in a sleep state if the necessary resource is not yet ready to execute the dispatched task, and improves the efficiency of the system, and is therefore rejected under 35 USC 103. Mo teaches: enqueueing the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array; and enqueuing a dependent fiber that depends from the fiber in the ready queue based on the fiber being enqueued in the check queue. (Mo col 8, lines 29 – 37: “Initially, the scheduler assigns CPU 1 to run task T01 and CPU 2 to run task T02. During execution, task T01 generates child tasks T05 and T06. Because these are new tasks, the scheduler classifies them as short-running tasks and adds them to the front of the task queue. Because parent task T01 cannot continue until tasks T05 and T06 complete, the scheduler reassigns CPU 1 to run child task T05, which was at the front of the task queue. Task T06 continues to wait in the queue, while task T02 continues to run on CPU 2”.) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mo into that of Raman and Wang in order enqueue the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array; and enqueuing a dependent fiber that depends from the fiber in the ready queue based on the fiber being enqueued in the check queue. It is commonly known in the field that affinity-based scheduling would queue children/dependent tasks on the same core or processor as the parent in order to maximize data locality and cache hits, such combination merely claims the combination of known parts in the field to achieve predictable results of improve cache hits and improvement of overall efficiency of the scheduling system and is therefore rejected under 35 USC 103. As per claim 2, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, the operations further including dispatching an additional task from the dependent fiber based on the dependent fiber being enqueued in the ready queue and the dependencies of the additional task being resolved. (Raman [0047]: “As soon as the GPU task 306 b becomes ready for execution (in task scheduling, a task is said to be ready when all its predecessor tasks have finished execution), it is dispatched 406 to the GPU 402”.) As per claim 3, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein an additional fiber is enqueued ahead of the fiber in the ready queue and the dependencies of an additional task in the additional fiber are resolved, the task being dispatched before the additional task based on the fiber being assigned a higher priority than the additional fiber. (Wang [0067]: “A condition on which the ready state of the task changes to the executing state is that the task participates in scheduling, and the priority of the task is the highest”.) As per claim 4, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein enqueuing the fiber in the check queue includes: moving the fiber from the sleep queue to the ready queue responsive to receiving a completion signal indicating that the task has been executed by the processing element array; (Raman [0031]: “During execution of the common property task graph, task completion signals may be sent to notify dependent tasks outside of the common property task graph of the completion of the task upon which the dependent task depends. Whether a task completion signal is sent after the completion of a task but before the completion of the common property task graph may depend on the dependency and criticality of the dependent task outside of the common property task graph.”; Wang [0067]: “a condition on which the interruptible sleep state of the task changes to the ready state is that the resource required by the task is readily available.”) dispatching an additional task from the fiber based on the fiber being in the ready queue and the dependencies of the additional task being resolved; (Raman [0051] – [0053]: “In determination block 602, the computing device may determine whether a ready queue is empty… In response to determining that the ready queue is not empty (i.e., determination block 602=“No”), the computing device may remove a ready task from the ready queue in block 606. In block 608 the computing device may execute the ready task.”) and moving the fiber from the ready queue to the sleep queue while the additional task is dispatched and unexecuted by the processing element array. (Wang figure 3 and [0067]: “a condition on which the executing state of the task changes to the interruptible sleep state is that a task resource is not ready and the task is waiting for the resource; a condition on which the interruptible sleep state of the task changes to the ready state is that the resource required by the task is readily available”.) As per claim 5, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 4, wherein enqueueing the fiber in the check queue includes: moving the fiber from the sleep queue to the ready queue responsive to receiving an additional completion signal indicating that the additional task has been executed by the processing element array; and moving the fiber from the ready queue to the check queue based on the one or more tasks of the fiber having been executed by the processing element array. (Wang [0067]; Raman figure 6 and [0051] – [0053] and Mo col 8, lines 29 – 37.) As per claim 6, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 4, wherein an additional fiber is enqueued ahead of the fiber in the sleep queue, and moving the fiber to the ready queue includes waiting for a dispatched task of the additional fiber to be executed before processing the completion signal of the task. (Wang [0067] and Mo col 8, lines 29 – 37.) As per claim 8, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein enqueuing the dependent fiber in the ready queue includes: retrieving the dependent fiber from the memory based on the dependent fiber being identified using the fiber graph; and enqueueing the dependent fiber in the ready queue based on the dependent fiber having a resolved dependency on the one or more tasks of the fiber. (Mo col 8, lines 29 – 37.) As per claim 9, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein the ready queue, the sleep queue, and the check queue are single-producer, single-consumer queues based on a first thread of the command processor managing the ready queue, and a second thread of the command processor managing the sleep queue and the check queue. (Raman [0044]: single entry point.) As per claim 10, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein dispatching the task includes selecting, in accordance with a load balancing policy, a processing element of the processing element array to which the task is to be dispatched, the load balancing policy indicating to balance workloads dispatched to each processing element of the processing element array. (Mo col 7, lines 4 – 17: load balancing.) As per claim 11, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein dispatching the task includes selecting, in accordance with a locality policy, a processing element of the processing element array to which the task is to be dispatched, the locality policy indicating to dispatch the one or more tasks of each respective fiber to a same respective processing element of the processing element array. (Mo col 8, lines 29 – 37: execute children tasks on the same core as parent.) As per claim 12, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein enqueuing the fiber in the sleep queue includes: placing the fiber in a sleep pool while the task is dispatched and unexecuted by the processing element array; and enqueuing, by the processing element array and responsive to the task being executed, a wakeup command in the sleep queue that identifies the fiber. (Wang figure 3 and [0067].) As per claim 13, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 12, wherein enqueuing the fiber in the check queue includes: looking up the fiber in the sleep pool based on the wakeup command being enqueued in the sleep queue; and retrieving the fiber from the sleep pool. (Wang figure 3 and [0067].) As per claim 14, the combination of Raman, Wang and Mo further teach: The accelerator device of claim 1, wherein the ready queue, the sleep queue, and the check queue are first-in-first-out queues. (Raman [0028]: FIFO.) As per claim 15, is the is method variant of claim 1 and is therefore rejected under the same rationale. As per claim 16, the combination of Raman, Wang and Mo further teach: The method of claim 15, wherein the fiber includes a set of operations instructing the command processor to process the fiber, and the dependent fiber is enqueued in the ready queue based on a wake fiber operation in the set of operations that identifies the dependent fiber. (Wang figure 3 and [0067] and Mo col 8, lines 29 – 37.) As per claim 17, the combination of Raman, Wang and Mo further teach: The method of claim 16, wherein the wake fiber operation is placed within the set of operations after an operation to enqueue the task in the ready queue based on a final task of the fiber having been executed by the processing element array. (Wang figure 3 and [0067]; Mo col 8, lines 29 – 37.) As per claim 18, Raman discloses: A system, comprising: an accelerator device that includes a command processor and a processing element array; and a host configured to compile operations for executing a fiber graph that includes fibers each having one or more tasks and indicates dependencies between the fibers and between the tasks within the fibers, (Raman figure 3 and [0045]: each of the task 304 and 306 are mapped to the claimed fiber including 1 or more tasks, and in the scenario where the fiber only includes 1 task, the dependency of tasks within the fiber is null; [0028]: scheduler executing on a device can create and schedule a task graph.) the operations instructing the command processor to: dispatch a task from a fiber for execution by the processing element array based on the fiber being enqueued in a ready queue and the dependencies of the task being resolved; (Raman [0045]: “A task may include state information that identifies whether the task is launched, ready, or finished… A task is in the ready state when all of its dependencies or prerequisites for execution have been met (e.g., all of its predecessors have finished execution), and is waiting to be assigned to the next available thread.”; figure 6 and [0051] – [0053]: “In determination block 602, the computing device may determine whether a ready queue is empty… In response to determining that the ready queue is not empty (i.e., determination block 602=“No”), the computing device may remove a ready task from the ready queue in block 606. In block 608 the computing device may execute the ready task.”) Raman did not explicitly disclose: push the fiber to a tail of the ready queue based on the task being dispatched and unexecuted by the processing element array; enqueue the fiber in a check queue based on the fiber being enqueued in the ready queue and the one or more tasks of the fiber having been executed by the processing element array; and enqueue a dependent fiber that depends from the fiber in the ready queue based on the fiber being in the check queue. However, Wang teaches: push the fiber to a tail of the ready queue based on the task being dispatched and unexecuted by the processing element array; (Wang [0103]: “If the task at the head of the ready queue Lu is not ready in S202, the process proceeds to S203: Wait for the task to be ready, and move the task from the head of the non-ready queue Lu to the tail of Lu.”) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Wang into that of Raman in order to enqueue the fiber in a sleep queue while the task is dispatched and unexecuted by the processing element array. Raman [0047] teaches “as soon as the GPU task 306 b becomes ready for execution (in task scheduling, a task is said to be ready when all its predecessor tasks have finished execution), it is dispatched 406 to the GPU 402”. Wang [0103] shows that task in at the head of ready queue is not ready, move the task to the tail of the queue in order to not block other tasks from progressing, such combination would allow tasks that are dispatched to a resource be placed in a back of the queue in order to not block other subsequent tasks on the queue from execution, and improves the efficiency of the system, and is therefore rejected under 35 USC 103. Mo teaches: enqueue the fiber in a check queue based on the fiber being enqueued in the ready queue and the one or more tasks of the fiber having been executed by the processing element array; and enqueue a dependent fiber that depends from the fiber in the ready queue based on the fiber being in the check queue. (Mo col 8, lines 29 – 37: “Initially, the scheduler assigns CPU 1 to run task T01 and CPU 2 to run task T02. During execution, task T01 generates child tasks T05 and T06. Because these are new tasks, the scheduler classifies them as short-running tasks and adds them to the front of the task queue. Because parent task T01 cannot continue until tasks T05 and T06 complete, the scheduler reassigns CPU 1 to run child task T05, which was at the front of the task queue. Task T06 continues to wait in the queue, while task T02 continues to run on CPU 2”.) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mo into that of Raman and Wang in order enqueue the fiber in a check queue based on the one or more tasks of the fiber having been executed by the processing element array; and enqueuing a dependent fiber that depends from the fiber in the ready queue based on the fiber being enqueued in the check queue. It is commonly known in the field that affinity-based scheduling would queue children/dependent tasks on the same core or processor as the parent in order to maximize data locality and cache hits, such combination merely claims the combination of known parts in the field to achieve predictable results of improve cache hits and improvement of overall efficiency of the scheduling system and is therefore rejected under 35 USC 103 . 07-21-aia AIA Claim (s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raman, Wang and Mo , and further in view of Reid (US 20110125986) . As per claim 7, the combination of Raman, Wang and Mo did not teach: The accelerator device of claim 4, wherein an additional fiber is enqueued ahead of the fiber in the sleep queue, and moving the fiber to the ready queue includes processing the completion signal of the task before a dispatched task of the additional fiber has been executed. However, Reid teaches: The accelerator device of claim 4, wherein an additional fiber is enqueued ahead of the fiber in the sleep queue, and moving the fiber to the ready queue includes processing the completion signal of the task before a dispatched task of the additional fiber has been executed. (Reid [0029]: “The provision of a pending task queue for a remote engine provides a significant degree of flexibility for the multi-processor system. In particular, the ability to have the next task which a remote engine must perform already queued up whilst a current task is being performed means that delays between the execution of one task and next may be kept to a minimum, since such a remote engine does not need to signal completion of a first task to the calling processor and wait for allocation of a second task before it can begin processing that second task.”) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Reid into that of Raman, Wang and Mo in order to have an additional fiber is enqueued ahead of the fiber in the sleep queue, and moving the fiber to the ready queue includes processing the completion signal of the task before a dispatched task of the additional fiber has been executed. Reid [0029] provided a motivation in support for this combination by teaching: “the ability to have the next task which a remote engine must perform already queued up whilst a current task is being performed means that delays between the execution of one task and next may be kept to a minimum, since such a remote engine does not need to signal completion of a first task to the calling processor and wait for allocation of a second task before it can begin processing that second task” . 07-21-aia AIA Claim (s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raman, Wang and Mo , and further in view of Steinberger et al (US 20230123634, hereinafter Steinberger) . As per claim 19, the combination of Raman, Wang and Mo did not teach: The system of claim 18, wherein the fiber includes a barrier representing the dependencies of the dependent fiber, and the command processor maintains a barrier table that includes a value representing a number of unresolved dependencies associated with the barrier. However, Reid teaches: The system of claim 18, wherein the fiber includes a barrier representing the dependencies of the dependent fiber, and the command processor maintains a barrier table that includes a value representing a number of unresolved dependencies associated with the barrier. (Steinberger [0074]: “A counter that specifies the number of tasks this task depends on, which may be atomically reduced by the scheduler to determine when all dependencies of a task are resolved and a task is ready for execution”.) It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Steinberger into that of Raman, Wang and Mo in order to have the fiber includes a barrier representing the dependencies of the dependent fiber, and the command processor maintains a barrier table that includes a value representing a number of unresolved dependencies associated with the barrier. Using a counter to list the number of dependency that a task has would allow the scheduler a clearer view at the dependency information and would improve the scheduling efficiency of the system by keeping an up-to-date dependency information on each task that is to be scheduled, such combination would enhance the overall appeals of all references and is therefore rejected under 35 USC 103. As per claim 20, the combination of Raman, Wang, Mo and Steinberger further teach: The system of claim 19, wherein to enqueue the fiber in the check queue, the operations instruct the command processor to: receive a completion signal indicating that the task has been executed by the processing element array; enqueue the completion signal in a signal queue; (Raman [0031]: “During execution of the common property task graph, task completion signals may be sent to notify dependent tasks outside of the common property task graph of the completion of the task upon which the dependent task depends. Whether a task completion signal is sent after the completion of a task but before the completion of the common property task graph may depend on the dependency and criticality of the dependent task outside of the common property task graph.”) decrement the value associated with the barrier in the barrier table based on the completion signal being in the signal queue; and enqueue the fiber in the check queue based on the value associated with the barrier being decremented to zero. (Steinberger [0103]: “After the execution of a task, the scheduler reads the number of dependencies of the finished tasks from the task descriptor as well as the location of the pointers to the depending task descriptors. Following the pointers, the dependency counter of each dependent task is atomically reduced by one. If a counter reaches zero, the task is ready to be executed and the scheduler places a pointer to the task descriptor into the appropriate global work queue. Thus, the task may be executed on the same or a different multi-processor. The work queues support concurrent enqueue and dequeue.”.) Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Driever (US 20180203724) teaches “analyzing, based on a list of resources maintained by a dispatcher processor, a task from a suspended queue to determine whether the task is waiting for a resource in order to execute; determining whether the task is waiting for a resource in order to execute; responsive to determining that the task is not waiting for the resource in order to execute, placing the task on a ready queue and adding an address of the resource to the list of resources maintained by the dispatcher processor; and dispatching the task to one of a plurality of execution processors for execution.”; Karypis et al (US 20150066157) teaches “Multiple parallel slave processes and a master process are assigned to a node executing an operating system such that the operating system maintains a ready queue comprising a list of one or more processes that are ready to be executed by at least one processing core. A parallel slave process takes an action that causes the operating system to keep the parallel slave process out of the ready queue. Based on receiving an indication that the parallel slave process is to be kept out of the ready queue, the master process sets the parallel slave process to a blocking state, selects a second parallel slave process that is in a runnable state but is currently kept from being in the ready queue, and takes an action that causes the operating system to add the parallel slave process that is in the runnable state to the ready queue.”; Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at 5712701014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHARLES M SWIFT/Primary Examiner, Art Unit 2196 Application/Control Number: 18/240,692 Page 2 Art Unit: 2196 Application/Control Number: 18/240,692 Page 3 Art Unit: 2196 Application/Control Number: 18/240,692 Page 4 Art Unit: 2196 Application/Control Number: 18/240,692 Page 5 Art Unit: 2196 Application/Control Number: 18/240,692 Page 6 Art Unit: 2196 Application/Control Number: 18/240,692 Page 7 Art Unit: 2196 Application/Control Number: 18/240,692 Page 8 Art Unit: 2196 Application/Control Number: 18/240,692 Page 9 Art Unit: 2196 Application/Control Number: 18/240,692 Page 10 Art Unit: 2196 Application/Control Number: 18/240,692 Page 11 Art Unit: 2196 Application/Control Number: 18/240,692 Page 12 Art Unit: 2196 Application/Control Number: 18/240,692 Page 13 Art Unit: 2196 Application/Control Number: 18/240,692 Page 14 Art Unit: 2196 Application/Control Number: 18/240,692 Page 15 Art Unit: 2196 Application/Control Number: 18/240,692 Page 16 Art Unit: 2196 Application/Control Number: 18/240,692 Page 17 Art Unit: 2196 Application/Control Number: 18/240,692 Page 18 Art Unit: 2196 Application/Control Number: 18/240,692 Page 19 Art Unit: 2196