DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 11 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Di Mola et al (US Patent No. 11,159,240 B1).
Regarding claim 1, Di Mola et al teaches a method, comprising:
determining an optical interconnect supports a defined optical mode (col. 2, lines 58-63; “The opto-ASIC co-packaged architecture chip 100 includes a plurality of co-packaged optical transceivers 110, such as transceiver 115 (e.g., an optical transceiver) that can receive electrical data for transmission and receive optical signal for processing from external devices (e.g., via an optical network).”; optical transceiver transmitting and receiving optical signals is considered to supports a defined optical mode);
decoding electrical signals from an electrical interconnect, the electrical signals to represent a number of bits from one or more messages (col. 5, lines 49-53; “The DSP processed signal is then converted from symbol format to binary format using the symbol-to-binary mapping circuits 385. Each of the binary signals then undergoes binary FEC decoding to correct errors.”);
converting the electrical signals to optical signals for the optical interconnect (col. 6, lines 3-9; “…the ASIC 402 is an example implementation of ASIC 105 or ASIC 215 that is connected to CPO module 416 (e.g., an optical transceiver, transceiver 115 in FIG. 1, PIC 220 in FIG. 2) via electrical paths (e.g., integrated electrical circuit paths 223, electrical connections through copper pillars 214 and organic substrate 260), over which data is transmitted in QAM signaling format.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”); and
mapping the decoded bits to one or more optical channels of the optical interconnect (col. 7, lines 29-31; …“the ASIC includes a symbol mapping circuit that maps binary data to symbols, such as a PAM or QAM symbols.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”).
Regarding claim 3, wherein the optical interconnect comprises fiber optic cables, vertical cavity surface emitting lasers (VCSELs), single-mode fiber, multi-mode fiber, waveguides, free-space optical interconnects, optical printed circuit boards (PCBs), parallel optics interconnects, coherent optical interconnects, or silicon photonics (col. 4, lines 36-40; “…the PIC 220 exchanges light with an external light source 225 via an optical fiber 221. The optical fiber 221 can couple with the PIC 220 using a prism, grating, or lens, according to some example embodiments.”; col. 6, lines 42-46; “In the illustrated example, a laser 422 (e.g., an external laser, a laser integrated into the CPO module 416) can generate the light for modulation and transmission, and additionally for demodulation by the receiver components in a coherent QAM configuration.”).
Regarding claim 11, an optical retimer, comprising:
an electronic integrated circuit (EIC) to process electrical signals for an electrical interconnect (col. 3, lines 27-36; “Each of the receiver portions include a number I/O ports (e.g., ADCs for the receivers, DACs for the transmitters) that depend on the number of co-packaged optical transceivers and the electrical interface types, according to some example embodiments. Further, each of the receiver and transmitter portions can include a number of data processing blocks (e.g., binary data processing 1 to binary data processing N) that can include binary data circuitry for binary data processing (e.g., error correction, symbol to binary converters, etc.).”);
a photonics integrate circuit (PIC) communicatively coupled to the EIC, the PIC to process optical signals for an optical interconnect (col. 4, lines 35-42; “…the PIC 220 exchanges light with an external light source 225 via an optical fiber 221. The optical fiber 221 can couple with the PIC 220 using a prism, grating, or lens, according to some example embodiments. The optical components of PIC 220 (e.g., optical modulators, optical switches) are controlled, at least in part, by control circuitry included in ASIC 215.”); and
logic circuitry communicatively coupled to the EIC and the PIC (col. 5, lines 45-55; “The ASIC 305 receives the electrical PAM data and converts it from analog to digital using a plurality of analog-to-digital (ADC) circuits 375, and the digital signal is then refined by DSP 380 (e.g., undergoes equalization) within the ASIC 305. The DSP processed signal is then converted from symbol format to binary format using the symbol-to-binary mapping circuits 385. Each of the binary signals then undergoes binary FEC decoding to correct errors. The error corrected data is then further processed using the application specific circuits of the ASIC 305 (e.g., switch ASIC) as discussed above in FIG. 1.”), the logic circuitry to:
determine the optical interconnect supports a defined optical mode (col. 2, lines 58-63; “The opto-ASIC co-packaged architecture chip 100 includes a plurality of co-packaged optical transceivers 110, such as transceiver 115 (e.g., an optical transceiver) that can receive electrical data for transmission and receive optical signal for processing from external devices (e.g., via an optical network).”; optical transceiver transmitting and receiving optical signals is considered to supports a defined optical mode);
decode electrical signals from the electrical interconnect, the electrical signals to represent a number of bits from one or more messages (col. 5, lines 49-53; “The DSP processed signal is then converted from symbol format to binary format using the symbol-to-binary mapping circuits 385. Each of the binary signals then undergoes binary FEC decoding to correct errors.”); and
instruct the EIC and the PIC to convert the electrical signals to optical signals for the optical interconnect (col. 6, lines 3-9; “…the ASIC 402 is an example implementation of ASIC 105 or ASIC 215 that is connected to CPO module 416 (e.g., an optical transceiver, transceiver 115 in FIG. 1, PIC 220 in FIG. 2) via electrical paths (e.g., integrated electrical circuit paths 223, electrical connections through copper pillars 214 and organic substrate 260), over which data is transmitted in QAM signaling format.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”), and
map the decoded bits to one or more optical channels of the optical interconnect (col. 7, lines 29-31; …“the ASIC includes a symbol mapping circuit that maps binary data to symbols, such as a PAM or QAM symbols.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”).
Regarding claim 19, Di Mola teaches a system, comprising:
a first system-on-a-chip (SoC) (col. 2, lines 42-48; “…co-packaged hybrid interface can be implemented to increase inter-chip data rates by integrating digital signal processing and error correction modules into the Ethernet ASIC and implementing spectral efficient transfers of data between the ASIC and the transceivers (e.g., PAM/QAM signaling between the ASIC and CPO modules).”);
a first electrical interconnect communicatively coupled to the first SoC (col. 3, lines 27-36; “Each of the receiver portions include a number I/O ports (e.g., ADCs for the receivers, DACs for the transmitters) that depend on the number of co-packaged optical transceivers and the electrical interface types, according to some example embodiments. Further, each of the receiver and transmitter portions can include a number of data processing blocks (e.g., binary data processing 1 to binary data processing N) that can include binary data circuitry for binary data processing (e.g., error correction, symbol to binary converters, etc.).”);
an optical interconnect (col. 4, lines 35-42; “…the PIC 220 exchanges light with an external light source 225 via an optical fiber 221. The optical fiber 221 can couple with the PIC 220 using a prism, grating, or lens, according to some example embodiments. The optical components of PIC 220 (e.g., optical modulators, optical switches) are controlled, at least in part, by control circuitry included in ASIC 215.”); and
a first optical retimer communicatively coupled to the first electrical interconnect and the optical interconnect (col. 5, lines 45-55; “The ASIC 305 receives the electrical PAM data and converts it from analog to digital using a plurality of analog-to-digital (ADC) circuits 375, and the digital signal is then refined by DSP 380 (e.g., undergoes equalization) within the ASIC 305. The DSP processed signal is then converted from symbol format to binary format using the symbol-to-binary mapping circuits 385. Each of the binary signals then undergoes binary FEC decoding to correct errors. The error corrected data is then further processed using the application specific circuits of the ASIC 305 (e.g., switch ASIC) as discussed above in FIG. 1.”; DSP and circuits associated with electrical interconnect and optical interconnect controlled by DSP are considered as optical retimer),
the optical retimer to determine the optical interconnect supports a defined optical mode (col. 2, lines 58-63; “The opto-ASIC co-packaged architecture chip 100 includes a plurality of co-packaged optical transceivers 110, such as transceiver 115 (e.g., an optical transceiver) that can receive electrical data for transmission and receive optical signal for processing from external devices (e.g., via an optical network).”; optical transceiver transmitting and receiving optical signals is considered to supports a defined optical mode),
decode electrical signals from the electrical interconnect, the electrical signals to represent a number of bits from one or more messages from the first SoC (col. 5, lines 49-53; “The DSP processed signal is then converted from symbol format to binary format using the symbol-to-binary mapping circuits 385. Each of the binary signals then undergoes binary FEC decoding to correct errors.”),
convert the electrical signals to optical signals for the optical interconnect (col. 6, lines 3-9; “…the ASIC 402 is an example implementation of ASIC 105 or ASIC 215 that is connected to CPO module 416 (e.g., an optical transceiver, transceiver 115 in FIG. 1, PIC 220 in FIG. 2) via electrical paths (e.g., integrated electrical circuit paths 223, electrical connections through copper pillars 214 and organic substrate 260), over which data is transmitted in QAM signaling format.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”), and
map the decoded bits from the first electrical interconnect to one or more optical channels of the optical interconnect (col. 7, lines 29-31; …“the ASIC includes a symbol mapping circuit that maps binary data to symbols, such as a PAM or QAM symbols.”; col. 6, lines 35-42; “The CPO module 416 implements one or more optical modulators to modulate a plurality of optical beams with PM-QAM optical signaling for transmission out of the opto-ASIC co-packaged architecture chip 100. For example, a modulator driver 418 for each data line uses the QAM electrical signaling to drive an optical modulator 420 (e.g., a dual polarization intensity modulator (DP-IM)) to generate modulated light for transmission.”).
Allowable Subject Matter
Claims 2, 4-10, 12-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Guduru (US Patent No. 9,882,635 B2) is cited to show rerouting bus data signals from faulty signal carriers to existing healthy signal carriers.
Baker et al (US Patent No. 9,697,883 B2) is cited to show optical interconnect in high-speed memory systems.
Wu et al (US Pub. No. 2018/0253398 A1) is cited to show high performance interconnect.
Das Sharma (US Pub. No. 2020/0145341 A1) is cited to show ordered sets for high-speed interconnects.
Meade et al (US Pub. No. 2021/0258078 A1) is cited to show remote memory architectures enabled by monolithic in-package optical I/O.
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DALZID E. SINGH
Primary Examiner
Art Unit 2635
/DALZID E SINGH/Primary Examiner, Art Unit 2635
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