Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant traversal of restriction requirement dated 12 September 2025 is considered and found persuasive. Claims 1-20 are being examined and the restriction requirement is withdrawn.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: FIG. 1B: 100B. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 20120008377 A1 (Chuang, et al., hereinafter Chuang).
Regarding claim 1, Chuang teaches a device (Chuang, FIG. 2-7) comprising: first transistors arranged as cross-coupled inverters coupled between a disconnect node and ground, (Chuang, FIG. 3, cross-coupled inverters 323, 325 are coupled between a disconnect node and a ground; although Chuang does not explicitly mention “disconnect node”, FIG. 3 provides for “power receiving terminals”/storage terminals” which can perform the function of a “disconnect node” as set forth in the instant specification) second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines; (Chuang, FIG. 3, transistors 311, 313 are arranged as passgates coupled between the cross-coupled inverters and bitlines) and third transistors coupled between a voltage supply and the disconnect node. (Chuang, FIG. 3, transistors 301, 303 are coupled between VDD and a disconnect node)
Regarding claim 2, Chuang teaches the device of claim 1, wherein: the first transistors and the second transistors are configured to operate as a cross-coupled bitcell latch, (Chuang, FIG. 3, also “latch circuit…”) and the third transistors are configured to provide a write assist feature (Chuang, [0024]: “As shown in FIG. 3, the Write-assist circuit 201 includes switch devices 301 and 303 (PMOSFETs in this embodiment). The switch device 301 includes a control terminal coupled to a Write world-line 307, a terminal coupled to a first predetermined voltage level VDD and another terminal to provide the power VVDD1 to the memory cell circuit 203. The switch device 303 has a control terminal coupled to a Write world-line 305, a terminal coupled to the first predetermined voltage level VDD and another terminal to provide the power VVDD2 to the memory cell circuit 203…”) that disconnects the cross-coupled bitcell latch from the voltage supply when deactivated. (FIG. 3, control terminal disconnects bitcell latch from voltage when not active)
Regarding claim 3, Chuang teaches the device of claim 2, further comprising: a wordline (Chuang, including “word-line 305…word-line 307…”) coupled to gates of the second transistors and the third transistors, (Chuang, FIG. 3) wherein the write assist feature operates as a built-in write assist feature when the wordline is asserted high so as to deactivate the third transistors. (Chuang, [0025]: “The switch device 311 has a bit transferring terminal B1 coupled to the data-storage terminal N1, a control terminal coupled to a first column-based Write word-line 305, and a bit transferring terminal B2. The switch device 313 has a bit transferring terminal B3 coupled to the data-storage terminal N2, a control terminal coupled to a column-based Write word-line 307, and a bit transferring terminal B4 coupled to the bit transferring terminal B2. The switch device 315 has a bit transferring terminal B5 coupled to the bit transferring terminal B4, a control terminal coupled to a row-based Read word-line 319, and a bit transferring terminal BE coupled to a bit-line 321. The switch device 317 has a control terminal coupled to the data-storage terminal N1, a terminal coupled to the bit transferring terminal B5 of the switch device 315, and another terminal coupled to a reference voltage level VVSS.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of US 6,061,267 A (Houston).
Regarding claim 4, Chuang teaches the device of claim 3, but does not appear to explicitly teach wherein: the first transistors, the second transistors and the third transistors are formed on a substrate, and the wordline comprises a buried wordline formed within the substrate.
Houston cures the deficiencies of Chuang. Houston teaches wherein: the first transistors, the second transistors and the third transistors are formed on a substrate, (Houston, col. 4, lines 1-9: “As known in the art, therefore, an insulator layer (typically silicon dioxide) is formed over the entire semiconductor substrate, and various devices are then formed over this insulator.”) and the wordline comprises a buried wordline formed within the substrate. (Houston, col. 16, lines 16-67: “Overlying buried oxide layer 54 is what is referred to generally herein as a buried conductor, where this buried conductor is electrically connected to wordline WL, thus, for purposes of later reference, the resulting Structure is referred to as a buried wordline, and a “B” is added to the subscript leaving a designation as WLo. In the preferred embodiment…”)
Both Chuang and Houston are directed to SRAM devices including multi-transistor structures. It would have been obvious to one of ordinary skill in the art to combine the multi-transistor memory structure of Chuang with the substrate and buried wordline formation of Houston. One of ordinary skill in the art would have motivation to combine in order to improve functionality of the memory device.
Regarding claim 7, Chuang teaches the device of claim 1, but does not appear to teach wherein: the first transistors, the second transistors and the third transistors are formed on a substrate, and the bitlines comprises buried bitlines formed within the substrate. Houston cures the deficiencies of Chuang. Houston teaches wherein the first transistors, the second transistors and the third transistors are formed on a substrate, (Houston, col. 4, lines 1-9: “As known in the art, therefore, an insulator layer (typically silicon dioxide) is formed over the entire semiconductor substrate, and various devices are then formed over this insulator.”) and the bitlines comprises buried bitlines formed within the substrate. (Houston, col. 16, lines 16-67: “Overlying buried oxide layer 54 is what is referred to generally herein as a buried conductor, where this buried conductor is electrically connected to wordline WL, thus, for purposes of later reference, the resulting Structure is referred to as a buried wordline, and a “B” is added to the subscript leaving a designation as WLo. In the preferred embodiment…”)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of Houston in view of US 20220037497 A1 (Chung, et al., hereinafter Chung).
Regarding claim 8, Chuang teaches the device of claim 1, but does not appear to teach wherein: the first transistors, the second transistors and the third transistors are formed on a substrate, the voltage supply is coupled to a first buried power rail formed within the substrate, and the ground is coupled to a second buried power rail formed within the substrate.
Houston teaches wherein: the first transistors, the second transistors and the third transistors are formed on a substrate. (Houston, col. 4, lines 1-9: “As known in the art, therefore, an insulator layer (typically silicon dioxide) is formed over the entire semiconductor substrate, and various devices are then formed over this insulator.”) However, Houston does not appear to teach wherein the voltage supply is coupled to a first buried power rail formed within the substrate, and the ground is coupled to a second buried power rail formed within the substrate.
Chung cures the deficiencies of Chuang/Houston. Chung teaches wherein the voltage supply is coupled to a first buried power rail formed within the substrate, (Chung, [0049]: “the dielectric isolation layer 242, the first ILD layer 232, the first CESL 230, and the isolation feature 214 and exposes the second buried power rail 211-2.”) and the ground is coupled to a second buried power rail formed within the substrate. (Chung, FIG. 2A-4C; Chung, [0026]: “The workpiece 200 may include a substrate portion 202 and a stack portion 204 disposed above the substrate portion 202. The substrate portion 202 may also be referred to as the substrate 202. Although not explicitly shown in the figures, the substrate 202 may include an n-type well region and a p-type well region for fabrication of transistors of different conductivity types.”)
Both Chuang/Houston and Chung are directed to SRAM devices including multi-transistor structures. It would have been obvious to one of ordinary skill in the art to combine the multi-transistor memory structure including a substrate and buried wordline formation of Chuang/Houston with the buried power rails formed within the substate of Chung. One of ordinary skill in the art would have motivation to combine in order to improve functionality of the memory device.
Allowable Subject Matter
Claims 5-6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, Chuang teaches the device of claim 2, but does not appear to teach further comprising: a wordline coupled to gates of the second transistors; and a control-line coupled to gates of the third transistors, wherein the write assist feature operates as a built-in write assist feature when the control-line is asserted high so as to deactivate the third transistors. In particular, “wherein the write assist feature operates as a built-in write assist feature when the control-line is asserted high so as to deactivate the third transistors” is not taught by the prior art in the context of the claim.
Claim 6 is dependent upon claim 5.
Regarding claim 9, the prior art of record does not explicitly teach the device of claim 1, wherein: the first transistors, the second transistors and the third transistors comprise P-type transistors and N-type transistors, and the first transistors, the second transistors and the third transistors are formed with a P-type and N-type complementary field effect transistor (PN CFET) technology such that the P-type transistors are physically disposed on the N-type transistors or such that the N-type transistors are physically disposed on the P-type transistors.
Claims 10-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 10, the prior art of record does not explicitly teach a device comprising: a plurality of transistors formed with a complementary field effect transistor (CFET) technology such that P-type transistors are physically disposed on N-type transistors or such that the N-type transistors are physically disposed on the P-type transistors, wherein the transistors include first transistors arranged as cross-coupled inverters coupled between a voltage supply and ground; wherein the transistors include second transistors arranged as passgates coupled between the cross-coupled inverters and bitlines, and wherein the transistors include third transistors coupled in series between the voltage supply and a read bitline.
Regarding claim 16, the prior art of record does not explicitly teach a device comprising: a plurality of transistors formed with a complementary field effect transistor (CFET) technology such that P-type transistors are physically disposed on N-type transistors or such that the N-type transistors are physically disposed on the P-type transistors, wherein the transistors include first transistors arranged as cross-coupled inverters coupled between a voltage supply and ground; wherein the transistors include second transistors arranged as first passgates coupled between the cross-coupled inverters and first bitlines; and wherein the transistors include third transistors arranged as second passgates coupled between the cross-coupled inverters and second bitlines.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J KING whose telephone number is (703)756-1232. The examiner can normally be reached M-F 9am-5pm.
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/DANIEL JOHN KING/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827