DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s correction filed 01/02/2026 with respect to claim rejection under 112(b) for claim(s) 3 and 20 made on 10/01/2025 has been considered and the claim rejection under 112(b) to the claims is withdrawn.
Applicant's arguments filed 01/02/2026 with respect to claim(s) 1, 10, and 19 have been considered but are moot in view of the new ground(s) of rejection under 103 based on Hooper et. al. (US 20170222790 A1) in view of McLaughlin et al. (US 2002/0190880 A1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hooper et. al. (US 2017/0222790 A1) in view of McLaughlin et al. (US A1).
Regarding claims 1, 10, and 19, Hooper discloses A method for mixing multiple audio channels, comprising and A device for mixing multiple audio channels, comprising: one or more memories; and one or more processors (¶[0209]: central processor (e.g., at the host 110)), coupled to the one or more memories (¶[0214]: the system 100 may be used to connect any suitable electronic devices, such as memory, processors) and A non-transitory computer-readable medium storing a set of instructions for wireless communication, the set of instructions comprising: one or more instructions that, when executed by one or more processors of a device (¶[0317]: one or more non-transitory computer readable media having instructions thereon that, in response to execution by one or more processing devices of a system):
connecting an audio processor (¶[0209]: central processor (e.g., at the host 110)) to one or more time division multiplexing (TDM) data chains (¶[0032]: time division multiplexed (TDM) communications over a two-wire bus (e.g., a twisted wire pair). In these systems, bi-directional synchronous data (e.g., digital audio), clock, and synchronization signals may be provided by the two-wire bus, supporting direct point-to-point connections between nodes on the bus and allowing multiple, daisy chained nodes at different locations to contribute or consume TDM channel content) that each includes a plurality of digital sample rate converters (¶[0199]: the node transceiver 120 may also provide a sample rate converter (e.g., built-in) to process the received radio signals. ¶[0058]: I2S/TDM/PDM transceiver 127 may be in communication with the bus protocol circuitry 126 and pins for communication with the external device 155. Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0] … any desired number of receive and/or transmit pins may be used. In ¶[0058], TDM transceiver supports multiple TX and RX channels DTX and DRX and arbitrary number of channels/pins. ¶[0119] and ¶[0058] taken together, each channel requires a plurality of sample rate converter for TDM alignment and that sample rate conversion is necessary per channel);
providing, to the plurality of digital sample rate converters in each TDM data chain (¶[0199]: the node transceiver 120 may also provide a sample rate converter (e.g., built-in) to process the received radio signals ... before transmitting the received radio signals over the bus 106 (e.g., at the audio sampling frequency corresponding to the superframe rate). In ¶[0199], sample rate converters directly to sample rate clocks), a set of TDM clocks that includes a sample rate clock input and a bit clock input (Fig. 2 BCLK as bit clock input, SYNC as sample rate clock input. ¶[0058]: The I2S/TDM/PDM transceiver 127 may be in communication with the bus protocol circuitry 126 and pins for communication with the external device 155. Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0], are illustrated in FIG. 2. In ¶[0058], it describes bit clocks and sampling-related clocks to nodes. ¶[0067]: PLL 128 may provide the clock that a node uses to time communications over the bus 106 ... the PLL 128 may operate at a multiple of the audio sampling frequency. In ¶[0067], PLL-derived clocks at multiples of the audio sample frequency);
connecting the plurality of digital sample rate converters in each TDM data chain to a corresponding plurality of audio ports that each corresponds to a stereo channel (¶[0046]: a slave node 104 may be configured to read data from and/or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, and/or I2C protocols. ¶[0058]: I2S/TDM” may refer to an extension of the I2S stereo (2-channel) content to multiple channels using TDM. In ¶[0046] and ¶[0058], a TDM chain is interfaced with a stereo channel);
receiving, at the plurality of digital sample rate converters in each TDM data chain, a plurality of digital audio inputs via the plurality of audio ports (¶[0046]: a slave node 104 may be configured to read data from and/or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, and/or I2C protocols. ¶[0159]: Upon actuation of the conferencing user interface element by a user, the slave node 104 may provide data from the microphone upstream and/or downstream on the bus 104 for receipt and/or playback. In ¶[0046] and ¶[0159], taken together, slave nodes receive audio inputs from peripherals through I2S/TMD ports, which are connected to the converters in each TDM chain);
receiving, at one or more TDM inputs associated with the audio processor, a TDM audio stream from each of the one or more TDM data chains, (¶[0067]: the PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe). In ¶[0067], shows the use of sample rate clock and bit clock to time TDM communications. ¶[0101]: upstream and downstream data may be transmitted along the bus 106 in TDM data slots within a superframe 190. In ¶[0101], shows that system forms TDM audio stream composed of multiple channels. Taken together, the audio processor receives TDM superframes carrying multiplexed/mixed audio channels); and
outputting, by the audio processor, the TDM audio stream (¶[0199]: the node transceiver 120 may also provide a sample rate converter … before transmitting the received radio signals over the bus 106. ¶[0203]: the system 100 may be used to interconnect audio visual equipment … Data from these pieces of equipment may be provided to other equipment along the bus 106 by the node transceivers 120. In ¶[0199] and ¶[0203], audio processor outputs the processed TDM audio stream onto the bus for downstream delivery).
Hooper does not disclose, but McLaughlin discloses wherein each of the plurality of digital sample rate converters converts a respective one of the plurality of digital audio inputs to a selected TDM sample rate and combines the converted respective one of the plurality of digital audio inputs into the TDM audio stream based on the sample rate clock input and the bit clock input ([0043]: The sample rate conversion system includes a master sample rate converter 250 and slave sample rate converters 260, 262, . . . . 270. Each of sample rate converters 250, 260, 262 . . . 270 receives an input sample clock LRCLK I, an input bit clock SCLK I, an output sample clock LRCLK O and an output bit clock SCLK O. In addition, each of the sample rate converters receives a serial data input SDATA I. The serial input data lines are connected in parallel, and the serial output data lines are connected in a daisy chain configuration. Thus, the serial data output SDATA O of sample rate converter 250 is connected to a serial data input TDM IN of slave sample rate converter 260, the serial data output SDATA O of sample rate converter 260 is connected to a serial data input TDM IN of sample rate converter 262, etc. The serial data output SDATA O of sample rate converter 270, the last sample rate converter in the chain, is the output of the sample rate conversion system. In the daisy chain configuration, serial data received by each sample rate converter is added onto an output data frame in a time multiplexed fashion. [0045]: The data format utilized for transmission of output data samples and sample rate ratio is described with reference to FIGS. 9, 10, 11A and 11B. In the embodiment of FIGS. 9, 10, 11A and 11B, the data is organized in 64-bit frames which contain left and right samples of stereo audio data. [0026]: an audio sample rate converter which converts time multiplexed left and right channels of a stereo audio system).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the sample rate converter, as taught by Hooper, to receive an input sample clock, an input bit clock, an output sample clock, an output bit clock, and serial data input, and connect the serial input data lines in parallel and the serial output data lines in a daisy chain configuration, so that the serial data output of a sample rate converter becomes the serial data input TDM IN of the next sample rate converter, and serial data received by each sample rate converter is added onto an output data frame in a time multiplexed fashion, as taught by McLaughlin.
Doing so allows all the sample rate converters in the sample rate conversion system to utilize the sample rate ratio measured by master sample rate converter 250, and the group delays of the time multiplexed data outputs are matched (McLaughlin: [0044]).
Regarding claims 2 and 11, Hooper in view of McLaughlin discloses wherein the plurality of audio ports are associated with an inter-integrated circuit sound (I2S) interface (¶[0041]: The host 110 may communicate with the master node 102 via an I2S/Time Division Multiplex (TDM) bus and/or an Inter-Integrated Circuit (I2C) bus).
Regarding claims 3, 12, and 20, Hooper in view of McLaughlin discloses wherein the sample rate clock input and the bit clock input are shared among the plurality of digital sample rate converters in each TDM data chain (¶[0067]: the PLL 128 may provide the clock that a node uses to time communications over the bus 106 … the PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe). In ¶[0067], a single PLL derived clock source provides timing for TDM communications).
Regarding claims 4 and 13, Hooper in view of McLaughlin discloses wherein a frequency of the bit clock input (¶[0058]: Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0], are illustrated in FIG. 2; the BCLK pin may be used for an I2S bit clock, the SYNC pin may be used for an I2S frame synchronization signal) associated with a respective TDM data chain is based on a number of multiplexed audio channels associated with the TDM data chain (¶[0058]: I2S/TDM” may refer to an extension of the I2S stereo (2-channel) content to multiple channels using TDM.), a frequency of the sample rate clock input associated with the TDM data chain (¶[0067]: the PLL 128 may provide the clock that a node uses to time communications over the bus 106 … the PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe)), and a number of bits per audio channel associated with the TDM data chain (¶[0058]: Six pins, BCLK, SYNC, DTX[1:0], and DRX[1:0], are illustrated in FIG. 2; the BCLK pin may be used for an I2S bit clock. ¶[0059]: Registers in the node transceiver 120 may determine which and how many I2S/TDM channels are being transmitted as data slots over the bus 106. A TDM mode (TDM MODE) register in the node transceiver 120 may store a value of how many TDM channels fit between consecutive SYNC pulses on a TDM transmit or receive pin. Together with knowledge of the channel size, the node transceiver 120 may automatically set the BCLK rate to match the amount of bits within the sampling time (e.g., 48 kHz). Taking ¶[0058] and ¶[0059] together, teaches that BCLK bit clock input is used in I2S/TDM and its rate is determined from channel size (bits per channel) so the bit clock frequency is based on the number of bits per audio channel).
Regarding claims 5 and 14, Hooper in view of McLaughlin discloses wherein the one or more TDM data chains include a first TDM data chain that generates a first TDM audio stream associated with a first TDM sample rate (¶[0067]: the PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024-bit clocks in each superframe). In ¶[0067], each TDM data chain can be clocked at a specific sample frequency, which produces a TDM audio stream at a defined first TDM sample rate) and a second TDM data chain that generates a second TDM audio stream associated with a second TDM sample rate (¶[0147]: the data slots on the bus 106 may be configured to be run at a full, continuous audio rate or to be run at a reduced rate by time-dividing bus data slots for a particular slave node 104 into multiple I2S/TDM channels. In ¶[0147], another (i.e. second) different audio rate (full vs reduced) can operate in the data bus 103).
Regarding claims 6 and 15, Hooper in view of McLaughlin discloses further comprising:
operating one or more digital sample rate converters, of the plurality of digital sample rate converters in a TDM data chain (¶[0059]: I2S/TDM/PDM transceiver 127 may provide an I2S slave (in regards to BCLK and SYNC) that can receive data from the host 110 and send data to the host 110 synchronously with an I2S interface clock of the host 110 … the I2S/TDM/PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with the peripheral device 108. In ¶[0059], I2S/TDM transceiver performs the role of digital sample rate converters within a TDM chain, which are operated in either slave or master mode), in a master mode based on an absence of a signal associated with a clock input for a corresponding one or more audio ports of the plurality of audio ports (¶[0059]: I2S/TDM/PDM transceiver 127 may provide an I2S slave (in regards to BCLK and SYNC) that can receive data from the host 110 and send data to the host 110 synchronously with an I2S interface clock of the host 110 … When the node transceiver 120 is included in a slave node 104, the external device 155 may include one or more peripheral devices 108, and the I2S/TDM/PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with the peripheral device 108. In ¶[0059], transceiver acts as a slave when an external I2S clock is supplied by the host, when that is not provided, the transceiver operated in master mode).
Regarding claims 7 and 16, Hooper in view of McLaughlin discloses further comprising:
providing, by the audio processor, a reference clock signal to a clock buffer (¶[0059]: an I2S frame synchronization signal may be received at the SYNC pin as an input from the host 110, and the PLL 128 may use that signal to generate clocks. In ¶[0059], shows processor associated (host 110) generation of reference clock signals to a clock buffer (PLL 128)); and
distributing, by the clock buffer, the reference clock signal to the plurality of digital sample rate converters in each TDM data chain (¶[0059]: PLL 128 may use that signal to generate clocks … Registers in the node transceiver 120 may determine which and how many I2S/TDM channels are being transmitted as data slots over the bus 106. A TDM mode (TDM MODE) register … may automatically set the BCLK rate to match the amount of bits within the sampling time. In ¶[0059], once the PLL generates the reference clock, the signal is distributed internally (via registers and mode control) to the converters in the downstream TDM chain. Taken with ¶[0067], because the PLL generates reference clock that drives all timing communication across the entire bus, it inherently feeds (distributes to) all active TDM chains).
Regarding claims 8 and 17, Hooper in view of McLaughlin discloses further comprising:
providing, by a clock source, a reference clock signal to a clock buffer (¶[0059]: an I2S frame synchronization signal may be received at the SYNC pin as an input from the host 110, and the PLL 128 may use that signal to generate clocks. In ¶[0059], shows processor associated (host 110) generation of reference clock signals to a clock buffer (PLL 128)); and
providing, by the clock buffer, the reference clock signal to the audio processor and to the plurality of digital sample rate converters in each TDM data chain (¶[0059]: the I2S/TDM/PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with the peripheral device 108 .... Registers in the node transceiver 120 may determine which and how many I2S/TDM channels are being transmitted as data slots over the bus 106 … the node transceiver 120 may automatically set the BCLK rate to match the amount of bits within the sampling time. In ¶[0059], PLL provides an I2S clock master and is supplied to all communications, which includes the converters in each TDM chain).
Regarding claims 9 and 18, Hooper in view of McLaughlin discloses further comprising:
receiving, from the audio processor at one or more port expanders connected to the plurality of digital sample rate converters in each TDM data chain (¶[0041]: host 110 may communicate with the master node 102 via an I2S/Time Division Multiplex (TDM) bus and/or an Inter-Integrated Circuit (I2C) bus … allowing the host 110 direct access to registers and status information for the one or more slave nodes 104, as well as enabling I2C-to-I2C communication over distance to allow the host 110 to control the peripherals 108. In ¶[0041], the host (audio processor) sends communication via I2C protocols in turn to manage downstream converters), configuration control information associated with each digital sample rate converter (¶[0046]: a slave node 104 may be configured to read data from and/or write data to the associated peripheral device 108 using I2S, pulse density modulation (PDM), TDM, and/or I2C protocols. In ¶[0046], each slave node communicates with peripheral devices (e.g., converters) using I2S; and combined with ¶[0041], the host provides register-level access and control information to the slave node, the system collectively shows that configuration information is received at intermediary port structures (nodes)); and
configuring each digital sample rate converter independently using the configuration control information received from the audio processor (¶[0041]: allowing the host 110 direct access to registers and status information for the one or more slave nodes 104. ¶[0046]: ¶[0046]: a slave node 104 may be configured to read data from and/or write data to the associated peripheral device 108. In ¶[0041] and ¶[0046], the configuration is done at the level of each peripheral/converter via register access from the audio processor, thus supporting the independent configuration of each converter).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THE HY NGUYEN whose telephone number is (571)270-3813. The examiner can normally be reached on Mo-Fr: 8am-4pm.
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/THE HY NGUYEN/Primary Examiner, Art Unit 2478
TheHy.Nguyen@USPTO.gov
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