Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 04/13/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Applicant’s amendment to the specification corrects the typographical issues mentioned in the prior office action. The objection to the specification is withdrawn.
Applicant’s amendment to the abstract removes the title information and the purported merits of the invention. The objection to the abstract is withdrawn.
Applicant’s amendment to claim 19 and arguments regarding the drawing objection is acknowledged. The drawing objection is withdrawn in view that the term “share” a common active region appears to mean that the two or more transistors are formed on the same layer as shown in figure 4 and 7F where transistor 120 includes semiconductor layer 124 and transistor 130 including semiconductor layer 134 are formed on the same layer 115b. The term active region is being interpreted as meaning a source region, a drain region, and a channel region as described in paragraph [00206] of the immediate invention. Figure 4 and 7F appears to show the source regions 124s and 134s, the drain regions 124d and 134d, and the channel regions 124c and 134c are on the same layer 115b.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the second gate electrode of the second thin film transistor is above each of the first gate electrodes such that the predetermined distance is covered by the second gate electrode must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Figure 4 and figure 7F shows the first electrodes of the first thin film transistor 121a and also show the gate electrode of the second thin film transistor 131. Neither figure 4 nor figure 7F show the second gate electrode 131 covering the predetermined distance between the first gate electrodes 121a. The first thin film transistor 120 and the second thin film transistor 130 are shown to not overlap and the second gate electrode 131 does not cover the space between the first gate electrodes 121a. Paragraph [00207] discusses the second gate electrode of the second thin film transistor being disposed above each of the first gate electrodes to cover the predetermined distance, but does not state where in the drawings this feature is shown.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 - 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140353605 A1 hereinafter Kim.
For claim 1, Kim teaches a thin film transistor (fig. 1) comprising a semiconductor layer (fig. 1 numeral 130); a first insulating layer on the semiconductor layer (fig. 1 numeral 141); a gate electrode on the first insulating layer (fig. 1 numeral 125); a second insulating layer on the gate electrode (fig. 1 numeral 142); a source electrode (fig. 1 numeral 176) and a drain electrode on the second insulating layer (fig. 1 numeral 177), the source electrode and the drain electrode respectively electrically connected to a source region (fig. 1 numeral 131) and a drain region (fig. 1 numeral 132) of the semiconductor layer; and a second gate electrode above the first gate electrode (fig. 1 numeral 126), wherein a channel region is between the source region and the drain region and the channel region extends continuously and overlaps the first gate electrode (fig. 1 numeral 133). Kim also teaches embodiments wherein the first gate electrode is two first gate electrodes separated from each other by a predetermined distance (fig. 4 numeral 125a and 125b) and the channel region overlaps the two first gate electrodes and that the overlap includes space between the two first gate electrodes (fig. 4 numeral 125a and 125b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the embodiments in Kim would include embodiments wherein there are two or more first gate electrodes on the first insulating layer separated by a predetermined distance and wherein the channel region extends continuously and includes a portion of the predetermined distance between the two or more first gate electrodes, as Kim teaches that the channel region can be formed in one continuous layer overlapping the gate electrodes (fig. 1 numeral 133; Par. [0060]) and that the first gate electrode can be split into two electrodes (fig. 4 numeral 125a and 125b; Par. [0086]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the two embodiments in Kim in order to fully insulate the first gate electrodes (Par. [0091]), to generate a strong electric field between the electrodes and the channel region (Par. [0093]), and to reduce electrical current leakage (Par. [0059]; Par. [0029]). Further, Kim links the two embodiments of figure 1 and figure 4 as substantially similar except for the change in first gate electrode structure (Par. [0086]) and Kim also teaches the embodiments may be modified in shape and sizes and the number of elements present (Par. [0045 – 0046]; Par. [0113]). Modifying figure 1 with the two first gate electrodes of figure 4 appears to be included as a change in the shape of the elements and a change in the number of elements.
For claim 2, Kim teaches all of claim 1. Kim also teaches the second gate electrode is on the second insulating layer between the source electrode and the drain electrode (fig. 1 shows second gate electrode 126 is on the second insulating layer 142 that is between the source electrode 176 and drain electrode 177).
For claim 3, Kim teaches all of claim 1. Kim also teaches the second gate electrode is above the two or more first gate electrodes (fig. 4 numeral 126) and the second electrode covers the predetermined distance between the two first gate electrodes (fig. 4 shows second gate electrode 126 covering the distance between the two first gate electrodes 125a and 125b).
For claim 4, Kim teaches all of claim 1. Kim also teaches the semiconductor layer outside the two or more first gate electrodes constitutes the source and the drain region (fig. 4 numeral 131 and 132; fig. 1 numeral 131 and 132) and the semiconductor layer below the two or more first gate electrodes and the second gate electrode constitutes the channel region (fig. 4 numeral 133; fig. 1 numeral 133).
For claim 5, Kim teaches all of claim 4. Kim also teaches an outer edge of the one first gate electrode from the two or more first gate electrodes and a boundary between the source region and the channel region are self-aligned (fig. 4 shows source region 131 and channel region 133 having a boundary 134 and the boundary is aligned with the outer edge of the first gate electrode 125a) and an outer edge of another first gate electrode from the two or more first gate electrodes and a boundary between the drain region and the channel region are self-aligned (fig. 4 shows drain region 132 and channel region 133 having a boundary 135 and the boundary is aligned with the outer edge of the first gate electrode 125b).
For claim 6, Kim teaches all of claim 1. Kim also teaches the second gate electrode overlaps at least a portion of the two or more first gate electrodes (fig. 4 shows second gate electrode 126 overlapping the first gate electrodes 125a and 125b).
For claim 7, Kim teaches all of claim 1. Kim also teaches the second gate electrode is electrically connected to the two or more first gate electrodes through a contact hole (fig. 4 numeral 43; Par. [0062]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20140353605 A1 hereinafter Kim in further view of US 20220231170 A1 hereinafter Fan.
For claim 8, Kim teaches all of claim 1. Kim is silent regarding the second insulating layer having a thickness that is greater than a thickness of the first insulating layer.
Fan teaches a thin film transistor (Fan, fig. 4) with a gate electrode (fig. 4 numeral G12) covered by a first and second insulating layers (fig. 4 numerals 120 and 130). The second insulating layer (130) has a greater thickness than the first insulating layer (120) (fig. 4; Par. [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the insulating layer thicknesses in Fan with the insulating layers in Kim in order to control the subthreshold swing of the thin film transistors (Fan, Par. [0043]) in order to improve the switching speed of the device (Par. [0043]).
Allowable Subject Matter
Claims 19 – 21 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 19’s “A driving transistor, comprising: two or more first thin film transistors and a second thin film transistor that are in series with each other… the two or more first thin film transistors and the second thin film transistor share a common active region… and wherein a channel region between a source region and a drain region extends continuously and includes a portion corresponding to a predetermined distance between the first gate electrodes of the two or more first thin film transistors”. Kim does not appear to teach the channel region being continuous in multiple thin film transistors and wherein those multiple thin film transistors share a common active region.
Claims 20 – 21 are allowable primarily as depending on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”
Response to Arguments
Applicant's arguments filed 04/03/2026 in regard to claim 1 have been fully considered but they are not persuasive.
Applicant’s arguments states that the channel region in Kim is not continuous and is separated by a weak electric field region. However, embodiments in Kim appear to teach a continuous channel region overlapping the first gate electrode and includes embodiments wherein the channel region overlaps at least partially with the distance between multiple first gate electrodes. Kim appears to teach both the continuous channel region and multiple first gate electrodes and provides motivation to include each feature (see rejection above). As all the limitation of claims 1 – 7 appear to be taught by Kim, the rejection of claims 1 – 7 is maintained.
Applicant’s arguments, see pages 11 - 12 of applicant’s remarks, filed 04/03/2026, with respect to claim 19 have been fully considered and are persuasive. The rejection of claims 19 - 21 of 01/27/2026 has been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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