Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/24/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 06/26/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Applicant’s arguments regarding the drawings objections are persuasive and clarifies the location of the second gate electrode in regard to the second thin film transistor and the first gate electrodes. The objection to the drawings is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, and 6 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20060030089 A1 hereinafter Chung.
For claim 1, Chung teaches “A thin film transistor (fig. 3D), comprising: a semiconductor layer (fig. 3D numeral 104); a first insulating layer on the semiconductor layer (fig. 3D numeral 106); two or more first gate electrodes on the first insulating layer and separated from each other by a predetermined distance (fig. 3D numeral 108a and 108b); a second insulating layer on the two or more first gate electrodes (fig. 3D numeral 112); a source electrode and a drain electrode on the second insulating layer (fig. 3D numeral 114 and 116), the source electrode and the drain electrode respectively connected to a source region and a drain region of the semiconductor layer (fig. 3D numeral C2; Par. [0045]); and a second gate electrode above the two or more first gate electrodes (fig. 3D numeral 118), wherein a channel region is between the source region and the drain region in a plan view of the thin film transistor (fig. 3D numeral 104; Par. [0046]; fig. 4 numeral 104 shows the channel region between the source and drain regions located under drain electrode and source electrode 116 and 114), the channel region extending continuously, and wherein the channel region includes a portion of the semiconductor layer continuously overlapping the second gate electrode and covering an entirety of the predetermined distance between the two or more first gate electrodes in the plan view (fig. 4 shows channel region 104 extending entirely between the two or more first gate electrodes 108a and 108b in a plan view).” Chung teaches the channel length L can be variable and is between the two first gate electrodes (Par. [0046]). The channel length can be the whole length of layer 104 or half the length, or a fourth of the layer 104 (Par. [0046]) or some other predetermined length as desired.
For claim 2, Chung teaches “The thin film transistor of claim 1, wherein the second gate electrode is on the second insulating layer between the source electrode and the drain electrode (fig. 3D numeral 118).”
For claim 3, Chung teaches “The thin film transistor of claim 1, wherein the second gate electrode is above the two or more first gate electrodes such that the predetermined distance is covered by the second gate electrode (fig. 3D numeral 118).”
For claim 4, Chung teaches “The thin film transistor of claim 1, wherein the semiconductor layer outside the two or more first gate electrodes constitutes the source region and the drain region (fig. 3D numeral C2), and the semiconductor layer below the two or more first gate electrodes and the second gate electrode constitutes the channel region (fig. 3D numeral 104; Par. [0046]).”
For claim 6, Chung teaches “The thin film transistor of claim 1, wherein the second gate electrode overlaps at least a portion of the two or more first gate electrodes (fig. 3D numeral 118).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20060030089 A1 hereinafter Chung in further view of US 20140353605 A1 hereinafter Kim.
For claim 5, Chung teaches all of claim 4. Chung is silent regarding the first gate electrodes and the boundary of the source region and the channel region being self-aligned and an outer edge of another first gate electrode from the two or more first gate electrodes and a boundary between the drain region and the channel region are self-aligned.
Kim teaches a thin film transistor (Kim, fig. 5) including a first gate electrodes (fig. 5 numeral 125a and 125b), a second gate electrode (fig. 5 numeral 126), a source region and a drain region (fig. 5 numeral 131 and 132) connected to a channel region (fig. 5 numeral 130). Kim also teaches an outer edge of the one first gate electrode from the two or more first gate electrodes and a boundary between the source region and the channel region are self-aligned (fig. 4 shows source region 131 and channel region 133 having a boundary 134 and the boundary is aligned with the outer edge of the first gate electrode 125a) and an outer edge of another first gate electrode from the two or more first gate electrodes and a boundary between the drain region and the channel region are self-aligned (fig. 4 shows drain region 132 and channel region 133 having a boundary 135 and the boundary is aligned with the outer edge of the first gate electrode 125b).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the self-alignment in Kim with the structure of Chung in order to minimize current leakage and control the breakdown voltage of the device (Kim, Par. [0051]).
For claim 7, Chung teaches all of claim 1. Chung is silent regarding the second gate electrode being electrically connected to the two or more first gate electrodes through a contact hole.
Kim teaches a thin film transistor (Kim, fig. 4) including a second gate electrode being electrically connected to two or more first gate electrodes through a contact hole (fig. 4 numeral 43; Par. [0062]).
It would have been obvious to one of ordinary skill in the art to combine the electrical connection in Kim with the electrodes in Chung in order to control current leakage and voltage breakdown while improving the capacitance characteristics of the device (Kim, Par. [0050 – 0051]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20060030089 A1 hereinafter Chung in further view of US 20220231170 A1 hereinafter Fan.
For claim 8, Chung teaches all of claim 1. Chung is silent regarding the second insulating layer having a greater thickness than the first insulating layer.
Fan teaches a thin film transistor (Fan, fig. 4) with a gate electrode (fig. 4 numeral G12) covered by first and second insulating layers (fig. 4 numerals 120 and 130). The second insulating layer (130) has a greater thickness than the first insulating layer (120) (fig. 4; Par. [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the insulating layer thicknesses in Fan with the insulating layers in Chung in order to control the subthreshold swing of the thin film transistors (Fan, Par. [0043]) in order to improve the switching speed of the device (Par. [0043]).
Allowable Subject Matter
Claims 19 – 21 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 19’s “A driving transistor, comprising: two or more first thin film transistors and a second thin film transistor that are in series with each other… the two or more first thin film transistors and the second thin film transistor share a common active region… and wherein a channel region between a source region and a drain region extends continuously and includes a portion corresponding to a predetermined distance between the first gate electrodes of the two or more first thin film transistors”. Chung, Kim, and Fan do not appear to teach the channel region being continuous in multiple thin film transistors and wherein those multiple thin film transistors share a common active region.
Claims 20 – 21 are allowable primarily as depending on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.T.N./ Examiner, Art Unit 2815
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
Prosecution Insights