Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The previous 112 claim rejection for claims 3-9 is withdrawn based on the amendments filed on 9/15/2025.
Response to Arguments
Applicant’s arguments, see Pg. 10, Para. 5, filed 2/2/2026, with respect to the rejection(s) of claim(s) 17-18 and 20 under 35 USC 102 & 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Senda, US20150236686 (hereinafter referred to as Senda). Senda teaches of acquiring overcurrent detection results while the power switch is in a partially ON state.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Senda, US20150236686 (hereinafter referred to as Senda).
In regards to claim 17, Senda teaches a method, comprising: receiving a control signal (signal Sa; [Fig. 2]); providing a first switch control signal (signal VGR1; [Fig. 2 & 4]) (Examiner’s Note: VGR1 is the VGR signal when the selector switch 18 is set to VR1 and VGR2 is the VGR signal when the selector switch 18 is set to VR2), responsive (implicit because VGR is downstream of the Sa signal; [Fig. 2]) to the control signal (signal Sa; [Fig. 2]), to partially turn on (implicit of VGR1 being less than the full potential of VGR2; [Fig. 4]) an output switch (IGBT 6; [Fig. 2]) of a driver circuit (gate driver 7; [Fig. 2]); obtaining overcurrent detection results (signal Sc; [0060] & [Fig. 2]) while the output switch is in the partially turned on state (Examiner’s Note: Senda teaches the overcurrent detection continuously occurring from t3 to t5 as shown in Fig. 4. Fig. 4 shows the function of the gate of IGBT 6 fully turning on when no overcurrent has been detected at t5; while Fig. 5 shows the function of the gate of IGBT 6 when an overcurrent is detected and the gate shuts off [0061]. Therefore, the overcurrent detection results are collected at the same time as the gate at the level VGR1.); and after a delay interval (time period from t3 to t5, also see mirror period for a subset of the delay; [0058-0059] & [Fig. 4]), providing a second switch control signal (signal VGR2; [Fig. 2 & 4]) to fully turn on (implicit of VGR2 being the maximum turn on voltage of the gate for IGBT 6; [Fig. 4]) the output switch responsive to the overcurrent detection results indicating there is no overcurrent condition (implicit with the gate voltage increasing to VGR2; [0058-0061] & [Fig. 4]).
In regards to claim 18, Senda teaches the method of claim 17, wherein the second switch control signal is stronger (VGR2-Vt is a higher level than VGR1-Vt as shown in Fig. 4; [Fig. 4]) than the first switch control signal.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Senda, US20150236686 (hereinafter referred to as Senda) in view of Fukushima et al., US20220302822 (hereinafter referred to as Fukushima).
In regards to claim 20, Senda teaches the method of claim 17, wherein obtaining the overcurrent detection results includes: receiving an output voltage (current sensing emitter; [0053] & [Fig. 2]) of the driver circuit (gate driver 7; [Fig. 2]).
Senda does not teach the method wherein obtaining the overcurrent detection results includes: comparing the output voltage to a reference voltage; and if the output voltage is greater than the reference voltage, providing comparison results indicating there is no overcurrent condition.
Fukushima teaches the method wherein obtaining the overcurrent detection results (SC_DET; [0057] & [Fig. 1]) includes: comparing the output voltage (output voltage Vout; [0057] & [Fig. 1]) to a reference voltage (reference voltage Vref2; [0057]); and if the output voltage is greater (higher voltage; [0056]) than the reference voltage, providing comparison results indicating there is no overcurrent condition (low level of signal SC_DET; [0056]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Senda to incorporate the method wherein obtaining the overcurrent detection results includes: comparing the output voltage to a reference voltage; and if the output voltage is greater than the reference voltage, providing comparison results indicating there is no overcurrent condition as taught by Fukushima. The motivation for doing so is to check to make sure the OC condition has cleared before resuming normal operation.
Allowable Subject Matter
Claims 1-18 & 20-21 are allowed.
The claimed combination found within independent claims 1, 10, & 17 are considered novel and unobvious in view of the prior art of record. The closest prior art is considered to be Mochiki et al., US10855269 (hereinafter referred to as Mochiki), Duvnjak, US9954461 (hereinafter referred to as Duvnjak), and Tanabe et al., US10483873.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 1, the prior art of record, either singularly or in combination, does not disclose or suggest the combination or limitations including “overcurrent detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the overcurrent detection circuitry configured to receive a first control signal on the third terminal of the overcurrent detection circuitry, and provide an overcurrent detection signal at the fourth terminal of the overcurrent detection circuitry responsive to the first control signal; and switch control circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the switch control circuitry coupled to the second terminal of the overcurrent detection circuitry, the second terminal of the switch control circuitry coupled to the third terminal of the overcurrent detection circuitry, and the third terminal of the switch control circuitry coupled to the first terminal of the overcurrent control circuit, wherein the switch control circuitry is configured to: receive the first control signal on the second terminal of the switch control circuitry; and provide a second control signal to the control terminal of the output switch responsive to a delay interval relative to the first control signal and overcurrent detection results obtained by the overcurrent detection circuitry during the delay interval.” Mochiki teaches of a driver circuitry as a switch control circuitry with an overcurrent detection and control circuitry, but does not teach two different signals coupled between the overcurrent detection circuitry and the switch control circuitry. Tanabe teaches of a drive circuit, switch control circuitry, an overcurrent detection circuit and protection circuit, overcurrent detection circuit, but also does not teach two different signals coupled between the overcurrent detection circuitry and the switch control circuitry.
Claims 2-9 and 21 are allowed based on dependence of claim 1.
In regards to claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination or limitations including “overcurrent detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, overcurrent detection circuitry configured to: receive a pulse-width modulation (PWM) control signal on the third terminal of the overcurrent detection circuitry, and provide an overcurrent detection signal at the fourth terminal of the overcurrent detection circuitry responsive to the PWM control signal; switch control circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the switch control circuitry coupled to the second terminal of the overcurrent detection circuitry, the second terminal of the switch control circuitry coupled to the third terminal of the overcurrent detection circuitry, and the third terminal of the switch control circuitry coupled to control terminal of the output switch, the switch control circuitry configured to: receive the PWM control signal on the second terminal of the switch control circuitry; and provide a control signal to the control terminal of the output switch responsive to the PWM control signal and the overcurrent detection signal.” Mochiki teaches of a driver circuitry as a switch control circuitry with an overcurrent detection and control circuitry, but does not teach two different signals coupled between the overcurrent detection circuitry and the switch control circuitry. Tanabe teaches of a drive circuit, switch control circuitry, an overcurrent detection circuit and protection circuit, overcurrent detection circuit, but also does not teach two different signals coupled between the overcurrent detection circuitry and the switch control circuitry. The PWM signal is taught going to the driver circuitry, but not the overcurrent detection circuitry for both Mochiki and Tanabe.
Claims 12-16 are allowed based on dependence of claim 10.
Conclusion
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838