Non-Final Rejection
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-4, 6-12, and 14-16 are rejected under 35 U.S.C. 103
Claims 5 and 13 have been canceled by Applicant
Response to Amendment
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4, 6, 9-12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (U.S. Publication No. 2023/0205574 A1), hereinafter referred to as Hsu in view of Montero et al. (U.S. Patent No. 10,067,834 B1), hereinafter referred to as Montero.
With regards to Claim 1, Hsu teaches:
A method for handling failures in an information handling system, the method comprising:
enabling one or more crash handlers to communicate crash handler notifications to an embedded controller (EC) of the information handling system (Fig. 1; Paragraph 0037-0038: regarding the SMI handler collecting and sending the SMI to a memory accessible by the BMC), wherein the EC is configured to perform keyboard controller functions (Paragraphs 0030-0034, 0036, and 0040 and Fig. 1, errors relating to PCIe, USB, and other external devices, including keyboards; Paragraph 0047) and one or more system management functions selected from: one or more thermal management functions and one or more battery management functions (Paragraphs 0035-0036);
associating one or more general purpose input/output (GPIO) pins with crash handling … to indicate a crash occurrence (Paragraph 0034: regarding the SMI signal and a designated pin);
configuring the EC to perform crash operations including:
registering the EC to poll status of the one or more GPIO pins (Fig. 1 and Paragraphs 0026, 0031, 0034, 0038, and 0042);
detecting a crash occurrence (Paragraph 0033: regarding how the CPU chipset detects interrupts and triggers the SMM; Paragraph 0027: regarding how the CPU chipset includes the BMC) associated with either:
a crash handler notification indicated by the status of the one or more GPIO pins (Paragraphs 0031 and 0034, SMI and pin; Paragraph 0039: the SMI can be triggered by “an uncorrectable error that may cause a system reboot or hang); or a system management mode (SMM) crash event (Fig. 1; Paragraphs 0031 and 0034: regarding how the SMM can be entered when the SMI is signaled to the SMI input port, that is coupled to the BMC);
and extracting and storing crash context information associated with the crash occurrence (Paragraph 0038: regarding how the BMC can store and retrieve data).
Hsu does not explicitly teach:
and configuring at least one of the crash handlers to toggle at least one of the one or more GPIO pins
However, Montero teaches:
… keyboard … (Col. 6, Lines 40-67, keyboard as an I/O device and PCH) and one or more system management functions selected from: one or more thermal management functions and one or more battery management functions (Col. 7, Lines 1-39);
associating one or more general purpose input/output (GPIO) pins with crash handling; and configuring at least one of the crash handlers to toggle at least one of the one or more GPIO pins to indicate a crash occurrence (Col. 3, Lines 31-46: regarding the toggling of I/O pins in response to a watchdog timer event);
… indicated by the status of the one or more GPIO pins (Col 10, Lines 39-55) …
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to toggle the GPIO pins of Hsu for additional functionality as taught by Montero (Col. 2, Lines 44-61: regarding how the toggling of I/O pins can “ensure that a defined signal level is present on the first and second I/O pins” before a reset).
With regards to Claim 2, Hsu in view of Montero teaches the method of Claim 1 as referenced above. Hsu in view of Montero further teaches:
wherein crash handler notifications are communicated to the EC (Hsu, Fig. 1; Paragraph 0037-0038: regarding the SMI handler collecting and sending the SMI to a memory accessible by the BMC) as MBOX commands via a peripheral interconnect (Montero, Col. 8, Lines 5-16: regarding an eSPI bus used to communicate commands with the EC in response to an error). Note: MBOX commands are being broadly interpreted as being commands relating to the communication of crash data, as disclosed in Fig. 1 and Page 12 of Applicant’s specification.
With regards to Claim 3, Hsu in view of Montero teaches the method of Claim 2 as referenced above. Hsu in view of Montero further teaches:
wherein the peripheral interconnect comprises an enhanced serial peripheral interconnect (eSPI) (Montero, Col. 8, Lines 5-16: regarding an eSPI bus used to communicate commands with the EC).
With regards to Claim 4, Hsu in view of Montero teaches the method of Claim 1 as referenced above. Hsu in view of Montero further teaches:
wherein detecting a crash occurrence associated with the SMM event includes: initiating an EC timer responsive to receiving an SMM entry message from an SMM handler; and detecting the EC timer reaching a threshold value before the EC receives an SMM exit message (Hsu, Paragraph 0044: regarding the SMI being triggered by a watchdog timer).
With regards to Claim 6, Hsu in view of Montero teaches the method of Claim 1 as referenced above. Hsu in view of Montero further teaches:
wherein said configuring of at least one of the crash handlers comprises configuring a basic input/output system (BIOS) crash handler (Hsu, Paragraph 0032: regarding the BIOS SMI handler; Hsu, Paragraph 0036: regarding how the BIOS can trigger the SMI) to toggle (Montero, Col. 3, Lines 31-46: regarding the toggling of I/O pins in response to a watchdog timer event) at least one of the one or more GPIO pins (Hsu, Paragraph 0034: regarding the SMI signal and a designated pin).
With regards to Claim 9, Hsu in view of Montero teaches:
An information handling system comprising:
a central processing unit (CPU) (Hsu, Paragraph 0027: regarding the CPU);
an embedded controller (EC) (Hsu, Paragraph 0026: regarding the BMC);
a system memory, accessible to the CPU, including processor executable instructions that, when executed by the CPU, cause the system to perform operations including (Hsu, Paragraph 0052: regarding the instructions being stored on a memory and accessed by a processor and a controller) …
Please see above the above rejection of Claim 1 for citations of the remaining limitations, as well as the motivation to combine references in accordance with 35 U.S.C. 103.
All limitations of Claims 10-12 and 14 have been addressed in the analyses of Claims 2-4 and 6, respectively. Please see the above rejections for further details.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu in view of Montero, in further view of Raynham et al. (U.S. Patent No. 5,774,647), hereinafter referred to as Raynham.
With regards to Claim 7, Hsu in view of Montero teaches the method of Claim 1 as cited above. Hsu in view of Montero further teaches:
the EC … indicative of the crash occurrence (Hsu, Paragraph 0029: regarding the BMC communicating data related to a crash with external and internal devices)
Hsu in view of Montero does not explicitly teach:
illuminating, by the EC, light emitting diodes (LEDs) of the EC selectively to generate an LED pattern indicative of the crash occurrence.
However, Raynham teaches:
illuminating, by the EC, light emitting diodes (LEDs) of the EC (Col. 3, Lines 33-36: regarding how the memory management controller connects to the LED indicators) selectively to generate an LED pattern indicative of the crash occurrence (Fig. 4; Col. 4, Lines 6-12: regarding different LED patterns being associated with different error conditions).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to add the feature of LED patterns indicative of a crash occurrence, as taught by Raynham, to the method of Hsu in view of Montero in order to visually indicate different errors to the user (Raynham, Col. 3, Lines 40-56 – Col. 4, Lines 1-5: regarding how different lights indicate different errors).
With regards to Claim 8, Hsu in view of Montero in further view of Raynham teaches the method of Claim 7 as referenced above. Hsu in view of Montero in further view of Raynham further teaches:
wherein the LED pattern is selected from a plurality of LED patterns, where each LED pattern corresponds to a particular crash event (Raynham, Fig. 4; Col. 4, Lines 6-12: regarding different LED patterns being associated with different error conditions).
All limitations of Claims 15 and 16 have been addressed in the analyses of Claims 7 and 8, respectively. Please see the above rejections for further details, including the motivation to combine references in accordance with 35 U.S.C. 103.
Response to Arguments
Applicant's arguments filed on January 20th, 2026, have been fully considered but they are not persuasive.
With regards to arguments that the newly claimed features are not taught by the art, Examiner respectfully disagrees. The prior art has been cited above as teaching all of the amended features.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Dreamlayers, “How an I/O port leads to System Management Mode,” 2012: teaches the relationship between I/O ports, keyboards, and SMM
IBM, “System Management Mode”: teaches various features of SMM, including its relation to I/O devices and registers
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/G.K.S./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113