DETAILED ACTION
Claims 1-27 are pending. Claims 1, 25, 26, and 27 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner was unable to find the foreign documents/non-patent literature noted in the IDS dated (09/01/2023) in the instant applications file wrapper. However, Examiner did consider them by finding them in the file wrapper of the co-pending application (18/176,183). Examiner recommends adding them to the file wrapper of this case as well for clarity of prosecution. All elements of the IDS were considered.
Examiner also notes that the double patenting rejection is currently a provisional; however, it appears that the co-pending application, recited below in the double patenting rejection, already has a notice of allowance of record and is awaiting patent publication. Therefore, the Examiner wants to provide ease of prosecution for the Applicant by making this situation apparent.
Reception nodes in the independent claims are not being interpreted under 112(f) because they are integrated into a single integrated circuit (IC) package. Additionally, paragraph [0066] of the instant application clearly speaks about electrodes in the reception nodes being utilized. Therefore, the Examiner is interpreting these elements as physical hardware.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-4, 6-10, 13, 15-17, 20, and 25-27 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1
Claims 1-4, 6-10, 13, 15, 20, 25, and 27 recite an apparatus with processors. Thus, these claims are directed to a system, which is one of the statutory categories of invention. Claim 26 recites a method that includes specific steps. Thus, these claims are directed to a method, which is one of the statutory categories of invention.
Next, the claims are evaluated to determine whether the claims recite a judicial exception.
Step 2A Prong 1
Claim 1 recites:
An apparatus, comprising:
reception nodes configured to receive input signals of an analog domain;
main signal processors configured to perform a signal processing operation on the input signals; and
auxiliary signal processors configured to replace the main signal processors, and perform at least a portion of the signal processing operation in response to a replacement condition being satisfied,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 2 recites:
The apparatus of claim 1, wherein the signal processing operation comprises at least one of a digital conversion operation, a signal generation operation, a signal amplification operation, a control operation, and a clock generation operation.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 3 recites:
The apparatus of claim 1, wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO) performing a digital conversion operation on a corresponding input signal of the input signals.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 4 recites:
The apparatus of claim 1, further comprising:
multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 6 recites:
The apparatus of claim 1, wherein the single IC package comprises at least one die in which the reception nodes, the main signal processors, and the auxiliary signal processors are integrated in at least a partial form of a stack package and a system in package.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 7 recites:
The apparatus of claim 1, wherein the input signals are received through 10 or more channels.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 8 recites:
The apparatus of claim 1, wherein the input signals are received through 10,000 or more channels.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 9 recites:
The apparatus of claim 1, wherein the input signals correspond to an electrical signal.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 10 recites:
wherein the auxiliary signal processors are configured to perform at least some of the signal processing operation in real-time instead of the main signal processors in response to the replacement condition being satisfied.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 13 recites:
The apparatus of claim 1, further comprising:
at least one controller configured to determine whether the main signal processors satisfy the replacement condition based on a performance test of the main signal processors.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 15 recites:
The apparatus of claim 13, wherein the at least one controller is further configured to, when a plurality of replacement targets satisfying the replacement condition among the main signal processors is detected, determine a replacement priority of the replacement targets based on a degree of defect due to at least one of an error and performance degradation of the replacement targets, and apply the auxiliary signal processors in order of high replacement priority.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 16 recites:
The apparatus of claim 1, wherein the replacement condition is based on a defect of the main signal processors due to at least one of an error and performance degradation of the main signal processors.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 17 recites:
The apparatus of claim 1, further comprising:
an electrode array measuring the input signal through electrodes disposed on a target point.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 20 recites:
The apparatus of claim 17, wherein, before the replacement condition is satisfied, the main signal processors are respectively connected to the electrodes.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 25 recites:
An apparatus comprising:
reception nodes configured to receive input signals of an analog domain;
main signal processors configured to perform a signal processing operation on the input signals; and
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation based on a defect of the main signal processors,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single chip.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 26 recites:
A method comprising:
receiving input signals of an analog domain;
performing a signal processing operation on the input signals using main signal processors; and
performing at least a portion of the signal processing operation using auxiliary signal processors instead of the main signal processors in response to a replacement condition being satisfied,
wherein the main signal processors and the auxiliary signal processors are implemented in a single integrated circuit (IC) package or a single chip.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Claim 27 recites:
A biologic response recording apparatus comprising:
a measuring instrument comprising:
an electrode array configured to generate input signals corresponding to data measured at target points through electrodes disposed on the target points,
main signal processors configured to perform a signal processing operation comprising a digital conversion operation of corresponding input signals of the input signals, respectively, and
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation including the digital conversion operation in response to a replacement condition being satisfied; and
a memory configured to store response data output by at least some of the main signal processors and the auxiliary signal processors.
The examiner submits that the foregoing italicized/bolded/underlined limitations comprise a mental process because this subject matter can be completed by a person with merely the aid of a pen and paper.
Next, the claims are evaluated to determine whether the claim as a whole integrates the abstract idea into a practical application of the exception.
Step 2A Prong 2
The claims includes the following additional limitations: “An apparatus, comprising”, “reception nodes configured”, “main signal processors configured”, “auxiliary signal processors”, “wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package”, “auxiliary signal processors configured to replace the main signal processors”, “wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO)”, “multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors”, “multiplexers (MUXs)”, “wherein the single IC package comprises at least one die in which the reception nodes, the main signal processors, and the auxiliary signal processors are integrated in at least a partial form of a stack package and a system in package”, “constitute a plurality of slots”, “dedicatedly and respectively allocated to the plurality of slots”, “at least one controller”, “an electrode array measuring the input signal through electrodes disposed on a target point”, “the main signal processors are respectively connected to the electrodes”, “A biologic response recording apparatus”, “a memory configured”, “receive input signals of an analog domain”, “wherein the input signals are received through 10 or more channels”, “wherein the input signals are received through 10,000 or more channels”, “wherein the input signals correspond to an electrical signal”, “an electrode array configured”, and “store response data output by at least some of the main signal processors and the auxiliary signal processors”.
Regarding “An apparatus, comprising”, “reception nodes configured”, “main signal processors configured”, “auxiliary signal processors”, “wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package”, “auxiliary signal processors configured to replace the main signal processors”, “wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO)”, “multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors”, “multiplexers (MUXs)”, “wherein the single IC package comprises at least one die in which the reception nodes, the main signal processors, and the auxiliary signal processors are integrated in at least a partial form of a stack package and a system in package”, “constitute a plurality of slots”, “dedicatedly and respectively allocated to the plurality of slots”, “at least one controller”, “an electrode array measuring the input signal through electrodes disposed on a target point”, “the main signal processors are respectively connected to the electrodes”, “A biologic response recording apparatus”, and “a memory configured” the examiner submits that these additional limitations are referencing generic computer components and merely includes instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea.
Regarding “receive input signals of an analog domain”, “wherein the input signals are received through 10 or more channels”, “wherein the input signals are received through 10,000 or more channels”, “wherein the input signals correspond to an electrical signal”, “an electrode array configured”, and “store response data output by at least some of the main signal processors and the auxiliary signal processors”, the examiner submits that these additional limitations could simply refer to as merely storing or retrieving data information in memory. Therefore, in support of this conclusion, see MPEP 2106.05(d)(II) which states that courts have recognized storing and retrieving information in memory are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
Thus, taken alone, the additional elements do not integrate the abstract idea into a practical application of the exception.
Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. For example, there is no indication that the combination of elements improves the functioning of a computer or improves any other technology.
Next, the claims as a whole are analyzed to determine whether any element, or combination of elements, is sufficient to ensure that the claims amount to significantly more than the exception.
Step 2B
Regarding “An apparatus, comprising”, “reception nodes configured”, “main signal processors configured”, “auxiliary signal processors”, “wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package”, “auxiliary signal processors configured to replace the main signal processors”, “wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO)”, “multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors”, “multiplexers (MUXs)”, “wherein the single IC package comprises at least one die in which the reception nodes, the main signal processors, and the auxiliary signal processors are integrated in at least a partial form of a stack package and a system in package”, “constitute a plurality of slots”, “dedicatedly and respectively allocated to the plurality of slots”, “at least one controller”, “an electrode array measuring the input signal through electrodes disposed on a target point”, “the main signal processors are respectively connected to the electrodes”, “A biologic response recording apparatus”, and “a memory configured” the examiner submits that these additional limitations are referencing generic computer components and merely includes instructions to implement the abstract idea on a computer, or merely uses a computer as a tool to perform the abstract idea.
Regarding “receive input signals of an analog domain”, “wherein the input signals are received through 10 or more channels”, “wherein the input signals are received through 10,000 or more channels”, “wherein the input signals correspond to an electrical signal”, “an electrode array configured”, and “store response data output by at least some of the main signal processors and the auxiliary signal processors”, the examiner submits that these additional limitations could simply refer to as merely storing or retrieving data information in memory. Therefore, in support of this conclusion, see MPEP 2106.05(d)(II) which states that courts have recognized storing and retrieving information in memory are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity.
Thus, taken alone, the additional elements do not amount to significantly more than the exception.
Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. For example, there is no indication that the combination of elements improves the functioning of a computer or improves any other technology.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Long!, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321 (d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321 (b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit https://www.uspto.gov/patent/forms/forms-patent-applications-filed-or-after-september-16-2012. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to https://www.uspto.gov/patents-application-process/applying-online/eterminal-disclaimer.
Claims 1-4, 9, 11-13, and 16-26 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9, 12-15, and 17 of copending Application No. 18/176,183 (‘183 app) in view of U.S. Publication No. 2019/0326921 to Fick et al. ("Fick"). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims under examination are taught by claims of the ‘183 app in view of Fick. Every limitation in claims 1-4, 9, 11-13, and 16-26 is taught in the conflicting reference patent claims and Fick, and the differences between the claims will be addressed below.
This is a provisional nonstatutory double patenting rejection.
For example, the elements of claim 1, of the present application are patentably indistinct from the elements of claim 1 of the ‘183 app in view of Fick. The proceeding table maps representative claim 1 from the instant application to claim 1 of the ‘183 app in view of Fick.
Claim 1 of the Instant Application
Claim 1 of the ‘183 app
Fick
An apparatus, comprising:
reception nodes configured to receive input signals of an analog domain;
main signal processors configured to perform a signal processing operation on the input signals; and
auxiliary signal processors configured to replace the main signal processors, and perform at least a portion of the signal processing operation in response to a replacement condition being satisfied,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package.
An apparatus, comprising:
an electrode array configured to measure input signals of an analog domain through electrodes arranged in a target point;
main signal processors configured to perform signal processing operations on corresponding respective input signals of the input signals;
auxiliary signal processors configured to replace at least one of the main signal processors, and perform at least some of the signal processing operations in response to a replacement condition being satisfied, and
a controller configured to, when a plurality of replacement targets satisfying the replacement condition is detected from the main signal processors, determine a replacement priority of the replacement targets based on a defect level of the replacement targets.
(Fick: Paragraph [0024], “In one embodiment, a method of implementing an integrated circuit includes: receiving an analog input signal at each of a plurality of distinct programmable current sources”)
(Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”)
As shown in the mapping above, claim 1 of the ‘183 app in view of Fick includes all the limitations of claim 1 of the instant application, while also reciting further limitations. Although, the ‘183 app does not recite the element regarding an integrated circuit and reception nodes receiving the signal; it would be obvious to one skilled in the art to combine Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]). Thus, claim 1 of the ‘183 app in view of Fick teaches claim 1 of the instant application.
For example, the elements of claim 25, of the present application are patentably indistinct from the elements of claim 1 of the ‘183 app in view of Fick. The proceeding table maps representative claim 25 from the instant application to claim 1 of the ‘183 app in view of Fick.
Claim 25 of the Instant Application
Claim 1 of the ‘183 app
Fick
An apparatus comprising:
reception nodes configured to receive input signals of an analog domain;
main signal processors configured to perform a signal processing operation on the input signals; and
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation based on a defect of the main signal processors,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single chip.
An apparatus, comprising:
an electrode array configured to measure input signals of an analog domain through electrodes arranged in a target point;
main signal processors configured to perform signal processing operations on corresponding respective input signals of the input signals;
auxiliary signal processors configured to replace at least one of the main signal processors, and perform at least some of the signal processing operations in response to a replacement condition being satisfied, and
a controller configured to, when a plurality of replacement targets satisfying the replacement condition is detected from the main signal processors, determine a replacement priority of the replacement targets based on a defect level of the replacement targets.
(Fick: Paragraph [0024], “In one embodiment, a method of implementing an integrated circuit includes: receiving an analog input signal at each of a plurality of distinct programmable current sources”)
(Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”)
As shown in the mapping above, claim 1 of the ‘183 app in view of Fick includes all the limitations of claim 25 of the instant application, while also reciting further limitations. Although, the ‘183 app does not recite the element regarding an integrated circuit and reception nodes receiving the signal; it would be obvious to one skilled in the art to combine Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]). Thus, claim 1 of the ‘183 app in view of Fick teaches claim 25 of the instant application.
For example, the elements of claim 26, of the present application are patentably indistinct from the elements of claim 17 of the ‘183 app in view of Fick. The proceeding table maps representative claim 26 from the instant application to claim 17 of the ‘183 app in view of Fick.
Claim 26 of the Instant Application
Claim 17 of the ‘183 app
Fick
A method comprising:
receiving input signals of an analog domain;
performing a signal processing operation on the input signals using main signal processors; and
performing at least a portion of the signal processing operation using auxiliary signal processors instead of the main signal processors in response to a replacement condition being satisfied,
wherein the main signal processors and the auxiliary signal processors are implemented in a single integrated circuit (IC) package or a single chip.
A method comprising: measuring input signals of an analog domain through electrodes of an electrode array arranged in a target point; performing signal processing operations on corresponding respective input signals of the input signals by implementing respective main signal processors; and performing at least some of the signal processing operations by implementing auxiliary signal processors instead of the main signal processors in response to a replacement condition being satisfied, includinq, when a plurality of replacement targets satisfying the replacement condition is detected from the main signal processors, determining a replacement priority of the replacement targets based on a defect level of the replacement targets.
(Fick: Paragraph [0024], “In one embodiment, a method of implementing an integrated circuit includes: receiving an analog input signal at each of a plurality of distinct programmable current sources”)
(Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”)
As shown in the mapping above, claim 17 of the ‘183 app in view of Fick includes all the limitations of claim 26 of the instant application, while also reciting further limitations. Although, the ‘183 app does not recite the element regarding an integrated circuit and reception nodes receiving the signal; it would be obvious to one skilled in the art to combine Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]). Thus, claim 17 of the ‘183 app in view of Fick teaches claim 26 of the instant application.
Claims 2-24 are children claims of the parent claim 1. Therefore, the ‘183 app and Fick are obviously used together for the same reason listed above for their parent claim. Below is the mapping of claims 2-24 for their respective non-statutory provisional double patenting rejection.
Claim 2 of the Instant Application
Claim 2 of the ‘183 app
The apparatus of claim 1, wherein the signal processing operation comprises at least one of a digital conversion operation, a signal generation operation, a signal amplification operation, a control operation, and a clock generation operation.
The apparatus of claim 1, wherein the signal processing operations comprise at least one of a digital conversion operation, a signal generation operation, a signal amplification operation, a control operation, and a clock generation operation.
Claim 3 of the Instant Application
Claim 5 of the ‘183 app
Fick
The apparatus of claim 1, wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO) performing a digital conversion operation on a corresponding input signal of the input signals.
The apparatus of claim 2, wherein each of the main signal processors comprise an analog digital converter (ADC) configured to perform the digital conversion operation.
(Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”)
Claim 4 of the Instant Application
Claim 4 of the ‘183 app
The apparatus of claim 1, further comprising:
multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors.
The apparatus of claim 3, wherein the main signal processors comprise a first main signal processor connected to a first electrode of the electrodes, the MUXs comprise a first MUX configured to selectively connect a first auxiliary signal processor of the auxiliary signal processors to first candidate electrodes comprising the first electrode, and the first MUX is configured to connect the first electrode to the first auxiliary signal processor in response to the replacement condition being satisfied by the first main signal processor.
Claim 9 of the Instant Application
Fick
The apparatus of claim 1, wherein the input signals correspond to an electrical signal.
(Fick: Paragraph [0058], “In some embodiments, the input circuit 110 may be configured as a single circuit with multiple signal output ports where each of the multiple output ports may be in electrical communication with a signal input terminal of a programmable current source 120. That is, each signal output port may be electrically coupled or otherwise, electrically connected to a corresponding signal input receiving terminal of a programmable current source 120 or of paired programmable current sources 120”)
Claim 11 of the Instant Application
Claim 7 of the ‘183 app
The apparatus of claim 1, wherein the main signal processors are divided in a predetermined first number and constitute a plurality of slots, and
the auxiliary signal processors are divided in a predetermined second number and dedicatedly and respectively allocated to the plurality of slots.
The apparatus of claim 1, wherein the main signal processors are divided into a predetermined first number of main signal processors, and configure a plurality of slots, and
the auxiliary signal processors are divided into a predetermined second number of auxiliary signal processors, and are dedicatedly allocated to each of the plurality of slots.
Claim 12 of the Instant Application
Claim 8 of the ‘183 app
The apparatus of claim 1, wherein the main signal processors are divided in a predetermined first number and constitute a plurality of slots, and
the auxiliary signal processors are allocated to the plurality of slots such that a predetermined third number of slots of the plurality of slots share at least some of the auxiliary signal processors.
The apparatus of claim 1, wherein the main signal processors are divided into a predetermined first number, and configure a plurality of slots, and the auxiliary signal processors are allocated to the plurality of slots such that a predetermined third number of slots of the plurality of slots share at least a portion of the auxiliary signal processors.
Claim 13 of the Instant Application
Claim 9 of the ‘183 app
The apparatus of claim 1, further comprising:
at least one controller configured to determine whether the main signal processors satisfy the replacement condition based on a performance test of the main signal processors.
The apparatus of claim 1, wherein the controller is configured to determine whether the main signal processors satisfy the replacement condition based on a performance test of the main signal processors.
Claim 16 of the Instant Application
Fick
wherein the replacement condition is based on a defect of the main signal processors due to at least one of an error and performance degradation of the main signal processors.
(Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”; wherein the replacement condition is failure requiring a redundant ADC to replace the failed component; wherein failure is equated to an error and performance degradation)
Claim 17 of the Instant Application
Claim 1 of the ‘183 app
The apparatus of claim 1, further comprising:
an electrode array measuring the input signal through electrodes disposed on a target point.
An apparatus, comprising:
an electrode array configured to measure input signals of an analog domain through electrodes arranged in a target point;
main signal processors configured to perform signal processing operations on corresponding respective input signals of the input signals;
auxiliary signal processors configured to replace at least one of the main signal processors, and perform at least some of the signal processing operations in response to a replacement condition being satisfied, and
a controller configured to, when a plurality of replacement targets satisfying the replacement condition is detected from the main signal processors, determine a replacement priority of the replacement targets based on a defect level of the replacement targets.
Claim 18 of the Instant Application
Claim 3 of the ‘183 app
The apparatus of claim 17, further comprising:
multiplexers (MUXs) connecting candidate electrodes of the electrodes to corresponding auxiliary signal processors of the auxiliary signal processors.
The apparatus of claim 1, further comprising: multiplexers (MUXs) configured to selectively connect candidate electrodes of the electrodes to corresponding auxiliary signal processors of the auxiliary signal processors.
Claim 19 of the Instant Application
Claim 4 of the ‘183 app
The apparatus of claim 18, wherein the main signal processors comprise a first main signal processor connected to a first electrode of the electrodes,
the MUXs comprise a first MUX configured to selectively connect a first auxiliary signal processor of the auxiliary signal processors to first candidate electrodes comprising the first electrode, and
the first MUX is configured to connect the first electrode to the first auxiliary signal processor in response to the replacement condition being satisfied by the first main signal processor.
The apparatus of claim 3, wherein the main signal processors comprise a first main signal processor connected to a first electrode of the electrodes, the MUXs comprise a first MUX configured to selectively connect a first auxiliary signal processor of the auxiliary signal processors to first candidate electrodes comprising the first electrode, and
the first MUX is configured to connect the first electrode to the first auxiliary signal processor in response to the replacement condition being satisfied by the first main signal processor.
Claim 20 of the Instant Application
Claim 6 of the ‘183 app
The apparatus of claim 17, wherein, before the replacement condition is satisfied, the main signal processors are respectively connected to the electrodes.
The apparatus of claim 1, wherein the main signal processors are connected to the respective electrodes before the replacement condition is satisfied.
Claim 21 of the Instant Application
Claim 12 of the ‘183 app
wherein the electrodes comprise main electrodes connected to the main signal processors and auxiliary electrodes connected to the auxiliary signal processors, and
the electrode array is configured to measure the input signals using the main electrodes and the auxiliary electrodes.
wherein the electrodes comprise main electrodes connected to the main signal processors and auxiliary electrodes connected to the auxiliary signal processors, and
the electrode array is configured to measure the input signals by implementing the main electrodes and the auxiliary electrodes.
Claim 22 of the Instant Application
Claim 13 of the ‘183 app
wherein the main signal processors comprise a first main signal processor connected to a first main electrode of the main electrodes,
the auxiliary signal processors comprise a first auxiliary signal processor connected to a first auxiliary electrode of the auxiliary electrodes, and the first auxiliary signal processor is connected to the first main electrode instead of the first main signal processor in response to the replacement condition being satisfied by the first main signal processor.
wherein the main signal processors comprise a first main signal processor connected to a first main electrode among the main electrodes, the auxiliary signal processors comprise a first auxiliary signal processor connected to a first auxiliary electrode among the auxiliary electrodes, and the first auxiliary signal processor is configured to replace the first main signal processor and connect to the first main electrode in response to the replacement condition being satisfied by the first main signal processor.
Claim 23 of the Instant Application
Claim 14 of the ‘183 app
wherein the main electrodes are arranged in a central area of the electrode array compared to the auxiliary electrodes, and data measurement through the first auxiliary electrode is paused in response to the replacement condition being satisfied by the first main signal processor.
wherein the main electrodes are arranged in a central area of the electrode array compared to the auxiliary electrodes, and data measurement through the first auxiliary electrode is paused in response to the replacement condition being satisfied by the first main signal processor.
Claim 24 of the Instant Application
Claim 15 of the ‘183 app
wherein the main signal processors comprise first main signal processors selectively connected to each electrode of a first electrode group among the electrodes,
the auxiliary signal processors comprise first auxiliary signal processors selectively connected to each electrode of the first electrode group, and
some of the first main signal processors and the first auxiliary signal processors selected in order from a high performance level to a low performance level are applied to the first electrode group.
wherein the main signal processors comprise first main signal processors selectively connected to each electrode of a first electrode group among the electrodes,
the auxiliary signal processors comprise first auxiliary signal processors selectively connected to each electrode of the first electrode group, and some of the first main signal processors and the first auxiliary signal processors selected in order from a high performance level to a low performance level are applied to the first electrode group.
Claim 10 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/176,183 (‘183 app) in view of Fick and further in view of U.S. Patent No. 4,984,240 to Keren-Zvi et al. ("Keren-Zvi"). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims under examination are taught by claims of the ‘183 app in view of Keren-Zvi. Every limitation in claim 10 is taught in the conflicting reference patent claims and Keren-Zvi, and the differences between the claims will be addressed below.
This is a provisional nonstatutory double patenting rejection.
For example, the elements of claim 10, of the present application are patentably indistinct from the elements of claim 1 of the ‘183 app in view of Fick and further in view of Keren-Zvi. The proceeding table maps representative claim 10 from the instant application to claim 1 of the ‘183 app in view of Fick and further in view of Keren-Zvi.
Claim 10 of the Instant Application
Keren-Zvi
wherein the auxiliary signal processors are configured to perform at least some of the signal processing operation in real-time instead of the main signal processors in response to the replacement condition being satisfied.
(Keren-Zvi: Fig. 3, #212n; Col. 6, lines 59-68, “The module controller in the agent module also notifies module controller 222.sub.N in spare module 212.sub.N of the failure of its client and sends the configuration of the signal processor of the failed module to spare module controller 222.sub.N via control bus 230. Module controller 222.sub.N configures signal processor 220.sub.N accordingly and causes fault monitor 224.sub.N to change switches 226a, 226b to position "3", thereby coupling signal processor 220.sub.N to auxiliary signal buses 218a, 218b so that spare module 212.sub.N replaces the failed module in the system”; wherein the module 212n including processors replaces the failed module with a mere flip of a switch and therefore the data will be processed real-time when the switch is flipped)
As shown in the mapping above, claim 1 of the ‘183 app in view of Fick and further in view of Keren-Zvi includes all the limitations of claim 27 of the instant application, while also reciting further limitations. Although, the ‘183 app does not recite the element of the auxiliary processors taking over real-time processing for the main processors; it would be obvious to one skilled in the art to combine Keren-Zvi. One of ordinary skill in the art would have been motivated to use the methods of Keren-Zvi because it would improve redundancy of the system. (Keren-Zvi: Col. 1, lines 36-44). Thus, claim 1 of the ‘183 app in view of Fick and further in view of Keren-Zvi teaches claim 10 of the instant application.
Claim 27 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 18/176,183 (‘183 app) in view of U.S. Publication No. 2012/0165616 to Geva et al. ("Geva"). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims under examination are taught by claims of the ‘183 app in view of Geva. Every limitation in claim 27 is taught in the conflicting reference patent claims and Geva, and the differences between the claims will be addressed below.
This is a provisional nonstatutory double patenting rejection.
For example, the elements of claim 27, of the present application are patentably indistinct from the elements of claim 1 of the ‘183 app in view of Geva. The proceeding table maps representative claim 27 from the instant application to claim 1 of the ‘183 app in view of Fick.
Claim 27 of the Instant Application
Claim 1 of the ‘183 app
Geva
A biologic response recording apparatus comprising:
a measuring instrument comprising:
an electrode array configured to generate input signals corresponding to data measured at target points through electrodes disposed on the target points,
main signal processors configured to perform a signal processing operation comprising a digital conversion operation of corresponding input signals of the input signals, respectively, and
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation including the digital conversion operation in response to a replacement condition being satisfied; and
a memory configured to store response data output by at least some of the main signal processors and the auxiliary signal processors.
An apparatus, comprising:
an electrode array configured to measure input signals of an analog domain through electrodes arranged in a target point;
main signal processors configured to perform signal processing operations on corresponding respective input signals of the input signals;
auxiliary signal processors configured to replace at least one of the main signal processors, and perform at least some of the signal processing operations in response to a replacement condition being satisfied, and
a controller configured to, when a plurality of replacement targets satisfying the replacement condition is detected from the main signal processors, determine a replacement priority of the replacement targets based on a defect level of the replacement targets.
(Geva: Pargraph [0127], “The sensor interface 50 can include an operational amplifier 50(1) that receives detection signals from one or more primary and/or secondary sensors, a filter 50(2) and an analog to digital converter 50(3). The output of the analog to digital converter 50(3) provides raw medical data. Alternatively, the output of the analog to digital converter 50(3) can be sampled and/or additionally processed to provide the raw medical data”)(Geva: Paragraph [0129], “The portable monitoring unit 110 is attached to a strip 132 that is worn around the neck of a monitored person 160. The portable monitoring unit 110 is coupled by electrodes to primary sensors 16, and communicated by short range transmission with secondary detectors 18 that are worn on a hand cuff 130 and a wristband 136”)
(Geva: Parargaph [0135], “The raw medical information can be received in a continuous manner, in intervals, or in any other manner. The reception can include receiving raw medical information from one or more sensors, storing the raw medical information in a memory module and retrieving the raw medical information from the memory module”; wherein Geva teaches storing raw medical data from the analog to digital converter and is combined with Fick/Guo’s redundant processors)
As shown in the mapping above, claim 1 of the ‘183 app in view of Fick includes all the limitations of claim 27 of the instant application, while also reciting further limitations. Although, the ‘183 app does not recite the element regarding storing into a biologic apparatus including a measuring instrument, a memory module, and electrode arrays arranged at target points to generate input; it would be obvious to one skilled in the art to combine Geva. One of ordinary skill in the art would have been motivated to use the methods of Geva because it would assist in efficiently detecting potential events. (Geva: Paragraphs [0004]-[0005]). Thus, claim 1 of the ‘183 app in view of Geva teaches claim 27 of the instant application.
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 9, 16, and 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication No. 2013/0181856 to Guo et al. (“Guo”) in view of Fick.
Regarding claim 1, Guo teaches:
An apparatus, comprising:
reception nodes configured to receive input signals of an analog domain (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”);
main signal processors configured to perform a signal processing operation on the input signals (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”); and
auxiliary signal processors configured to replace the main signal processors, and perform at least a portion of the signal processing operation (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”)
However, Guo does not explicitly teach:
in response to a replacement condition being satisfied,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package.
However, in the same field of endeavor, Fick teaches:
in response to a replacement condition being satisfied (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”),
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single integrated circuit (IC) package (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Guo by having the processors to be in an integrated circuit and replacing a failed main processor with an auxiliary when a replacement component meets a replacement condition, as taught by Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]).
Regarding claim 2, the Guo/Fick combination teaches all of the elements of claim 1 and further teaches:
wherein the signal processing operation comprises at least one of a digital conversion operation (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”), a signal generation operation, a signal amplification operation, a control operation, and a clock generation operation.
Regarding claim 3, the Guo/Fick combination teaches all of the elements of claim 1 and further teaches:
wherein each of the main signal processors and the auxiliary signal processors comprises an analog digital converter (ADO) performing a digital conversion operation on a corresponding input signal of the input signals (Guo: Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”).
Regarding claim 4, the Guo/Fick combination teaches all of the elements of claim 1 and further teaches:
multiplexers (MUXs) configured to provide a signal path used by one of the auxiliary signal processors to replace one of the main signal processors (Fick: Paragraph [0072], “Further, in such embodiments, a number of redundant ADCs (X) may be deployed for each set of N ADCs in an integrated circuit. In use or operation, outputs of the redundant ADCs may be multiplexed into all N ADC outputs in a given set. This architecture allows for a transparent design that does not add extra parasitics to sensitive analog nodes. In a variant implementation, each defective or corrupt ADC may be shifted by one when a redundant ADC is required. In this way, there is less routing but may require that the digital fabric be aware of the redundancy implementation”).
Regarding claim 9, the Guo/Fick combination teaches all of the elements of claim 1 and further teaches:
wherein the input signals correspond to an electrical signal (Fick: Paragraph [0058], “In some embodiments, the input circuit 110 may be configured as a single circuit with multiple signal output ports where each of the multiple output ports may be in electrical communication with a signal input terminal of a programmable current source 120. That is, each signal output port may be electrically coupled or otherwise, electrically connected to a corresponding signal input receiving terminal of a programmable current source 120 or of paired programmable current sources 120”).
Regarding claim 16, the Guo/Fick combination teaches all of the elements of claim 1 and further teaches:
wherein the replacement condition is based on a defect of the main signal processors due to at least one of an error and performance degradation of the main signal processors (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”; wherein the replacement condition is failure requiring a redundant ADC to replace the failed component).
Regarding claim 25, Guo teaches:
An apparatus comprising:
reception nodes configured to receive input signals of an analog domain (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”);
main signal processors configured to perform a signal processing operation on the input signals (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”);
However, Guo does not explicitly teach:
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation based on a defect of the main signal processors,
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single chip.
However, in the same field of endeavor, Fick teaches:
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation based on a defect of the main signal processors (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”),
wherein the reception nodes, the main signal processors, and the auxiliary signal processors are implemented in a single chip (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”; wherein a single chip can be interpreted as a single integrated circuit).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Guo by having the processors to be in a chip or an integrated circuit and replacing a failed main processor with an auxiliary when a replacement component meets a replacement condition, as taught by Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]).
Regarding claim 26, Guo teaches:
A method comprising:
receiving input signals of an analog domain (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”);
performing a signal processing operation on the input signals using main signal processors (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”);
However, Guo does not explicitly teach:
performing at least a portion of the signal processing operation using auxiliary signal processors instead of the main signal processors in response to a replacement condition being satisfied,
wherein the main signal processors and the auxiliary signal processors are implemented in a single integrated circuit (IC) package or a single chip.
However, in the same field of endeavor, Fick teaches:
performing at least a portion of the signal processing operation using auxiliary signal processors instead of the main signal processors in response to a replacement condition being satisfied (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”),
wherein the main signal processors and the auxiliary signal processors are implemented in a single integrated circuit (IC) package or a single chip (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”; wherein a single chip can be interpreted as a single integrated circuit).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Guo by having the processors to be in a chip or an integrated circuit and replacing a failed main processor with an auxiliary when a replacement component meets a replacement condition, as taught by Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]).
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Guo in view of Fick and further in view of Keren-Zvi.
Regarding claim 10, the Guo/Fick combination teaches all of the elements of claim 1. However, the Guo/Fick combination does not appear to teach:
wherein the auxiliary signal processors are configured to perform at least some of the signal processing operation in real-time instead of the main signal processors in response to the replacement condition being satisfied.
However, in the same field of endeavor, Keren-Zvi teaches:
wherein the auxiliary signal processors are configured to perform at least some of the signal processing operation in real-time instead of the main signal processors in response to the replacement condition being satisfied (Keren-Zvi: Fig. 3, #212n; Col. 6, lines 59-68, “The module controller in the agent module also notifies module controller 222.sub.N in spare module 212.sub.N of the failure of its client and sends the configuration of the signal processor of the failed module to spare module controller 222.sub.N via control bus 230. Module controller 222.sub.N configures signal processor 220.sub.N accordingly and causes fault monitor 224.sub.N to change switches 226a, 226b to position "3", thereby coupling signal processor 220.sub.N to auxiliary signal buses 218a, 218b so that spare module 212.sub.N replaces the failed module in the system”; wherein the module 212n including processors replaces the failed module with a mere flip of a switch and therefore the data will be processed real-time when the switch is flipped).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Guo/Fick combination by having the secondary processor to handle real-time processing during replacement, as taught by Keren-Zvi. One of ordinary skill in the art would have been motivated to use the methods of Keren-Zvi because it would improve redundancy of the system. (Keren-Zvi: Col. 1, lines 36-44).
Regarding claim 13, the Guo/Fick combination teaches all of the elements of claim 1. However, the Guo/Fick combination does not appear to teach:
at least one controller configured to determine whether the main signal processors satisfy the replacement condition based on a performance test of the main signal processors.
However, in the same field of endeavor, Keren-Zvi teaches:
at least one controller configured to determine whether the main signal processors satisfy the replacement condition based on a performance test of the main signal processors (Keren-Zvi: Col. 4, lines 7-20, “When signal processor 20.sub.2 fails to operate, fault monitor 24.sub.2 detects this failure and sets its status to indicate that processor 20.sub.2 is malfunctioning. Module controller 22.sub.2 learns of the failure by reading the status of fault monitor 24.sub.2 and sends a response to module controller 22.sub.1 indicating a fault status. Module controller 22.sub.2 also sends a set command to fault monitor 24.sub.2 to change its state from pass to fail and cause fault monitor 24.sub.2 to open primary switch 36 in module 12.sub.2. When module controller 22.sub.1 reads the response from controller 22.sub.2 indicating the fault, it closes the secondary switch 40 in module 12.sub.1. As a result, signals on line 14.sub.2 are diverted from failed module 12.sub.2, through secondary switch 40 in its partner module 12.sub.1, and onto auxiliary signal bus 18”; wherein a fault monitor is the controller in charge of detecting failure and wherein monitoring/detecting a failure is inherently a performance test).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Guo/Fick combination by having at least one controller determine that a main processor must be replaced based on a performance test, as taught by Keren-Zvi. One of ordinary skill in the art would have been motivated to use the methods of Keren-Zvi because it would improve redundancy of the system. (Keren-Zvi: Col. 1, lines 36-44).
Claims 17, 20, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Guo in view of Fick and further in view of Geva.
Regarding claim 17, the Guo/Fick combination teaches all of the elements of claim 1. However, the Guo/Fick combination does not appear to teach:
an electrode array measuring the input signal through electrodes disposed on a target point.
However, in the same field of endeavor, Geva teaches:
an electrode array measuring the input signal through electrodes disposed on a target point (Geva: Paragraph [0129], “The portable monitoring unit 110 is attached to a strip 132 that is worn around the neck of a monitored person 160. The portable monitoring unit 110 is coupled by electrodes to primary sensors 16, and communicated by short range transmission with secondary detectors 18 that are worn on a hand cuff 130 and a wristband 136”).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Guo/Fick combination by having electrodes measuring the raw input signal, as taught by Geva. One of ordinary skill in the art would have been motivated to use the methods of Geva because it would improve the ability to efficiently monitor biological vitals of a user. (Geva: Paragraphs [0002]-[0004]).
Regarding claim 20, the Guo/Fick/Geva combination teaches all of the elements of claim 17 and further teaches:
wherein, before the replacement condition is satisfied, the main signal processors are respectively connected to the electrodes (Geva: Paragraph [0129], “The portable monitoring unit 110 is attached to a strip 132 that is worn around the neck of a monitored person 160. The portable monitoring unit 110 is coupled by electrodes to primary sensors 16, and communicated by short range transmission with secondary detectors 18 that are worn on a hand cuff 130 and a wristband 136”; wherein the claim language broadly only specifies a signal processor being connected to electrodes before a replacement event).
Regarding claim 27, Guo teaches:
main signal processors configured to perform a signal processing operation comprising a digital conversion operation of corresponding input signals of the input signals, respectively, (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”) and
auxiliary signal processors configured to replace the main signal processors and perform at least a portion of the signal processing operation including the digital conversion operation (Guo: Fig. 1a, #15 and #16; Fig. 5, #153 and #155; Paragraph [0038], “As shown in FIG. 1b and FIG. 1c, the first processing module 15 includes a first decoder 151, a first scrambler 152, and a first digital-to-analog conversion circuit 153, which are connected in sequence, and the second processing module 16 includes a second decoder 161, a second scrambler 162, and a second digital-to-analog conversion circuit 163 which are connected in sequence”; and Paragraph [0055], “As shown in FIG. 5, based on the embodiment shown in FIG. 1b, the first processing module 15 further includes: [0056] a redundant logic unit 154, connected to the first scrambler 152 and the first digital-to-analog conversion circuit 153, and configured to perform redundant logic processing according to a conversion control signal output by the first scrambler 152, and output a conversion control signal and a redundant control signal, where the conversion control signal and the redundant control signal are redundant to each other; and [0057] a redundant digital-to-analog conversion circuit 155, connected to the redundant logic unit 154 and the first digital-to-analog conversion circuit 153, and configured to perform digital-to-analog conversion according to the redundant control signal, so as to obtain a redundant analog signal”)
However, Guo does not appear to teach:
in response to a replacement condition being satisfied.
However, in the same field of endeavor, Fick teaches:
in response to a replacement condition being satisfied (Fick: Paragraph [0071], “Due to yield issues often arising from fabrication defects, the integrated circuit 100 may be implemented with redundant ADCs to account for failure. In one or more specific implementations, column redundancy may be implemented enabling a replacement of an entire ADC in case of failure”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Guo replacing a failed main processor with an auxiliary when a replacement component meets a replacement condition, as taught by Fick. One of ordinary skill in the art would have been motivated to use the methods of Fick because it would continuously improve operation efficiency. (Fick: Paragraphs [0050]-[0051]).
However, the Guo/Fick combination does not appear to teach:
A biologic response recording apparatus comprising:
a measuring instrument comprising:
an electrode array configured to generate input signals corresponding to data measured at target points through electrodes disposed on the target points,
a memory configured to store response data output by at least some of the main signal processors and the auxiliary signal processors.
However, in the same field of endeavor, Geva teaches:
A biologic response recording apparatus comprising:
a measuring instrument (Geva: Pargraph [0127], “The sensor interface 50 can include an operational amplifier 50(1) that receives detection signals from one or more primary and/or secondary sensors, a filter 50(2) and an analog to digital converter 50(3). The output of the analog to digital converter 50(3) provides raw medical data. Alternatively, the output of the analog to digital converter 50(3) can be sampled and/or additionally processed to provide the raw medical data”) comprising:
an electrode array configured to generate input signals corresponding to data measured at target points through electrodes disposed on the target points (Geva: Paragraph [0129], “The portable monitoring unit 110 is attached to a strip 132 that is worn around the neck of a monitored person 160. The portable monitoring unit 110 is coupled by electrodes to primary sensors 16, and communicated by short range transmission with secondary detectors 18 that are worn on a hand cuff 130 and a wristband 136”),
a memory configured to store response data output by at least some of the main signal processors and the auxiliary signal processors (Geva: Parargaph [0135], “The raw medical information can be received in a continuous manner, in intervals, or in any other manner. The reception can include receiving raw medical information from one or more sensors, storing the raw medical information in a memory module and retrieving the raw medical information from the memory module”; wherein Geva teaches storing raw medical data from the analog to digital converter and is combined with Fick/Guo’s redundant processors).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Guo/Fick combination by having electrodes to measure biological data and storing the responses, as taught by Geva. One of ordinary skill in the art would have been motivated to use the methods of Geva because it would assist in efficiently detecting potential events. (Geva: Paragraphs [0004]-[0005]).
Allowable Subject Matter
Claims 5 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 6-8, 11-12, 15, 18-19, and 21-24 are rejected under non-art rejections as well as being objected to for being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims as well as rewritten to overcome non-art rejections.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 5 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
wherein a first main signal processor of the main signal processors receives a first input signal of the input signals from a first reception node of the reception nodes, a first MUX of the MUXs connects the first reception node to a first auxiliary signal processor of the auxiliary signal processors in response to the replacement condition is satisfied as a defect occurs in the first main signal processor.
As to claim 6 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
6. The apparatus of claim 1, wherein the single IC package comprises at least one die in which the reception nodes, the main signal processors, and the auxiliary signal processors are integrated in at least a partial form of a stack package and a system in package.
As to claim 7 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
7. The apparatus of claim 1, wherein the input signals are received through 10 or more channels.
As to claim 8 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
8. The apparatus of claim 1, wherein the input signals are received through 10,000 or more channels.
As to claim 11 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
11. The apparatus of claim 1, wherein the main signal processors are divided in a predetermined first number and constitute a plurality of slots, and
the auxiliary signal processors are divided in a predetermined second number and dedicatedly and respectively allocated to the plurality of slots.
As to claim 12 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
12. The apparatus of claim 1, wherein the main signal processors are divided in a predetermined first number and constitute a plurality of slots, and
the auxiliary signal processors are allocated to the plurality of slots such that a predetermined third number of slots of the plurality of slots share at least some of the auxiliary signal processors.
As to claim 14 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
14. The apparatus of claim 13, wherein the at least one controller is further configured to provide a test signal to the main signal processors while connection between the reception nodes and the main signal processors is open and determine whether the main signal processors satisfy the replacement condition by analyzing each processing result of the main signal processors for the test signal.
As to claim 15 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
15. The apparatus of claim 13, wherein the at least one controller is further configured to, when a plurality of replacement targets satisfying the replacement condition among the main signal processors is detected, determine a replacement priority of the replacement targets based on a degree of defect due to at least one of an error and performance degradation of the replacement targets, and apply the auxiliary signal processors in order of high replacement priority.
As to claim 18 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
18. The apparatus of claim 17, further comprising:
multiplexers (MUXs) connecting candidate electrodes of the electrodes to corresponding auxiliary signal processors of the auxiliary signal processors.
As to claim 21 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
21. The apparatus of claim 17, wherein the electrodes comprise main electrodes connected to the main signal processors and auxiliary electrodes connected to the auxiliary signal processors, and
the electrode array is configured to measure the input signals using the main electrodes and the auxiliary electrodes.
As to claim 24 it contains allowable subject matter when the claim is taken as a whole. See the italicized/bolded/underlined text indicating aspects that in combination with the remainder of the claim differentiate it from prior art:
24. The apparatus of claim 17, wherein the main signal processors comprise first main signal processors selectively connected to each electrode of a first electrode group among the electrodes,
the auxiliary signal processors comprise first auxiliary signal processors selectively connected to each electrode of the first electrode group, and
some of the first main signal processors and the first auxiliary signal processors selected in order from a high performance level to a low performance level are applied to the first electrode group.
Claims 19 and 22-23 are dependent upon allowable claims 18 and 21, respectively. Therefore, claims 19 and 22-23 contain allowable subject matter by the virtue of dependency.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US 20240159819 A1, US 20230160934 A1, US 20190282115 A1, US 20180359566 A1, US 20100290164 A1, US 7573416 B1, US 5496349 A, US 5319370 A). The following statement is a brief summary of very pertinent art that was not relied upon:
US 20240159819 A1: Error detection or error reduction action may be performed based on the result of the self-testing process. For example, a redundant sensor may be used to replace a faulty primary sensor after identifying a faulty primary sensor. As another example, if an input channel is determined to be defective, depending on the application and safety requirements, the system 100 may perform the self-testing again at a later time to determine if the error in the input channel is temporary, may stop driving the load at the corresponding output channel, or may instruct the system 100 to enter a safe mode once defect is detected in the input channels.
US 20230160934 A1: Furthermore, a secondary load-sensing subsystem 100′ (FIG. 2) that is similar to the current sensor 102 and signal conditioning and amplification circuit 104 may be provided to monitor and/or sense current in the AC load line that provides electrical power to the medical equipment 112, to determine whether the medical equipment 112 is powered on and requires monitoring or whether the medical equipment 112 is powered off and therefore does not need monitoring. The sensing element (core and conductor coil loops) of the secondary load-sensing subsystem 100′ are sized/designed in view of the anticipated AC loads for powering the medical equipment 112, as are the components of the signal conditioning and amplification circuitry of the secondary system (i.e., op-amps, resistors, capacitors, and diodes). Output signal 108′ of the secondary subsystem 100′ will also be provided to an analog-to-digital converter (not illustrated), the output of which is processed via the processor 106—along with the output of the system 100—as part of the process for assessing the integrity of the ground connection conductor 122, as addressed more fully below.
US 20190282115 A1: In certain implementations of the above ECG signal processing system, conditioning the secondary ECG signal lead includes at least one of performing noise filtering, performing signal amplification, and performing analog to digital conversion on the secondary ECG signal lead.
US 20180359566 A1: In accordance with an embodiment of the disclosure, the audio module 304 can include a primary audio processor 402, an intermediate audio processor 404 and a secondary audio processor 406. In accordance with another embodiment of the disclosure, audio module 304 can further include a wireless communication module 408, an analog to digital converter (ADC) 410 and one or more digital to analog converters (DAC) 412. In accordance with yet another embodiment of the disclosure, the audio module 304 can yet further include one or both of a wireless audio module 414 and a multiplexer 416.
US 20100290164 A1: During first predetermined time interval T1, controller 38 inactivates grounded neutral fault detector circuit 16a, drive signal V.sub.ac is zero and load current I.sub.ac is zero. Thus, the output of buffer/amp 30 is the monitored secondary current I.sub.s, which is coupled to input terminal IN1 on MUX 32. Controller 38 provides a control signal to MUX 32 to select the IN1 input as the output of MUX 32. ADC 34 samples the buffered (or amplified) secondary current I.sub.s signal and provides a digital count corresponding to secondary current I.sub.s to processor 36. Processor 36 may be a conventional microprocessor integrated circuit, or other similar processor. Alternatively, ADC 34 and processor 36 may be combined into a single device that includes a microprocessor and analog-to-digital converter, such as such as an ATTINY461A microcontroller by Atmel Corporation, San Jose, Calif., or a MSP430s microcontroller by Texas Instruments Incorporated, Dallas, Tex. Processor 36 processes the converted I.sub.s data to determine if ground leakage current I.sub.L2G exceeds the first predetermined threshold.
US 7573416 B1: The circuit may be further characterized by the first control signal being a low power mode signal provided by a processor. The circuit may further comprise an analog-to-digital converter having a reference voltage input terminal for receiving at least one reference voltage from the reference voltage generating circuit. The circuit may be further characterized by the analog-to-digital converter being a redundant signed division analog-to-digital converter. The circuit may be further characterized by the reference voltage generating circuit comprising a plurality of series-connected resistive elements. The circuit may further comprise a precharge circuit coupled to the first terminal of the second switch, the precharge circuit for precharging the capacitive element to a predetermined voltage in response to a mode control signal. The circuit may be further characterized by the second control signal being provided in response to setting a register bit field of a processor. The circuit may be further characterized by the circuit being implemented as a portion of an integrated circuit and the capacitive element is external to the integrated circuit. The circuit may be further characterized by the second control signal being an active mode control signal.
US 5496349 A: The amplified and filtered analog signal is conducted to an analog to digital converter (A/D converter) 103. When the A/D converter 103 receives a conversion strobe from a main processor 104, the A/D converter 103 converts the analog voltage from the signal processing unit 102 into a digital representation that it makes available on its data bus to both the main processor 104 and an auxiliary processor 105. The conversion strobe preferably occurs every 10 milliseconds. The A/D converter 103 may output its data in either parallel or serial format. If the data is output in serial format, a shift register (not shown) is interposed between the A/D converter 103 and the processors 104, 105 to convert serial data from the A/D converter 103 to parallel data for input to each processor. The processors 104, 105, as well as other high voltage components such as the power supply, are separated from the rest of MPD by an isolation barrier 109, designed to protect the patient from unintended dangerous voltages. Both processors 104, 105 read the digital representation from the output generated the A/D converter 103, called a sample, and incorporate it in their analyses. Throughout their analyses, the processors 104, 105 communicate via a communication link (link) to assure that they are operating correctly. The link is preferably an RS-232 line. Both processors 104, 105 periodically transmit a signal to the other processor indicating that the processor is operating properly. If either processor 104, 105 fails to receive such a signal from the other processor for a period of time exceeding a signaling threshold, the processor that did not receive a signal enters a DISABLED STATE (described below), in which the MPD cannot continue normal operation. If the analysis of the main processor 104 reaches a tentative treat result, both processors 104, 105 together trigger a charging circuit 107 in the treatment subsystem 106, causing it to begin accumulating a charge. If the processors agree throughout their analyses and both reach a final treat result, the MPD either defibrillates the patient (in the case of an automatic defibrillator) or advises an operator to manually initiate defibrillation (in the case of a semi-automatic defibrillator). In either case, both processors 104, 105, trigger a delivery circuit 108 of the treatment subsystem, causing the delivery circuit 108 to deliver the charge accumulated in the treatment subsystem 106 to the patient via the dual-purpose electrodes. Both processors 104, 105 must signal the delivery circuit for it to deliver the charge accumulated in the treatment subsystem 106 to the patient. If the analyses of the processors 104, 105 diverge at any point, either the main processor 104 or the auxiliary processor 105 triggers an internal discharge function of the treatment subsystem 106, causing it to dissipate the accumulated charge by discharging it internally. Because processor analysis divergence implicates the failure of one of the processors 104, 105, the MPD further disables itself pending service. The MPD further includes an analyze button switch (not shown) and, in the case of a semi-automatic defibrillator, a deliver button switch (not shown), which each generate a signal that is made available to both processors 104, 105 to cause the processors to trigger the delivery circuit 108.
US 5319370 A: The primary analog-to-digital converter 11 is a successive approximation type converter. It consists of a charge redistribution digital-to-analog converter (DAC) 24 with the digital output thereof connected to a comparator 26 to provide a digital output. An analog signal multiplexor 28 is operable to receive the analog input voltage V.sub.IN, a ground voltage V.sub.GND and the voltage V.sub.TRIM. The voltage V.sub.TRIM is output from the trim circuit 14 and from the chip such that this voltage is provided external to the circuit. This is then tied back into the input of the analog multiplexer 28. The output of the analog multiplexer 28 is input to the charge redistribution DAC 24. This converter is substantially the same type that is disclosed in U.S. Pat. No. 4,709,225, entitled Self-Calibration Method for Capacitors in a Monolithic Integrated Circuit, which patent is incorporated herein by reference. As will be described hereinbelow, the reference block 10 includes a secondary analog-to-digital converter that is utilized to continuously monitor the voltage reference 12 and provide a trimming operation. This secondary converter is utilized in order to maximize the throughput of the primary converter because it now does not have to monitor the reference voltage while it converts the external analog input signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Matthew N Putaraksa whose telephone number is (303)297-4365. The examiner can normally be reached on Monday-Thursday 7:00am-5:00pm MT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matt Kim can be reached on 571-272-4182. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MATTHEW N PUTARAKSA/Examiner, Art Unit 2114
Prosecution Insights