DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2019/0206877).
[claim 1] A semiconductor device (figs. 2, 3A, 3B, 3C) comprising: a substrate (100, fig. 3A) including a cell active region (e.g. 112a, 112b, fig. 3A,3B, 3C); a word line (WL, LC, fig. 3A) on the cell active region, the word line including a gate electrode (BE, fig. 3A, [0023]), a gate intervening pattern (UE, fig. 3A, [0023]) on the gate electrode, and a gate capping pattern (117, fig. 3A, [0026]) on the gate intervening pattern, wherein the gate intervening pattern is disposed between the gate electrode and the gate capping pattern (fig. 3A); a bit line (BL, fig. 3C) electrically connected to the cell active region (to 112a, fig. 3C); a connection structure (LC, fig. 3A optionally the connection structure could only be 151) in the word line and extending through the gate intervening pattern, the connection structure and the gate electrode including different materials from each other (see [0023] for BE gate electrode material which may be titanium, and LC materials are shown in [0047] which can be TaN); and a word line contact plug (196, fig. 3A optionally 152 could also be part of the plug) in contact with the connection structure.
[claim 2] The semiconductor device as claimed in claim 1, wherein a level of a top surface of the connection structure is higher than a level of a top surface of the gate electrode (fig. 3A).
[claim 3] The semiconductor device as claimed in claim 1 further comprising a boundary device isolation pattern (102,191, fig. 3A) on the substrate wherein a level of a top surface of the gate capping pattern is lower than a level of a topmost surface of the boundary device isolation pattern (fig. 3A).
[claim 4] The semiconductor device as claimed in claim 3, wherein a level of a bottom surface of the word line contact plug is lower than a level of a top surface of the gate intervening pattern (if 152 is part of word line contact plug, fig. 3A) and is higher than a level of a top surface of the gate electrode (fig. 3A).
[claim 5] The semiconductor device as claimed in claim 3, the word line contact plug passes through the gate capping pattern (fig. 3A).
[claim 6] The semiconductor device as claimed in claim 3, wherein: a side surface of the connection structure is in contact with a side surface of the gate intervening pattern (fig. 3A), and a top surface of the connection structure is in contact with the gate capping pattern (if the gate capping pattern also includes 101, 153, 193, and 194, fig. 3A).
[claim 7] The semiconductor device as claimed in claim 1, wherein a lattice constant of the connection structure is different from a lattice constant of the gate electrode (e.g. gate electrode BE may be polysilicon [0023] while 151 of the connection structure may be a metal nitride [0047]).
[claim 8] The semiconductor device as claimed in claim 1, wherein: the word line further includes a gate dielectric pattern (115,102, fig. 3A) between the gate electrode and the cell active region, and a side surface of the connection structure is in contact with the gate dielectric pattern (fig. 3A).
[claim 9] The semiconductor device as claimed in claim 1 wherein the gate electrode and the connection structure to have an interface defined therebetween (fig. 3A).
[claim 10] The semiconductor device as claimed in claim 1, further comprising a cell active pattern (items such as 112a/112b, fig. 3A, 3B, 3C), on the substrate and a boundary device isolation pattern (102, fig. 3A, 3B, 3C) defining the cell active pattern, wherein the connection structure does not overlap the cell active pattern (see fig. 3A where 151 is not above source, drain, channel area, etc.).
[claim 19] A semiconductor device (fig. 2, 3A, 3B, 3C), comprising: a substrate (100, fig. 3A) including a cell region (e.g. 112a, 112b in CAR region, fig.2, 3A,3B, 3C), a peripheral region (PCR region to the right of LC, fig. 2), and a boundary region (portion between the right side of LC and left side of the first active region 112a or 112b in the CAR region, fig. 2, 3A) between the cell region and the peripheral region; a cell active pattern on the boundary region (fig. 2, 3A); a boundary device isolation pattern (102, fig. 3A, 3B, 3C) defining the cell active pattern; a word line (WL, fig. 3A) on the cell active pattern; a connection structure (LC, fig. 3A optionally only 151 can be the connection structure; a word line contact plug (196, fig. 3A, optionally 152 could also be part of the plug) connected to the connection structure; and an interlayer insulating layer (194, fig. 3A) enclosing the word line contact plug, wherein the word line includes: a gate dielectric pattern (115,117 fig. 3A, 3B) on the cell active pattern, a gate electrode (BE, fig. 3A) on the gate dielectric pattern, a gate intervening pattern (UE, fig. 3A) on the gate electrode, and a gate capping pattern (101, fig. 3A) on the gate intervening pattern, wherein the gate intervening pattern is disposed between the gate electrode and the gate capping pattern (fig. 3A), wherein the connection structure extends through the gate intervening pattern and electrically connects the gate electrode to the word line contact plug (fig. 3A), the connection structure and the gate electrode including different materials from each other (see [0023] for BE gate electrode material which may be TaN or TiN, and LC materials are shown in [0047] which can be Ta or Ti), and the connection structure and the gate electrode having an interface defined therebetween (fig. 3A), and wherein a side surface of the connection structure is in contact with the gate dielectric pattern (117 contacts the side of the connection structure, fig. 3A).
[claim 20] The semiconductor device as claimed in claim 19, wherein the connection structure has an electric conductivity higher than an electric conductivity of the gate electrode (gate electrode BE is a metal nitride while connection structure LC may be a metal).
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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