DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (claims 1-10 and 19-20) in the reply filed on 3-31-2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 and 6-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo (US 2002/0149958) in view of Kim (US 2002/0081799).
[claim 1] Kunikiyo discloses a semiconductor device, comprising: a substrate (1, fig. 3) including a cell active region (81-84, 701,712,723,734,745, fig. 3, [0135]); a word line (WLa, 9, 13, fig. 3,2 [0137]) on the cell active region, the word line including a gate electrode (9, fig. 3, [0137]); a bit line (bit lines connect to 701,712,723,734,734,745, fig. 3, [0134]) electrically connected to the cell active region; a connection structure (13, fig. 3, [0137] which may be made of a metal [0139]) in the word line and on the gate electrode. Kunikiyo, however, does not expressly disclose the material of the gate electrode.
Kim discloses a semiconductor device wherein the gate electrode (15, 17 fig. 6) is made of a polysilicon layer (15, fig. 6, [0027]) with a silicide layer (17, fig. 6, [0027] thereon.
It is obvious to one of ordinary skill in the art before the time of filing to made Kunikiyo’s gate electrode out of polysilicon layer with a silicide layer thereon in order to provide a material (polysilicon) that is low cost, allows for high temperature processing, and is work function tunable and a silicide layer thereon to form an ohmic contact with the metal thereon.
With this modification Kunikiyo discloses:
[claim 1] the connection structure and the gate electrode including different materials (the connection structure 13 is made of a metal [0139] while gate electrode 9 upon modification is made of polysilicon); a word line contact plug (14, fig. 3, [0137]) in contact with the connection structure.
[claim 2] The semiconductor device as claimed in claim 1, wherein a level of a top surface of the connection structure is higher than a level of a top surface of the gate electrode (fig. 3).
[claim 3] The semiconductor device as claimed in claim 1, further comprising a boundary device isolation pattern (12, fig. 3, 12 isolates word line contacts of the various devices ) on the substrate, wherein the word line further includes a gate intervening pattern (the silicide layer that sits on the polysilicon layer of the gate electrode 9 upon modification, fig. 3) on the gate electrode and a gate capping pattern (11, fig. 3) on the gate intervening pattern, and wherein a level of a top surface of the gate capping pattern is lower than a level of a topmost surface of the boundary device isolation pattern (fig. 3).
[claim 6] The semiconductor device as claimed in claim 3, wherein: a side surface of the connection structure is in (electrical) contact with the gate intervening pattern, and a top surface of the connection structure is in contact with the gate capping pattern (corner of the top surface of connection structure 13 is in contact with gate capping pattern 11, fig. 3).
[claim 7] The semiconductor device as claimed in claim 1, wherein a lattice constant of the connection structure is different from a lattice constant of the gate electrode (inherent as the connection structure is made of metal and the gate electrode is polysilicon).
[claim 8] The semiconductor device as claimed in claim 1, wherein: the word line further includes a gate dielectric pattern (5, fig. 3) between the gate electrode and the cell active region, and a side surface of the connection structure is in (electrical) contact with the gate dielectric pattern.
[claim 9] The semiconductor device as claimed in claim 1, wherein the gate electrode and the connection structure are provided to have an interface defined therebetween (either the silicide could be interface or if it is omitted there would be a direct interface, fig. 3).
[claim 10] The semiconductor device as claimed in claim 1, further comprising a cell active pattern (81,82,83,84, fig. 3) on the substrate and a boundary device isolation pattern (e.g. 601, 612, 123, 634, 645, fig. 3) defining the cell active pattern, the connection structure not overlapping the cell active pattern (fig. 3).
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo (US 2002/0149958) in view of Kim (US 2002/0081799).
Kunikiyo/Kim disclose the semiconductor device in claim 3 but does not expressly discloses a shape of the connection structure and the word line plug such that both elements penetrate the gate intervening pattern but not the gate electrode.
Nevertheless it would have been obvious to have made the shape a of the connection structure and the word line plug such that both elements penetrate the gate intervening pattern but not the gate electrode, since it has been held that a particular shape configuration was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
With this modification Kunikiyo discloses:
[claim 4] The semiconductor device as claimed in claim 3, wherein a level of a bottom surface of the word line contact plug is lower than a level of a top surface of the gate intervening pattern and is higher than a level of a top surface of the gate electrode (upon modification).
[claim 5] The semiconductor device as claimed in claim 3, wherein: the connection structure penetrates the gate intervening pattern (upon modification), and the word line contact plug penetrates the gate capping pattern (upon modification).
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kunikiyo (US 2002/0149958) in view of Kim (US 2002/0081799).
[claim 19] Kunikiyo discloses a semiconductor device (fig. 1-3), comprising: a substrate (1, fig. 3) including a cell region (whole cell array except last cell before peripheral area fig. 2), a peripheral region (region adjacent to last cell in the array along the word line connection, see also [0038]), and a boundary region (last cell in the array before peripheral area, fig. 2) between the cell region and the peripheral region; a cell active pattern (81-84, 701,712,723,734,745, fig. 3, [0135]) on the boundary region; a boundary device isolation pattern (601, 612, 623, 634, 645, fig. 3)defining the cell active pattern; a word line (WLa, 9, fig. 3,2 [0137]) on the cell active pattern; a connection structure (13, fig. 3); a word line contact plug (14, fig. 3) connected to the connection structure; and an interlayer insulating layer (12, fig. 3) enclosing the word line contact plug, wherein the word line includes: a gate dielectric pattern (5, fig. 3) on the cell active pattern, a gate electrode (9, fig. 3) on the gate dielectric pattern. Kunikiyo, however, does not expressly disclose the material of the gate electrode.
Kim discloses a semiconductor device wherein the gate electrode (15, 17 fig. 6) is made of a polysilicon layer (15, fig. 6, [0027]) with a silicide layer (17, fig. 6, [0027] thereon.
It is obvious to one of ordinary skill in the art before the time of filing to made Kunikiyo’s gate electrode out of polysilicon layer with a silicide layer thereon in order to provide a material (polysilicon) that is low cost, allows for high temperature processing, and is work function tunable and a silicide layer thereon to form an ohmic contact with the metal thereon.
With this modification Kunikiyo discloses:
[claim 19] a gate intervening pattern (the silicide on the polysilicon gate electrode upon modification) on the gate electrode, and a gate capping pattern on the gate intervening pattern, wherein the connection structure electrically connects the gate electrode to the word line contact plug (fig. 3), the connection structure and the gate electrode including different materials from each other (the connection structure 13 is made of a metal [0139] while gate electrode 9 upon modification is made of polysilicon), and the connection structure and the gate electrode having an interface defined therebetween (with an interface layer between 13 and 9, fig. 3), and wherein a side surface of the connection structure is in (electrical) contact with the gate dielectric pattern.
[claim 20] The semiconductor device as claimed in claim 19, wherein the connection structure has an electric conductivity higher than an electric conductivity of the gate electrode (the connection structure 13 is made of a metal [0139] while gate electrode 9 upon modification is made of polysilicon which has lower conductivity than a metal).
Conclusion
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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