DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 9/1/2023.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/9/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-10, 13-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPGPUB 2012/0105569 (“Ono”).
As per claim 1, Ono substantially teaches an apparatus (Ono, FIG. 2A) comprising:
a multi-level cache memory; and a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. Ono therefore substantially teaches a multi-level cache memory; and a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level).
As per claim 2, the rejection of claim 1 is incorporated, and Ono further substantially teaches:
wherein the core-side predictor including a predictor table, the predictor table including a predictor table entry, the predictor table entry including a cache hit counter and a cache accesses counter for the instruction pointer in the cache level of the multi-level cache memory: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040 and 0042-0043, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. The Examiner further notes that the system of Ono may use an array (i.e., a table) of entries that comprises counters associated with program counters (i.e., instruction pointers) for tracking cache hits and cache misses (i.e., a cache hit counter and a cache access counter). Ono therefore substantially teaches wherein the core-side predictor including a predictor table, the predictor table including a predictor table entry, the predictor table entry including a cache hit counter and a cache accesses counter for the instruction pointer in the cache level of the multi-level cache memory).
As per claim 3, the rejection of claim 2 is incorporated, and Ono further substantially teaches:
wherein the core-side predictor include predictor circuitry, the predictor circuitry to divide a number of cache hits stored in the cache hit counter by a number of cache accesses stored in the cache accesses counter to provide a result, the predictor circuitry to output a miss prediction if the result is less than a threshold value and to output a hit prediction if the result is greater than the threshold value: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040 and 0042-0043, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. The Examiner further notes that the system of Ono may use an array (i.e., a table) of entries that comprises counters associated with program counters (i.e., instruction pointers) for tracking cache hits and cache misses (i.e., a cache hit counter and a cache access counter). In order to make a prediction as to whether a given cache access request will likely hit or likely miss in L1 cache, core pipeline 206 may calculate a ratio of cache misses to cache hits to calculate a resulting value that is then compared to a threshold to determine whether to predict a cache hit or a cache miss in L1 cache for the given cache access request. In other words, a value of cache hits (tracked by the cache hit counter associated with the program counter value of the given instruction) may be divided by the number of cache misses (tracked by the cache miss counter associated with the program counter value of the given instruction) to generate a result that is then compared to a threshold in order to determine whether to predict a cache hit or a cache miss. The Examiner notes that the example given in (Ono, paragraphs 0034-0035) describes comparing a ratio of cache misses to cache hits for a given program counter in order to determine whether to predict a cache hit or a cache miss and then does not send a speculative access request to lower-level cache (i.e., predicts a hit in L1 cache) when the ratio of cache misses to cache hits is less than a threshold ratio of 0.5 (i.e., there are fewer cache misses than cache hits); conversely, simple logic states that when the ratio of cache hits to cache misses is greater than the threshold value of 0.5, the number of cache hits is greater than the number of cache misses, and a cache hit would be predicted. Ono therefore substantially teaches wherein the core-side predictor include predictor circuitry, the predictor circuitry to divide a number of cache hits stored in the cache hit counter by a number of cache accesses stored in the cache accesses counter to provide a result, the predictor circuitry to output a miss prediction if the result is less than a threshold value and to output a hit prediction if the result is greater than the threshold value).
As per claim 6, the rejection of claim 1 is incorporated, and Ono further substantially teaches:
wherein the multi-level cache memory has four levels, the cache level is level four cache: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. As evidenced by the attached non-patent literature definition of “cache,” which is not relied upon by the Examiner for any rejection but is merely and only provided as evidence, “cache” may refer to “a computer memory with very short access time used for storage of frequently or recently used instructions or data.” Since the memory of Ono is used to store instructions or data that are frequently used, such as in a working set of memory, the memory of Ono may be considered to be a last-level cache. Since the multi-level cache memory of Ono has three explicitly numbered levels, the last-level cache (i.e., the memory) would be an L4 cache. Ono therefore substantially teaches wherein the multi-level cache memory has four levels, the cache level is level four cache).
As per claim 7, the rejection of claim 6 is incorporated, and Ono further substantially teaches:
wherein the level four cache is embedded Dynamic Random Access Memory (eDRAM) or Static Random Access Memory (SRAM): (Ono, Abstract; and paragraph 0023, where the caches of the multi-level caching system of Ono, including the memory (i.e., the L4 cache), may be embodied as Dynamic Random Access Memory (DRAM) or SRAM. The Examiner notes that when the multi-level caching system of Ono uses DRAM as the memory (i.e., the L4 cache), the DRAM is embedded within computing device 200 and is thus an embedded DRAM. Ono therefore substantially teaches wherein the level four cache is embedded Dynamic Random Access Memory (eDRAM) or Static Random Access Memory (SRAM)).
As per claim 8, Ono substantially teaches a system (Ono, FIG. 2A) comprising:
a memory; and a System-on-Package communicatively coupled to the memory, the System-on-Package comprising: a multi-level cache memory; and a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access the memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies an instruction and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. The Examiner further notes that the apparatus illustrated in (Ono, FIG. 2A) is a multi-core processor 202 system that is packaged within computing device 200 and is thus a system-on-package that communicates with memory. Ono therefore substantially teaches a memory; and a System-on-Package communicatively coupled to the memory, the System-on-Package comprising: a multi-level cache memory; and a core, the core including a core-side predictor, the core-side predictor to track a hit rate for an instruction pointer in a cache level of the multi-level cache memory to predict a cache miss in the cache level, the core to directly access the memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level).
As per claim 9, the rejection of claim 8 is incorporated, and the Examiner notes that the language of claim 9 is substantially similar to the language of claim 2. The Examiner therefore rejects claim 9 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 2.
As per claim 10, the rejection of claim 9 is incorporated, and the Examiner notes that the language of claim 10 is substantially similar to the language of claim 3. The Examiner therefore rejects claim 10 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 3.
As per claim 13, the rejection of claim 8 is incorporated, and the Examiner notes that the language of claim 13 is substantially similar to the language of claim 6. The Examiner therefore rejects claim 13 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 6.
As per claim 14, the rejection of claim 13 is incorporated, and the Examiner notes that the language of claim 14 is substantially similar to the language of claim 7. The Examiner therefore rejects claim 14 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 7.
As per claim 15, Ono substantially teaches a method (Ono, FIG. 2A and FIG. 3) comprising:
tracking, by a core-side predictor in a core, a hit rate for an instruction pointer in a cache level of a multi-level cache memory to predict a cache miss in the cache level; and directly accessing, by the core, a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level: (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0030-0040, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. Ono therefore substantially teaches tracking, by a core-side predictor in a core, a hit rate for an instruction pointer in a cache level of a multi-level cache memory to predict a cache miss in the cache level; and directly accessing, by the core, a memory and the cache level of the multi-level cache memory in parallel based on a prediction that the cache miss is likely in the cache level).
As per claim 16, the rejection of claim 15 is incorporated, and the Examiner notes that the language of claim 16 is substantially similar to the language of claim 2. The Examiner therefore rejects claim 16 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 2.
As per claim 17, the rejection of claim 16 is incorporated, and the Examiner notes that the language of claim 17 is substantially similar to the language of claim 3. The Examiner therefore rejects claim 17 using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 3.
As per claim 20, the rejection of claim 15 is incorporated, and Ono further substantially teaches:
wherein the multi-level cache memory has four levels, the cache level is level four cache, the level four cache is embedded Dynamic Random Access Memory (eDRAM) or Static Random Access Memory (SRAM): (Ono, Abstract; FIG. 2A, reference numerals 202, 204, 206, 210, 212, 216, 220, 222, 224, and component labeled “MEMORY”; and paragraphs 0023 and 0030-0040, where the system of Ono comprises multi-core processor 202 that comprises both processor core 204 (i.e., a core), L1 data cache 210, L2 cache 212, shared L3 cache 216, and memory (i.e., a multi-level memory hierarchy comprising multiple levels of cache). Core pipeline 206 predicts whether a received access request (e.g., load request 220) is likely to hit or miss in L1 data cache 210 based on a comparison of counter values maintained by core pipeline 206; based on the comparison of counter values, core pipeline 206 sends speculative access requests to lower levels of the multi-level memory hierarchy (e.g., L2 cache 212, shared L3 cache 216, and memory) in parallel with sending the received access request to L1 cache 210. The Examiner notes that core pipeline 206 identifies instructions and associated counters by referencing the instruction’s program counter (i.e., instruction pointer) and is thus a core-side predictor that tracks a hit rate and predicts cache hits and cache misses based on an instruction pointer counter associated with a given cache level. As evidenced by the attached non-patent literature definition of “cache,” which is not relied upon by the Examiner for any rejection but is merely and only provided as evidence, “cache” may refer to “a computer memory with very short access time used for storage of frequently or recently used instructions or data.” Since the memory of Ono is used to store instructions or data that are frequently used, such as in a working set of memory, the memory of Ono may be considered to be a last-level cache. Since the multi-level cache memory of Ono has three explicitly numbered levels, the last-level cache (i.e., the memory) would be an L4 cache. In addition, (Ono, Abstract; and paragraph 0023) teaches where the caches of the multi-level caching system of Ono, including the memory (i.e., the L4 cache), may be embodied as Dynamic Random Access Memory (DRAM) or SRAM. The Examiner notes that when the multi-level caching system of Ono uses DRAM as the memory (i.e., the L4 cache), the DRAM is embedded within computing device 200 and is thus an embedded DRAM. Ono therefore substantially teaches wherein the multi-level cache memory has four levels, the cache level is level four cache, the level four cache is embedded Dynamic Random Access Memory (eDRAM) or Static Random Access Memory (SRAM)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5, 11-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2012/0105569 (“Ono”) in view of U.S. Patent No. 7,930,485 (“Fertig”).
As per claim 4, the rejection of claim 3 is incorporated, but Ono does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Fertig teaches speculative memory prefetch.
As per claim 4, Fertig particularly teaches:
wherein the cache hit counter and the cache accesses counters are free running, the number of cache accesses stored in the cache accesses counter and the number of cache hits stored in the cache hit counter divided by a same number prior to overflow of the cache accesses counter: (Fertig, Abstract; FIG. 5; column 8, lines 31-49; and column 9, lines 7-61, where the system of Fertig uses counters that run with each incoming cache access, hit, and miss and are reset prior to overflowing the maximum value set by the number of bits used by the counters. Fertig therefore particularly teaches wherein the cache hit counter and the cache accesses counters are free running, the number of cache accesses stored in the cache accesses counter and the number of cache hits stored in the cache hit counter divided by a same number prior to overflow of the cache accesses counter).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Fertig and Ono before them before the instant application was effectively filed, to modify the system of Ono to include the principles of Fertig of implementing counters for cache accesses, hits, and misses and resetting the respective values of the counters prior to overflow of the counters.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance by implementing techniques to enable management of cache prefetch request predictions with a desired degree of certainty in order to reduce or eliminate needless prefetch requests (Fertig, column 6, line 52, to column 6, line 4).
As per claim 5, the rejection of claim 3 is incorporated, but Ono does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Fertig teaches speculative memory prefetch.
As per claim 5, Fertig particularly teaches:
wherein the cache hit counter has five bits and the cache accesses counter has five bits: (Fertig, Abstract; and column 8, lines 31-49, where the system of Fertig may use counters with an arbitrary number of bits that dictate a maximum value to be used for comparison to a threshold to determine whether to perform prefetching operations. Although Fertig explicitly teaches the use of 6-bit counters, it would have been obvious to a person having ordinary skill in the art to modify the system of Fertig to use 5-bit counters. The modification would have been obvious because a person having ordinary skill in the art would be motivated to reduce system complexity while increasing granularity of cache management by opting to make an architectural design choice of using 5-bit counters instead of 6-bit counters. Fertig therefore particularly teaches wherein the cache hit counter has five bits and the cache accesses counter has five bits).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Fertig and Ono before them before the instant application was effectively filed, to modify the system of Ono to include the principles of Fertig of implementing counters for cache accesses, hits, and misses and resetting the respective values of the counters prior to overflow of the counters.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance by implementing techniques to enable management of cache prefetch request predictions with a desired degree of certainty in order to reduce or eliminate needless prefetch requests (Fertig, column 6, line 52, to column 6, line 4).
As per claim 11, the rejection of claim 10 is incorporated, and the Examiner notes that the language of claim 11 is substantially similar to the language of claim 4. Claim 11 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 4.
As per claim 12, the rejection of claim 10 is incorporated, and the Examiner notes that the language of claim 12 is substantially similar to the language of claim 5. Claim 12 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 5.
As per claim 18, the rejection of claim 17 is incorporated, and the Examiner notes that the language of claim 18 is substantially similar to the language of claim 4. Claim 18 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 4.
As per claim 19, the rejection of claim 17 is incorporated, and the Examiner notes that the language of claim 19 is substantially similar to the language of claim 5. Claim 19 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of claim 5.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
USPGPUB 2023/0108964: teaches techniques for increasing cache hit and cache miss prediction accuracy.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached at (571)272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135
