DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 02/26/2026 is accepted, in which, claims 1, 13, and 17 are amended. Claims 1 and 13 are independent with claims 1-21 awaiting an action on the merits as follows.
The objection to the specification is withdrawn in view of the amended title.
The rejection of claims 7 and 17 under USC 112b is withdrawn in view of the amended claims.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 7, 9, 10, 12-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 20230215956 A1), and further in view of Kitakado (US 20120146043 A1).
Regarding claim 1, Oh teaches a transistor (DT, Fig 4) comprising:
a first electrode (GE);
an active layer (AL) disposed under (shown under, Fig 5) the first electrode (GE) and
including a source region (ALS), a drain region (ALD), and an active region (ALM) overlapping (shown overlapping) the first electrode (GE) on a plane (XZ); and
a second electrode (BE) disposed under (shown under) the active layer (AL) and overlapping (shown overlapping) at least a portion of the active layer (AL) on a plane (XZ);
wherein the active layer (AL) includes a hole pattern (AH), and
the hole pattern (AH) overlaps (shown overlapping) at least a portion of the source region (ALS) and a portion of the drain region (ALD) on a plane (XZ).
Oh fails to explicitly teach the second electrode includes a second electrode hole pattern.
However, Kitakado teaches wherein the second electrode includes a second electrode hole pattern (37A: holes between bottom gate 37 sections, Fig 9).
Oh and Kitakado are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Oh with the features of Kitakado to create a transistor wherein the second electrode includes a second electrode hole pattern that can be fabricated easily and can achieve leakage current reduction, without its structure becoming complex or the device becoming bulky (Kitakado, [Abs.]).
Regarding claim 2, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the drain region (ALD, Fig 4), the active region (ALM), and the source region (ALS) are sequentially arranged (shown sequential) along a first direction (X), and
a length (BEL: length from leftmost edge to rightmost edge of BE) of the second electrode (BE) in the first direction (X) is greater (shown greater) than a length (GEL: length from leftmost edge to rightmost edge of GE) of the first electrode (GE) in the first direction (X).
Regarding claim 3, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the hole pattern (AH, Fig 4) partially overlaps (shown overlapping) the first electrode (GE).
Regarding claim 7, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the hole pattern (AH, Fig 4) is in a part (AHO: outer portion of AH shown only overlapping ALS in the XZ plane indicated by white rectangles) of the active layer (AL) that does not overlap (shown not overlapping) the first electrode (GE).
Regarding claim 9, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the hole pattern (AH, Fig 4) partially overlaps (shown overlapping) the second electrode (BE).
Regarding claim 10, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the hole pattern (AH, Fig 4) overlaps (shown overlapping) the second electrode (BE).
Regarding claim 12, the combination of Oh and Kitakado discloses the transistor of claim 1. Oh goes on to teach wherein the active layer (AL, Fig 4) comprises an oxide semiconductor (oxide semiconductor, [0057]).
Regarding claim 13, Oh teaches a display panel (100, Fig 1) comprising:
a base layer (110, Fig 5);
a circuit layer (PCA, Fig 3) disposed on (shown on, Fig 5) the base layer (110) and including a gate driving circuit (Fig 2; driving element, [0043]); and
a light-emitting layer (ELA) disposed on (shown on) the circuit layer (PCA),
wherein the gate driving circuit (Fig 2) includes a plurality of transistors (DT; each SP contains the circuit layer PCA where the circuit is arranged, [0037]; device contains a plurality of subpixels SP, [0032]; therefore, the gate driving circuit contains a plurality of transistors), and
at least one of the plurality of transistors (DT, Fig 4) includes a first electrode (GE), an active layer (AL) disposed under (shown under) the first electrode (GE) and including a hole pattern (AH), and
a second electrode (BE) disposed under (shown under) the active layer (AL) and overlapping (shown overlapping, Fig 5) at least a portion of the active layer (AL) on a plane (XZ).
Oh fails to explicitly teach the second electrode includes a second electrode hole pattern.
However, Kitakado teaches wherein the second electrode includes a second electrode hole pattern (37A: holes between bottom gate 37 sections, Fig 9).
Oh and Kitakado are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Oh with the features of Kitakado to create a transistor wherein the second electrode includes a second electrode hole pattern that can be fabricated easily and can achieve leakage current reduction, without its structure becoming complex or the device becoming bulky (Kitakado, [Abs.]).
Regarding claim 14, the combination of Oh and Kitakado discloses the display panel of claim 13. Oh goes on to teach wherein the active layer (AL, Fig 4) comprises a source region (ALS), a drain region (ALD), and an active region (ALM) overlapping (shown overlapping) the first electrode (GE) on a plane (XZ),
the drain region (ALD), the active region (ALM), and the source region (ALS) are sequentially arranged (shown sequential) along a first direction (X), and
a length (BEL: length from leftmost edge to rightmost edge of BE) of the second electrode (BE) in the first direction (X) is greater (shown greater) than a length (GEL: length from leftmost edge to rightmost edge of GE) of the first electrode (GE) in the first direction (X).
Regarding claim 15, the combination of Oh and Kitakado discloses the display panel of claim 14. Oh goes on to teach wherein the hole pattern (AH, Fig 4) overlaps (shown overlapping) at least a portion of the source region (ALS) and a portion of the drain region (ALD) on a plane (XZ).
Regarding claim 16, the combination of Oh and Kitakado discloses the display panel of claim 13. Oh goes on to teach wherein on a plane (XZ, Fig 4), one portion of the hole pattern (AH) overlaps (shown overlapping) the first electrode (GE).
Regarding claim 18, the combination of Oh and Kitakado discloses the display panel of claim 13. Oh goes on to teach wherein the hole pattern (AH, Fig 4) partially overlaps (shown overlapping) the second electrode (BE).
Regarding claim 19, the combination of Oh and Kitakado discloses the display panel of claim 13. Oh goes on to teach wherein the hole pattern (AH, Fig 4) does not overlap (shown not overlapping) the first electrode (GE).
Regarding claim 20, the combination of Oh and Kitakado discloses the display panel of claim 13. Oh goes on to teach wherein the hole pattern (AH, Fig 4) overlaps (shown overlapping) the second electrode (BE).
Claims 4, 5, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 20230215956 A1), in view of Kitakado (US 20120146043 A1), and further in view of Kuwabara (US 20070096096 A1).
Regarding claim 4, the combination of Oh and Kitakado discloses the transistor of claim 3. Oh teaches the first electrode (GE, Fig 4), and goes on to teach wherein the drain region (ALD, Fig 4), the active region (ALM), and the source region (ALS) are sequentially arranged (shown sequential) along a first direction (X),
an overlap length (L4: L1-L2, Fig 6) of the hole pattern (AH) overlapping the first electrode (GE) is equal to or less than about 4 µm (less; edge of the gate electrode GE corresponds to the active layer holes AH, [0066]; if the edge corresponds to the hole, then the overlap length would be zero) measured in the first direction (X).
The combination fails to explicitly teach a length of the first electrode in the first direction is about 4 µm to about 10 µm.
However, Kuwabara teaches a length (5 µm, [0052]) of the first electrode in the first direction is about 4 µm to about 10 µm.
Oh, Kitakado, and Kuwabara are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Oh and Kitakado with the features of Kuwabara to create a length of the first electrode in the first direction is about 4 µm to about 10 µm so the device has high definition, high aperture ratio and high reliability (Kuwabara, [0005]) along with improved productivity and lower cost (Kuwabara, [0007]) by creating high response speed which is suitable for displaying moving images, low voltage drive, and low power consumption drive (Kuwabara, [0008]).
Regarding claim 5, the combination of Oh, Kitakado, and Kuwabara discloses the transistor of claim 4. Oh goes on to teach wherein the overlap length (L4, Fig 6) of the hole pattern (AH) overlapping the first electrode (GE) is equal to or less than about 1 µm (less; edge of the gate electrode GE corresponds to the active layer holes AH, [0066]; if the edge corresponds to the hole, then the overlap length would be zero) measured along the first direction (X).
Regarding claim 17, the combination of Oh and Kitakado discloses the display panel of claim 16. Oh teaches the first electrode (GE, Fig 4), and goes on to teach wherein the active layer (AL, Fig 4) comprises a source region (ALS), a drain region (ALD), and an active region (ALM),
wherein the active region (ALM) overlaps (shown overlapping) the first electrode (GE),
wherein the drain region (ALD), the active region (ALM), and the source region (ALS) are sequentially arranged (shown sequential) along a first direction (X),
an overlap length (L4: L1-L2, Fig 6) of the hole pattern (AH) overlapping the first electrode (GE) is equal to or less than about 4 µm (less; edge of the gate electrode GE corresponds to the active layer holes AH, [0066]; if the edge corresponds to the hole, then the overlap length would be zero) measured in the first direction (X).
The combination fails to explicitly teach a length of the first electrode in the first direction is about 4 µm to about 10 µm.
However, Kuwabara teaches a length (5 µm, [0052]) of the first electrode in the first direction is about 4 µm to about 10 µm.
Oh, Kitakado, and Kuwabara are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Oh and Kitakado with the features of Kuwabara to create a length of the first electrode in the first direction is about 4 µm to about 10 µm so the device has high definition, high aperture ratio and high reliability (Kuwabara, [0005]) along with improved productivity and lower cost (Kuwabara, [0007]) by creating high response speed which is suitable for displaying moving images, low voltage drive, and low power consumption drive (Kuwabara, [0008]).
Claims 6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 20230215956 A1), in view of Kitakado (US 20120146043 A1), and further in view of the obviousness of change in proportion.
Regarding claims 6 and 8, the combination of Oh and Kitakado discloses the transistor of claim 3 and claim 7. Oh teaches the active layer (AL), and goes on to teach wherein the hole pattern (AH, Fig 4; two or more holes, [0059]) comprises a plurality (plurality shown) of holes (AH), and
a width (W) of the active layer (AL).
The combination fails to explicitly teach a ratio of sum of widths of the plurality of holes to a width of the active layer is no more than about 40% (claim 6) or 80% (claim 8).
However, in paragraph [0059], Oh states the active layer AL may have two or more holes AH. Figure 3 of Oh shows AL with 16 holes in two columns of 8, figure 4 shows 6 holes in two columns of 3, and figure 8 shows holes with varied widths such that the ratio on the source side of the active layer is different than the ratio on the drain side. The ratio of the sum of the widths of the hole pattern and the width of the active layer would be different in each embodiment.
Section 2144.04.IV.A discusses the obviousness of change of proportion. Oh discloses the claimed invention except for a ratio of sum of widths of the plurality of holes to a width of the active layer is no more than about 40% (claim 6) or 80% (claim 8). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have these ratios because Oh discloses several embodiments that affect the ratio between the sum of widths of the hole pattern and the width of the active layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claims 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Oh (US 20230215956 A1), in view of Kitakado (US 20120146043 A1), and further in view of Jang (US 20160093643 A1).
Regarding claims 11 and 21, the combination of Oh and Kitakado discloses the transistor of claim 1 and the display panel of claim 13. Oh teaches the first electrode (GE, Fig 4), and the second electrode (BE).
The combination fails to explicitly teach the first electrode and the second electrode are electrically connected to each other and receive a same voltage.
However, Jang teaches wherein the first electrode and the second electrode are electrically connected to each other and receive a same voltage (the first gate electrode is electrically connected to the second gate electrode, the same voltage is applied to the first gate electrode and the second gate electrode, [Abstract]).
Oh, Kitakado, and Jang are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor display devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Oh and Kitakado with the features of Jang to create a device wherein the first electrode and the second electrode are electrically connected to each other and receive a same voltage having high performance electrical characteristics (Jang, [0002]) to solve the problem that exists in that electrical characteristics of the transistor is deteriorated if a voltage applied to the top gate is different from that applied to the bottom gate (Jang, [0006]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim (US 20130043479 A1) - Active layer with several hole embodiments.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897