DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 5 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasao et al. (US PG. Pub. 2021/0345496) in view of Holzer et al. (US PG. Pub. 2017/0279385).
Regarding claim 1 – Sasao teaches a multilayer printed circuit board (figs. 21-23), comprising: a dielectric material (300C [paragraph 0120] Sasao states, “printed circuit board 300C”) and at least two conductor layers (fig. 23, PTN1-PTN4 shown on top and bottom surface SA/SB [paragraph 0096] Sasao states, “the pattern wirings PTN1 to PTN4 are multilayer wirings, are formed on both the main mounting surface SA and the sub-mounting surface SB (and in an intermediate wiring layer) to overlap with each other, and are electrically connected to each other through via holes”); the conductor layers (PTN1-PTN4) comprising: a plurality of individual mounting pads (pads shown in PTN1 & PTN2 connected to the power module 220 that have high-side switches shown in figure 21) for high-side switches (M1 [paragraph 0068] Sasao states, “The power modules 220 include a high-side switch (switching transistor) M1, a low-side switch (synchronous rectifier transistor transistor) M2”); a plurality of individual mounting pads (pads shown in PTN1 & PTN2 connected to the power module 220 that have low-side switches M2 shown in figure 21) for low-side switches (M2); a first common input line (input line PTN2 on top conductor layer [paragraph 0088] Sasao states, “The first pattern wirings PTN1_1 to PTN1_3 correspond to input lines 202_1 to 202_3”; figure 32 shows Vin at 202-1) for the high-side switches (M1); and a second common input line (input line PTN2 on bottom conductor layer) for the low-side switches (M2), wherein the first common input line (input line PTN2 on top conductor layer) and the second common input line (input line PTN2 on bottom conductor layer) at least partially overlap in a height direction of the printed circuit board (figure 22 shows the power modules 220 having the high and low-side switches being aligned along the x-direction and therefore the PTN2 shown in figure 23 will overlap in a height direction (z-direction); overlap also discussed in paragraph 0096 quoted above).
Sasao fails to teach a plurality of individual mounting pads for high-side switches arranged on a first side of the dielectric material; a plurality of individual mounting pads for low-side switches alternatingly interleaved with the plurality of individual mounting pads for high-side switches arranged on a first side of the dielectric material.
Holzer teaches a plurality of individual mounting pads (figs. 1-3, KF11, KF12 [paragraph 005] Holzer states, “two first contact surfaces (KF11, KF12) on the surface (OF), upon which respectively a first power transistor (T11, T12) is directly arranged”) for high-side switches (T11, T12 [paragraph 0040] Holzer states, “one of the two first power transistors (e.g. the “high-side” power transistors)”) arranged on a first side (see side shown in figures 1-2) of the dielectric material ([paragraph 0029] Holzer states, “The circuit carrier may comprise a printed circuit board and/or a ceramic substrate”); a plurality of individual mounting pads (KF31 & KF32 [paragraph 0006] Holzer states, “two second power transistors (T21, T22) is arranged respectively next to one of the at least two third contact surfaces (KF31, KF32)”) for low-side switches (T21, T22 [paragraph 0040] Holzer states, “the two second power transistors (e.g. the “low-side” power transistors)”) alternatingly interleaved ([paragraph 0055] Holzer states, “The first and third contact surfaces KF11, KF12 and KF31, KF32 here are alternating”) with the plurality of individual mounting pads (KF11 & KF12) for high-side switches (T11, T12) arranged on a first side of the dielectric material (figures 1 and 2 show the mounting pads for high and low side switches being on an upper surface and appears to meet the claimed limitation).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer printed circuit board having high side and low side switches having a first and second common input line that overlap as taught by Sasao with the mounting pads for high-side switches and mounting pads for low-side switches being arranged on a first side of the dielectric material and being alternatively interleaved as taught by Holzer because Holzer states, “By the alternating arrangement of the first and third contact surfaces, by means of which the respective positive and negative voltage-side power transistors are connected to their corresponding power supply conductors, the respective induction surface areas, which span between the respective positive and negative voltage-side power transistors, and consequently also the total induction surface area of the power module, are further reduced…one of the two first power transistors (e.g. the “high-side” power transistors) and, respectively, one of the two second power transistors (e.g. the “low-side” power transistors), to be mutually paired in an alternating and adjacent arrangement, with small mutual clearances. In consequence, stray induction currents are again reduced” [paragraph 0037 & 0040].
Regarding claim 4 – Sasao in view of Holzer teach the printed circuit board of claim 1, wherein the first common input line (Sasao; figs. 21-23, input line PTN2 on top conductor layer [paragraph 0088] Sasao states, “The first pattern wirings PTN1_1 to PTN1_3 correspond to input lines 202_1 to 202_3”; figure 32 shows Vin at 202-1) and the second common input line (input line PTN2 on bottom conductor layer) completely overlap in the height direction of the printed circuit boards (figure 22 shows the power modules 220 having the high and low-side switches being aligned along the x-direction and therefore the PTN2 shown in figure 23 will reasonably completely overlap in a height direction (z-direction)).
Regarding claim 5 – Sasao teaches an inverter (figs. 21-23; The preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.) comprising: a plurality of high-side switches (fig. 22, high-side switches M1 within power module 220_2 & 220_4 [paragraph 0068] Sasao states, “The power modules 220 include a high-side switch (switching transistor) M1, a low-side switch (synchronous rectifier transistor transistor) M2”); a plurality of low-side switches (M2 contained within 220_1 & 220_3) alternatingly arranged with the plurality of high-side switches (figure 22 shows the power modules 220_1 to 220_4 alternating on opposite sides of the PCB 330C); a multilayer printed circuit board (figs. 21-23) comprising a dielectric material (300C [paragraph 0120] Sasao states, “printed circuit board 300C”) and at least two conductor layers (fig. 23, PTN1-PTN4 shown on top and bottom surface SA/SB [paragraph 0096] Sasao states, “the pattern wirings PTN1 to PTN4 are multilayer wirings, are formed on both the main mounting surface SA and the sub-mounting surface SB (and in an intermediate wiring layer) to overlap with each other, and are electrically connected to each other through via holes”); the conductor layers (PTN1-PTN4) comprising: a respective mounting pad (pads shown in PTN1 & PTN2 connected to the power module 220 that have high-side switches shown in figure 21) for each of the plurality of high-side switches (high-side switches M1 within power module 220_2 & 220_4); a respective mounting pad (pads shown in PTN1 and PTN2 connected to the power module 220 that have low-side switches shown in figure 21) for each of the plurality of low-side switches (low-side switches M2 within power modules 220_1 & 220_3); and a first common input line (input line PTN2 on top conductor layer [paragraph 0088] Sasao states, “The first pattern wirings PTN1_1 to PTN1_3 correspond to input lines 202_1 to 202_3”; figure 32 shows Vin at 202-1) for the plurality of high-side switches (M1); and a second common input line (input line PTN2 on bottom conductor layer) for the plurality of low-side switches (M2), wherein the first common input line (input line PTN2 on top conductor layer) and the second common input line (input line PTN2 on bottom conductor layer) at least partially overlap in a height direction of the printed circuit board (figure 22 shows the power modules 220 having the high and low-side switches being aligned along the x-direction and therefore the PTN2 shown in figure 23 will overlap in a height direction (z-direction); overlap also discussed in paragraph 0096 quoted above).
Sasao fails to teach a plurality of high-side switches arranged in parallel; a plurality of low-side switches arranged in parallel and alternating arranged with the plurality of high-side switches; the conductor layers comprising: a respective mounting pad for each of the plurality of high-side switches arranged on a first side of the dielectric material; a respective mounting pad for each of the plurality of low-side switches alternatingly arranged with the respective mounting pads for each of the plurality of high-side switches on the first side of the dielectric material.
Holzer teaches a plurality of high-side switches (figs. 1-3, T11, T12 [paragraph 0005 & 0040] Holzer states, “a first power transistor (T11, T12)… the two first power transistors (e.g. the “high-side” power transistors)”) arranged in parallel (T11 and T12 are shown parallel left to right and appears similar that of the instant application); a plurality of low-side switches (T21 & T22 [paragraph 0005] Holzer states, “two second power transistors (T21, T22)…two second power transistors (e.g. the “low-side” power transistors)”) arranged in parallel (T21 and T22 are shown parallel left to right and appears similar that of the instant application) and alternating arranged with the plurality of high-side switches ([paragraph 0040] Holzer states, “two first power transistors (e.g. the “high-side” power transistors) and, respectively, one of the two second power transistors (e.g. the “low-side” power transistors), to be mutually paired in an alternating and adjacent arrangement, with small mutual clearances”); the conductor layers comprising: a respective mounting pad (KF11 & KF12) for each of the plurality of high-side switches (T11 & T12) arranged on a first side (top surface) of the dielectric material ([paragraph 0029] Holzer states, “The circuit carrier may comprise a printed circuit board and/or a ceramic substrate”); a respective mounting pad (KF31 & KF32) for each of the plurality of low-side switches (T21 & T22) alternatingly arranged with the respective mounting pads (KF11 & KF12) for each of the plurality of high-side switches (T11 & T12) on the first side of the dielectric material (figures 1 and 2 show the mounting pads for high and low side switches being on an upper surface and appears to meet the claimed limitation).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer printed circuit board having high side and low side switches having a first and second common input line that overlap as taught by Sasao with the mounting pads for high-side switches and mounting pads for low-side switches being arranged on a first side of the dielectric material and being alternatively interleaved as taught by Holzer because Holzer states, “By the alternating arrangement of the first and third contact surfaces, by means of which the respective positive and negative voltage-side power transistors are connected to their corresponding power supply conductors, the respective induction surface areas, which span between the respective positive and negative voltage-side power transistors, and consequently also the total induction surface area of the power module, are further reduced…one of the two first power transistors (e.g. the “high-side” power transistors) and, respectively, one of the two second power transistors (e.g. the “low-side” power transistors), to be mutually paired in an alternating and adjacent arrangement, with small mutual clearances. In consequence, stray induction currents are again reduced” [paragraph 0037 & 0040].
Regarding claim 17 – Sasao in view of Holzer teach the inverter of claim 5, wherein each of the plurality of low-side switches (Holzer; fig. 1, T21 & T22) carries a portion of a first signal ([paragraph 0061] Holzer states, “an external control signal for the control of the negative voltage-side power MOSFETs T21, T22 can be applied”) and each of the plurality of high-side switches (T11 & T12) carries a portion of a second signal ([paragraph 0075] Holzer states, “the control signal for the control of the negative voltage-side power transistors T11, T12 is applied to the respective gate terminals G21, G22 thereof”).
Claim(s) 2-3 and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasao et al. in view of Holzer et al. as applied to claim 1 above, and further in view of Kapusta (US PG. Pub. 2020/0176360).
Regarding claim 2 – Sasao in view of Holzer teach the printed circuit board of claim 1, but fails to teach wherein the multilayer printed circuit board comprise the dielectric material and at least four conductor layers.
Kapusta teaches wherein a multilayer printed circuit board (fig. 9-12) comprise a dielectric material (104 [paragraph 0032] Kapusta states, “metallized insulating substrate 104”) and at least four conductor layers (figure 9 shows two metallized insulating substrates 104 having “at least four conductor layers”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer printed circuit board as taught by Sasao in view of Holzer with the four conductor layers as taught by Kapusta because additional conductor layers allows for higher circuit density and signal speed.
Regarding claim 3 – Sasao in view of Holzer and Kapusta teach the printed circuit board of claim 2, wherein the overlapping first (Kapusta; fig. 10B, 132) and second common input lines (134) are distributed on the at least four conductor layers (figure 9 shows two metallized insulating substrates 104 having “at least four conductor layers” with overlapping lines 132 & 134).
Regarding claim 6 – Sasao in view of Holzer teach the inverter of claim 5, but fails to teach wherein the multilayer printed circuit board comprise the dielectric material and at least four conductor layers.
Kapusta teaches wherein a multilayer printed circuit board (fig. 9-12) comprise a dielectric material (104 [paragraph 0032] Kapusta states, “metallized insulating substrate 104”) and at least four conductor layers (figure 9 shows two metallized insulating substrates 104 having “at least four conductor layers”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the multilayer printed circuit board as taught by Sasao in view of Holzer with the four conductor layers as taught by Kapusta because additional conductor layers allows for higher circuit density and signal speed.
Regarding claim 7 – Sasao in view of Holzer and Kapusta teach the printed circuit board of claim 6, wherein the overlapping first (Kapusta; fig. 10B, 132) and second common input lines (134) are distributed on the at least four conductor layers (figure 9 shows two metallized insulating substrates 104 having “at least four conductor layers” with overlapping lines 132 & 134).
Regarding claim 8 – Sasao in view of Holzer and Kapusta teach the inverter of claim 7, wherein the first common input line (Sasao; figs. 21-23, input line PTN2 on top conductor layer [paragraph 0088] Sasao states, “The first pattern wirings PTN1_1 to PTN1_3 correspond to input lines 202_1 to 202_3”; figure 32 shows Vin at 202-1) and the second common input line (input line PTN2 on bottom conductor layer) completely overlap in the height direction of the printed circuit boards (figure 22 shows the power modules 220 having the high and low-side switches being aligned along the x-direction and therefore the PTN2 shown in figure 23 will reasonably completely overlap in a height direction (z-direction)).
Regarding claim 9 – Sasao in view of Holzer and Kapusta teach the inverter of claim 7, wherein the first (Sasao; figs. 21-23, input line PTN2 on top conductor layer [paragraph 0088] Sasao states, “The first pattern wirings PTN1_1 to PTN1_3 correspond to input lines 202_1 to 202_3”; figure 32 shows Vin at 202-1) and the second common input lines (input line PTN2 on bottom conductor layer) at least partially overlap one another in a projection along a thickness of the multilayer printed circuit board (figure 22 shows the power modules 220 having the high and low-side switches being aligned along the x-direction and therefore the PTN2 shown in figure 23 will reasonably completely overlap in a height direction (z-direction)).
Allowable Subject Matter
Claims 10-15 are allowed.
Response to Arguments
Applicant's arguments filed 12/9/2025 have been fully considered but they are not persuasive.
Applicant argues regarding the rejection to claim 1, “Sasao discloses a DC-DC converter, where each line is carrying a different signal. In contrast, the disclosed and claimed multilayer printed circuit board has multiple parallel devices interdigitated each carrying a portion of the same signal. Because Sasao discloses each line carrying a different signal , as discussed in more detail below, it is different than the line of the disclosed and claimed configuration…The interconnections between the individual power modules 22 cannot result in the claimed configurations because each power module 220 is an individual component…The wirings PTN1 to PTN4 are first and second common input lines as disclosed and claimed. Therefore the claimed configuration cannot be realized with the power modules 220 and circuit board 300 of Sasao without redesigning the entire circuit, which would render Sasao unsuitable for its intended purpose” [REMARKS pages 10-12].
Examiner disagrees. As the claims are currently written the specific signal being argued is not claimed. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “each carrying a portion of the same signal”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Additionally PTN2 as shown in figure 23 of Sasao is considered the first common input line (upper PTN2 connected to upper module 220 that includes a high-side switch M1) and the second common input line (lower PTN2 connected to lower module 220 that includes a low-side switch M2). The overlapping of the upper and lower PTN2 is described in paragraph 0108 and quoted in the rejection to claim 1 above and appears to meet the claimed limitation.
Applicant lastly argues “Further, the individual mounting pads for high-side switches and low side switches are not part of the circuit board 300A as required in the claim but are internal to the power module 220. Thus, for this additional reason, Sasao fails to disclose the limitation for which it is cited” [REMARKS page 12].
Examiner disagrees. Sasao shows in figure 23 pads/connections between power modules 220 having the high-side and low-side switches that are electrically connected together. Additionally the secondary reference Holzer more clearly shows pads that connected to the switches.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847