Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The instant application is a continuation of parent application 15/202,995, now Patent 10,885,429. The instant application is also a continuation of parent application 17/141,981, now Patent 11,748,609.
Examiner notes that the present claims appear identical to the originally filed claims of application 15/202,995 of 7/6/2016. Further, the referenced cited by the applicant in the Information Disclosure Statement are present in the file folder of a parent application.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a resistance adjuster configured to adjust a resistance value in Claims 1 and 15.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim limitations resistance adjustor configured to adjust a resistance value in each of Claims 1 and 15 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The resistance adjustor is described in paragraphs [0072-0073] of the specification only with regards to function, with no corresponding structure. Specifically, in [0073], “The resistance adjustors implemented for training units 545 and 555 may be any type of resistance adjuster that adjusts resistance values associated with resistive memories to decrease the difference between an output voltage signal and a desired signal,” which does not provide any corresponding structure. Fig. 8A, cited in paragraph [0072], further does not describe a structure for the resistance adjuster. Therefore, Claims 1 and 15 are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
For the purpose of examination, any circuit element which adjusts the resistance of the resistive memories will be interpreted to read on the claimed resistance adjuster.
Claim 7 recites the limitation the analog neuromorphic circuit crossbar configuration of Claim 1. There is insufficient antecedent basis for this limitation in the claim, as Claim 1 does not recite any crossbar configuration. For the purpose of examination, Claim 7 will be interpreted as if it had read the analog neuromorphic circuit of Claim 1.
Claim 16 recites the limitation the analog neuromorphic system that implements a plurality of resistive memories. There is insufficient antecedent basis for this limitation in the claim, as this recitation is the first element of the preamble of the claim. For the purpose of examination, the claim will be interpreted as if it had read the analog neuromorphic system of Claim 15 that implements a plurality of resistive memories.
Claims 2-7 and 16-20 are rejected for dependence upon an indefinite claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-8, and 10-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Soudry, “Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training.”
Regarding Claim 1, Soudry teaches an analog neuromorphic circuit (pg. 3, 2nd column, last paragraph, “dedicated analog hardware for implementing online gradient descent is described … to implement general MNNs [multi-layer neural networks]”) that implements a plurality of resistive memories (pg. 2, 1st column, 2nd-to-last paragraph, “The proposed scheme uses a memristor as a memory element to store the weight”), comprising: a plurality of resistive memories configured to: provide a resistance to an input voltage signal as the input voltage signal propagates through the plurality of resistive memories generating a first output voltage signal (pg. 4, Fig. 2, where “
x
1
,
…
,
x
M
” are inputs corresponding to input voltage signal “u” that generate a first output voltage signal “
r
1
,
…
,
r
N
”, i.e. pg. 6, 1st column, 4th paragraph – 2nd column, 1st paragraph, “During each read phase, a vector x is given and encoded in
u
and
u
-
… [the signal is passed through the memristors to] obtain
r
=
W
x
”); provide a resistance to a first error signal that propagates through the plurality of resistive memories generating a second output voltage signal (pg. 7, 1st column, 2nd paragraph, “This last operation requires the additional output
δ
≜
W
T
y
... The additional output can be generated by the circuit in an additional read phase … between the original read and write phases, in which the original role of the input and output lines is inverted” i.e. the first error signal is “y” and the second output voltage signal is
δ
); a first comparator configured to: compare the first output voltage signal to a desired output signal (pg. 7, 2nd column, in between Eqs. (35) & (36), “
y
=
d
-
r
”, the comparator shown on pg. 5, Fig. 4(b), the bottom-right circuit element performing the subtraction; with pg. 3, 1st column, 4th paragraph, “should aim to predict the right desired labels d”), wherein the desired output signal is at a signal level that the first output voltage signal is desired to be within a threshold of the signal level (pg. 8, 1st column, Fig. 5, “training the SNN using gradient descent on the MSE [error] will tend to decrease this error until it converges to some fixed-point” i.e. the error converging denotes desired to be within a threshold of the signal level), generate the first error signal that is representative of a difference between the first output voltage signal and the desired output signal (pg. 7, 2nd column, in between Eqs. (35) & (36), “
y
=
d
-
r
”, the comparator shown on pg. 5, Fig. 4(b), the bottom-right circuit element performing the subtraction to generate the error signal y which is the difference between first output voltage signal r and desired output signal d); and provide the first error signal so that the first error signal propagates back through the plurality of resistive memories (pg. 7, 1st column, 2nd paragraph, “This last operation requires the additional output
δ
≜
W
T
y
... The additional output can be generated by the circuit in an additional read phase … between the original read and write phases, in which the original role of the input and output lines is inverted” i.e. the first error signal is “y”, also see pg. 4, Fig. 2 and pg. 5, Fig. 4(b) which illustrate that y propagates back through the plurality of resistive memories); and a resistance adjuster configured to adjust a resistance value associated with each resistive memory (pg. 6, 1st column, 3rd paragraph, “in the updating phase (write), the synaptic weights are updated according to the update rule … in the proposed design, the synaptic weight
W
n
m
is stored using
s
n
m
, the memristor state variable [specifying conductivity/resistance]”) based on the first error signal and the second output voltage signal (pg. 7, 1st column, 2nd paragraph, “For each layer, a synaptic grid circuit … updates the weight matrix as in (30). This last operation requires the additional output
δ
≜
W
T
y
” i.e. is based on the first error signal y and the second output voltage signal
δ
”) to decrease the output between the first output voltage signal and the desired output signal (pg. 3, 1st column, 4th paragraph, “W is tuned to minimize some measure of error between the estimated and desired labels”, i.e. r and d).
Regarding Claim 3, Soudry teaches the analog neuromorphic circuit of Claim 1 (and thus the rejection of Claim 1 is incorporated). Soudry further teaches wherein the plurality of resistive memories is arranged in a grid configuration that includes at least two rows and at least two columns of resistive memories (pg. 4, Fig. 2, “Every (n,m) node in the grid is a memristor-based synapse”) so that each column of resistive memories is grouped as a vertical neuron configuration and each set of two rows or resistive memories is grouped as a horizontal neuron configuration (pg. 4, Fig. 2 has columns and rows of neurons, including groups that are columns and groups that are any two rows).
Regarding Claim 4, Soudry teaches the analog neuromorphic circuit of Claim 3 (and thus the rejection of Claim 3 is incorporated). Soudry further teaches wherein the input voltage signal is propagated through each vertical neuron configuration (pg. 4, Fig. 2, the inputs “
x
1
,
…
,
x
M
” are columns/vertical) so that each resistance of each resistive memory included in each of the vertical neuron configurations contribute to the generation of the first output voltage signal (pg. 4, Fig. 2, the outputs“
r
1
,
…
,
r
N
” correspond to rows and thus depend on each resistive memory included in each of the vertical neuron configurations).
Regarding Claim 5, Soudry teaches the analog neuromorphic circuit of Claim 4 (and thus the rejection of Claim 4 is incorporated). Soudry further teaches wherein the first error signal is propagated back through the plurality of resistive memories via each horizontal neuron configuration (pg. 4, Fig. 2, the errors “
y
1
,
…
,
y
N
” are input via rows/horizontal neuron configurations) so that each resistance of each resistive memory included in each of the horizontal neuron configurations contributes to the generation of the second output voltage signal (pg. 7, 1st column, 2nd paragraph, “in which the original role of the input and output lines is inverted” i.e. for the second read, the inputs are rows/errors/“
y
1
,
…
,
y
N
” and the second output voltage signal δ corresponds to columns and thus depends on each resistive memory included in each of the horizontal neuron configurations).
Regarding Claim 6, Soudry teaches the analog neuromorphic circuit of Claim 5 (and thus the rejection of Claim 5 is incorporated). Soudry further teaches wherein the propagation of the input signal though each of the vertical neuron configurations to generate the first output voltage signal and the propagation of the first error signal back through the plurality of resistive memories via each of the horizontal neuron configurations to generate the second output voltage signal is executed without additional resistive memories associated with additional analog neuromorphic circuits (pg. 4, 1st column, Fig. 2, neither the forward nor backward propagation relies upon any additional resistive memories, only the resistive memories in that
N
×
M
grid).
Regarding Claim 7, Soudry teaches the analog neuromorphic circuit [] of Claim 1 (and thus the rejection of Claim 1 is incorporated). Soudry further teaches wherein each resistive memory is a memristor (pg. 2, 1st column, 2nd-to-last paragraph, “the proposed scheme uses a memristor as a memory element to store the weight”).
Regarding Claim 8, Soudry teaches a method for adjusting resistances of a plurality of resistive memories (pg. 1, 1st column, Abstract, “a method for performing these update operations simultaneously using memristor-based arrays … given a voltage pulse, the conductivity of a memristor will increment”) positioned in an analog neuromorphic circuit (pg. 3, 2nd column, last paragraph, “dedicated analog hardware for implementing online gradient descent is described … to implement general MNNs [multi-layer neural networks]”), comprising: applying an input voltage signal to the neuromorphic circuit (pg. 4, 1st column, Fig. 2, “every node in the grid is a memristor-based synapse that receives voltage input from the shared
u
m
,
u
-
m
, and the
e
n
lines” where specifically
u
m
and
u
-
m
are components of the recited input voltage signal); providing a resistance to the input voltage signal by each resistive memory as the input voltage signal propagates through the plurality of resistive memories to generate a first output voltage signal (pg. 4, Fig. 2, where “
x
1
,
…
,
x
M
” are inputs corresponding to input voltage signal “u” that generate a first output voltage signal “
r
1
,
…
,
r
N
”, i.e. pg. 6, 1st column, 4th paragraph – 2nd column, 1st paragraph, “During each read phase, a vector x is given and encoded in
u
and
u
-
… [the signal is passed through the memristors to] obtain
r
=
W
x
”); comparing the first output voltage signal to a desired output signal (pg. 7, 2nd column, in between Eqs. (35) & (36), “
y
=
d
-
r
” with pg. 3, 1st column, 4th paragraph, “should aim to predict the right desired labels d”), wherein the desired output signal is at a signal level that the first output voltage signal is desired to be within a threshold of the signal level (pg. 8, 1st column, Fig. 5, “training the SNN using gradient descent on the MSE [error] will tend to decrease this error until it converges to some fixed-point” i.e. the error converging denotes desired to be within a threshold of the signal level), generating a first error signal that is representative of a difference between the first output voltage signal and the desired output signal (pg. 7, 2nd column, in between Eqs. (35) & (36), “
y
=
d
-
r
” to generate the first error signal y which is the difference between first output voltage signal r and desired output signal d); providing the first error signal so that the first error signal propagates back through the plurality of resistive memories; providing a resistance to the first error signal by each resistive memory as the first error signal propagates back through the plurality of resistive memories to generate a second output voltage signal (pg. 7, 1st column, 2nd paragraph, “This last operation requires the additional output
δ
≜
W
T
y
... The additional output can be generated by the circuit in an additional read phase … between the original read and write phases, in which the original role of the input and output lines is inverted” i.e. the first error signal is “y”, also see pg. 4, Fig. 2 and pg. 5, Fig. 4(b) which illustrate that y propagates back through the plurality of resistive memories); and adjusting a resistance value with each resistive memory (pg. 6, 1st column, 3rd paragraph, “in the updating phase (write), the synaptic weights are updated according to the update rule … in the proposed design, the synaptic weight
W
n
m
is stored using
s
n
m
, the memristor state variable [specifying conductivity/resistance]”) based on the first error signal and the second output voltage signal (pg. 7, 1st column, 2nd paragraph, “For each layer, a synaptic grid circuit … updates the weight matrix as in (30). This last operation requires the additional output
δ
≜
W
T
y
” i.e. is based on the first error signal y and the second output voltage signal
δ
”) to decrease the output between the first output voltage signal and the desired output signal (pg. 3, 1st column, 4th paragraph, “W is tuned to minimize some measure of error between the estimated and desired labels”, i.e. r and d).
Regarding Claim 10, Soudry teaches the method of Claim 8 (and thus the rejection of Claim 8 is incorporated). Soudry further teaches arranging the plurality of resistive memories in a grid configuration that includes at least two rows and at least two columns of resistive memories (pg. 4, Fig. 2, “Every (n,m) node in the grid is a memristor-based synapse”) so that each column of resistive memories is grouped as a vertical neuron configuration and each set of two rows or resistive memories is grouped as a horizontal neuron configuration (pg. 4, Fig. 2 has columns and rows of neurons, including groups that are columns and groups that are any two rows).
Regarding Claim 11, Soudry teaches the method of Claim 10 (and thus the rejection of Claim 10 is incorporated). Soudry further teaches propagating the input voltage signal through each vertical neuron configuration (pg. 4, Fig. 2, the inputs “
x
1
,
…
,
x
M
” are columns/vertical) so that each resistance of each resistive memory included in each of the vertical neuron configurations contributes to the generation of the first output voltage signal (pg. 4, Fig. 2, the outputs“
r
1
,
…
,
r
N
” correspond to rows and thus depend on each resistive memory included in each of the vertical neuron configurations).
Regarding Claim 12, Soudry teaches the method of Claim 11 (and thus the rejection of Claim 11 is incorporated). Soudry further teaches propagating back the first error signal through the plurality of resistive memories via each horizontal neuron configuration (pg. 4, Fig. 2, the errors “
y
1
,
…
,
y
N
” are input via rows/horizontal neuron configurations) so that each resistance of each resistive memory included in each of the horizontal neuron configurations contributes to the generation of the second output voltage signal (pg. 7, 1st column, 2nd paragraph, “in which the original role of the input and output lines is inverted” i.e. for the second read, the inputs are rows/errors/“
y
1
,
…
,
y
N
” and the second output voltage signal δ corresponds to columns and thus depends on each resistive memory included in each of the horizontal neuron configurations).
Regarding Claim 13, Soudry teaches the method of Claim 12 (and thus the rejection of Claim 12 is incorporated). Soudry further teaches executing the propagation of the input signal though each of the vertical neuron configurations to generate the first output voltage signal and the propagation of the first error signal back through the plurality of resistive memories via each of the horizontal neuron configurations to generate the second output voltage signal without additional resistive memories associated with additional analog neuromorphic circuits (pg. 4, 1st column, Fig. 2, neither the forward nor backward propagation relies upon any additional resistive memories, only the resistive memories in that
N
×
M
grid).
Regarding Claim 14, Soudry teaches the method of Claim 8 (and thus the rejection of Claim 8 is incorporated). Soudry further teaches wherein each resistive memory is a memristor (pg. 2, 1st column, 2nd-to-last paragraph, “the proposed scheme uses a memristor as a memory element to store the weight”).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 and 2 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 1 of U.S. Patent No. 10,885,429.
Claims 3-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 2-6, respectively, of U.S. Patent No. 10,885,429.
Claims 8 and 9 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 7 of U.S. Patent No. 10,885,429.
Claims 10-14 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 8-12, respectively, of U.S. Patent No. 10,885,429.
Claims 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims 13-18, respectively, of U.S. Patent No. 10,885,429.
Claims 1 and 15 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 5 of U.S. Patent No. 11,748,609.
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over Claim 15 of U.S. Patent No. 11,748,609.
Although the claims at issue are not identical, they are not patentably distinct from each other because the reference claims anticipate the respective claims of the instant application.
Conclusion
Claims 2, 9, and 15-20 have been searched, but not rejected under either 35 USC 102 nor 35 USC 103.
Claims 2, 9, and 15-20 are rejected for reasons other than prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN M SMITH whose telephone number is (469)295-9104. The examiner can normally be reached on Monday - Friday, 8:00am - 4pm Pacific.
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/BRIAN M SMITH/Primary Examiner, Art Unit 2122
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