DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of fig. 16) and claims generic thereto (i.e., claims 1-26) in the reply filed on 02/27/2026 is acknowledged. The traversal is on the ground(s) that fig. 16 embodiment is a structural schematic that builds cumulatively upon all of the features introduced in the earlier embodiments (including figs. 1, 2, 5, and 6), and it further introduces the second signal line L2 and second crossing line 20 as an additive feature. The species thus cannot be considered to have mutually exclusive characteristics when one species fully encompasses the features of another. This is found persuasive and the restriction requirement is withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 15-24 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FEI et al. 20210125546.
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Regarding claims 1 and 26, figs. 6-7 of FEI discloses a display apparatus, comprising:
a display panel, comprising:
a display region 100 and at least two non-display regions 210s, wherein:
the at least two non-display regions at least include a first non-display region (left 210) and a second non-display region (right 210) which are disposed to be adjacent to each other;
the first non-display region and the second non-display region are arranged along a first direction 1 (fig. 6); and
the display region 100 at least partially surrounds the at least two non-display regions (fig. 6); and
the display region includes a plurality of first signal lines 123 extending along the first direction 1 (fig. 7);
at least a part of the plurality of first signal lines includes at least one first line segment (portion of 123 on left side fig. 7) and at least one second line segment (portion of 123 on right side of fig. 7);
the at least one first line segment 1323 is between two adjacent non-display regions 210 (fig. 7);
at least a part of the at least one second line segment is on a side of the first non-display region away from the second non-display region (left side of fig. 7) along the first direction 1, and/or, at least a part of the at least one second line segment is on a side of the second non-display region away from the first non-display region (right side of fig. 7) along the first direction 1; and
in a same first signal line (any 123 in fig. 7), a first line segment of the at least one first line segment and a second line segment of the at least one second line segment are electrically connected with each other through a first crossing line 1321.
Regarding claim 15, fig. 7 of FEI discloses further including: a frame region 220 configured by at least partially surrounding the display region, wherein at least a part of line segments in first crossing lines 1323 is at the frame region.
Regarding claim 16, fig. 3 of FEI discloses wherein: the display region further includes a plurality of second signal lines 111 extending along a second direction; at least a part of the plurality of second signal lines includes a third line segment (111 in top of fig. 3) and a fourth line segment (111 in bottom of fig. 3) which are arranged along the second direction; along the second direction, the third line segment and the fourth line segment are on two sides of the first non-display region or on two sides of the second non-display region; in a same second signal line, the third line segment and the fourth line segment are electrically connected with each other through a second crossing line 131; at least a part of second crossing lines 131 is disposed at a same layer as first crossing lines (fig. 11); and the second direction intersects the first direction.
Regarding claim 17, fig. 11 of FEI discloses wherein: the second crossing lines are disposed at a same layer as the first crossing lines.
Regarding claim 18, fig. 11 of FEI discloses wherein: the first crossing line is connected to a first signal line of the plurality of first signal lines through a first connection hole (that of left 123 and 132), and the second crossing line is electrically connected to a second signal line of the plurality of second signal lines through a second connection hole (that of 131 and 111); the display panel further includes a plurality of third connection holes (those right 123 and 132); and along a thickness direction of the display panel, the first connection hole, the second connection hole, and a third connection hole of the plurality of third connection holes are not overlapped with each other (fig. 11 of FEI necessary discloses no overlapped).
Regarding claim 19, fig. 3 of FEI discloses wherein: the second crossing line 131 includes a line segment extending along the second direction; and the line segment extending along the second direction is not overlapped with other second signal lines along a thickness direction of the display panel.
Regarding claim 20, figs. 2 and 6 of FEI discloses further including: fixed voltage signal lines 110/120 in the display region, wherein the fixed voltage signal lines include a first fixed voltage signal line 120 extending along the first direction (fig. 6) and a second fixed voltage signal line 110 extending along the second direction;
in the first crossing line and the second crossing line, along a thickness direction of the display panel, at least a part of line segments 123 (left and right 123 in fig. 11) extending along the first direction is overlapped with the first fixed voltage signal line 123, and at least a part of line segments extending along the second direction is overlapped with the second fixed voltage signal line 11.
Regarding claim 21, fig. 11 of FEI discloses wherein: in the first crossing line 1321 and the second crossing line 131, along a thickness direction of the display panel, at least a part of line segments (contact line segments) extending along the first direction is overlapped with the first signal line 123.
Regarding claim 22, fig. 11 of FEI discloses wherein: the first crossing line 1321 includes a first sub-line-segment extending along the first direction and a second sub-line-segment extending along the second direction; the second crossing line 131 includes a third sub-line-segment extending along the first direction and a fourth sub-line-segment extending along the second direction; and along a thickness direction of the display panel, the first sub-line-segment and the third sub-line-segment are not overlapped with each other, and the second sub-line-segment and the fourth sub-line-segment are not overlapped with each other (this is necessary the case as they are in the same layer and cannot overlap).
Regarding claim 23, figs. 3, 7 and 11 of FEI discloses wherein: at least a part of the third sub-line-segment is between (a broad term) two adjacent first sub-line-segments, and at least a part of the fourth sub-line-segment is between two adjacent second sub-line-segments.
Regarding claim 24, fig. 7 of, wherein: along the first direction, a length of the first non-display region (diameter of 210) is greater than a length of the second non-display region (length of 210 across that is not a diameter); and at least a part of second crossing lines half surrounds the first crossing line on a side of the first non-display region away from the second non-display region (compare fig. 3 and fig. 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-14 are rejected under 35 U.S.C. 103 as being unpatentable over FEI in view of Chen 11373599.
Regarding claim 2, FEI discloses claim 1, but does not disclose further including: a plurality of pixel drive circuits in the display region and a plurality of light-emitting elements electrically connected to the plurality of pixel drive circuits, wherein the plurality of pixel drive circuit is electrically connected to a plurality of control lines, and the plurality of first signal lines includes the plurality of control lines; and a first frame region and a second frame region which are opposite to each other along the first direction, wherein both the first frame region and the second frame region include a plurality of shift registers; at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the first frame region, and at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the second frame region; first crossing lines corresponding to at least a part of the plurality of control lines are wired along a first side of a second direction with respect to the first non-display region and the second non-display region; and first crossing lines corresponding to at least a part of the plurality of control lines are wired along a second side of the second direction with respect to the first non-display region and the second non-display region; the first side and the second side are opposite to each other along the second direction; and the second direction intersects the first direction.
However, Chen disclose a display panel comprising a plurality of pixel drive circuits in the display region and a plurality of light-emitting elements electrically connected to the plurality of pixel drive circuits, wherein the plurality of pixel drive circuit is electrically connected to a plurality of control lines, and the plurality of first signal lines includes the plurality of control lines; and a first frame region and a second frame region which are opposite to each other along the first direction, wherein both the first frame region and the second frame region include a plurality of shift registers (fig. 1 of Chen); at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the first frame region, and at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the second frame region; first crossing lines corresponding to at least a part of the plurality of control lines are wired along a first side of a second direction with respect to the first non-display region and the second non-display region; and first crossing lines corresponding to at least a part of the plurality of control lines are wired along a second side of the second direction with respect to the first non-display region and the second non-display region; the first side and the second side are opposite to each other along the second direction; and the second direction intersects the first direction.
In view of such teaching, it would have been obvious to form a display panel of FEI further including: a plurality of pixel drive circuits in the display region and a plurality of light-emitting elements electrically connected to the plurality of pixel drive circuits, wherein the plurality of pixel drive circuit is electrically connected to a plurality of control lines, and the plurality of first signal lines includes the plurality of control lines; and a first frame region and a second frame region which are opposite to each other along the first direction, wherein both the first frame region and the second frame region include a plurality of shift registers; at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the first frame region, and at least a part of the plurality of control lines is electrically connected to the plurality of shift registers in the second frame region; first crossing lines corresponding to at least a part of the plurality of control lines are wired along a first side of a second direction with respect to the first non-display region and the second non-display region; and first crossing lines corresponding to at least a part of the plurality of control lines are wired along a second side of the second direction with respect to the first non-display region and the second non-display region; the first side and the second side are opposite to each other along the second direction; and the second direction intersects the first direction such as taught by Chen in order to control the display panel.
Regarding claim 3, fig. 7 of FEI discloses wherein: a quantity of first crossing lines wired along the first side of the second direction with respect to the first non-display region and the second non-display region is same as a quantity of first crossing lines wired along the second side of the second direction with respect to the first non-display region and the second non-display region.
Regarding claim 4, FEI and Chen discloses claim 2, and Col. 4, line 50 to col. 5 line 3 and fig. 2 of Chen discloses wherein: a pixel drive circuit of the plurality of pixel drive circuits includes a data write module T2, a compensation moduleT3 , a first reset module T4( first transistor), a second reset module T4 (second transistor), a light-emitting control module T7 and a voltage adjustment module PVDD; the plurality of control lines includes a first control line connected to a control terminal of the first reset module, a second control line connected to a control terminal of the compensation module, a third control line connected to control terminals of the second reset module and the voltage adjustment module, a fourth control line connected to a control terminal of the data write module, and a light-emitting control line connected to the light-emitting control module; and two of the first control line, the second control line, the third control line and the light-emitting control line are connected to shift registers in the first frame region; and the other two of the first control line, the second control line, the third control line and the light-emitting control line are connected to shift registers in the second frame region.
As such it would have been obvious to form a panel comprising wherein: a pixel drive circuit of the plurality of pixel drive circuits includes a data write module T2, a compensation module , a first reset module, a second reset module, a light-emitting control module and a voltage adjustment module; the plurality of control lines includes a first control line connected to a control terminal of the first reset module, a second control line connected to a control terminal of the compensation module, a third control line connected to control terminals of the second reset module and the voltage adjustment module, a fourth control line connected to a control terminal of the data write module, and a light-emitting control line connected to the light-emitting control module; and two of the first control line, the second control line, the third control line and the light-emitting control line are connected to shift registers in the first frame region; and the other two of the first control line, the second control line, the third control line and the light-emitting control line are connected to shift registers in the second frame region in order to control the panel functions.
Regarding claim 5, fig. 2 of Chen discloses wherein: at least a part of fourth control lines connecting to first crossing lines is connected to the shift registers in the first frame region; and a remaining part of fourth control lines connecting to first crossing lines is connected to the shift registers in the second frame region.
Regarding claim 6, fig. 1 of Chen discloses further including: a plurality of pixel rows, wherein each pixel row includes a plurality of light-emitting elements; at least one of the first control line, the second control line, the third control line and the light-emitting control line is electrically connected to pixel drive circuits corresponding to light-emitting elements in N pixel rows respectively, wherein N2; and the fourth control line EMIT (in fig. 1) is only electrically connected to pixel drive circuits corresponding to light-emitting elements in a same pixel row.
Regarding claim 7, figs. 3-7 and of FEI discloses wherein: the first line segment includes a first terminal adjacent to the first non-display region and a second terminal adjacent to the second non-display region; and the resulting structure would have been one wherein at least one of the first control line, the second control line, the third control line, and the light-emitting control line in adjacent N pixel rows is electrically connected to first or second terminals of N corresponding first line segments.
Regarding claim 8, Chen discloses wherein: at least one of the first reset module and the compensation module includes a metal oxide transistor; and the resulting structure would have been one that discloses between the first non-display region and the second non-display region, along a thickness direction of the display panel, the metal oxide transistor includes an active layer, and a first gate electrode and a second gate electrode which are respectively on two sides of the active layer; and in a same metal oxide transistor, terminals of the first gate electrode and the second gate electrode are electrically connected with each other (see fig. 2 of Chen for T4 CMOS).
Regarding claim 9, figs. 1-22 of Chen discloses wherein: the first control line, the second control line, the third control line, the fourth control line and the light-emitting control line are distributed in at least two different film layers.
Regarding claim 10, fig. 7 of FEI discloses wherein: first crossing lines 1323 corresponding to the first control line, the second control line, the third control line and the light-emitting control line respectively (there exist some type of corresponding) include a first sub-first-crossing-line and a second sub-first-crossing-line (the different 1323); and a first end of a first line segment in the first control line, the second control line, the third control line and the light-emitting control line is connected to a second line segment on a side of the first non-display region away from the second non-display along the first direction through the first sub-first-crossing-line, and a second end of the first line segment is connected to a second line segment on a side of the second display region away from the first non-display region along the first direction through the second sub-first-crossing-line.
Regarding claim 11, it would have been obvious to form a panel comprising wherein: at least three pixel columns are arranged between the first non-display region and the second non-display region; the first line segment is electrically connected to the first sub-first-crossing-line through a first via and to the second sub-first-crossing-line through a second via; and along the first direction, a distance between the first via and the second via is greater than or equal to a total width of three consecutive pixel columns in order to maximize pixels in the display region.
Regarding claim 12, it would have been obvious to form a panel comprising wherein: a first line segment in the fourth control line is electrically connected to a second line segment on a side of the first line segment along the first direction through a first crossing line in order to make electrical connection from one side to the other side.
Regarding claim 13, it would have been obvious to form a panel comprising wherein: in first crossing lines connected to fourth control lines, at least a part of the first crossing lines is at the first side of the second direction with respect to the first line segment, and at least a part of the first crossing lines is at the second side of the second direction with respect to the first line segment; and in first crossing lines connected to at least one of the first control line, the second control line, the third control line and the light-emitting control line, at least a part of the first crossing lines is on at least one side of the first line segment along the second direction in order to meet the applicant circuit design.
Regarding claim 14, it would have been obvious to form a panel comprising wherein: at least three pixel columns are arranged between the first non-display region and the second non-display region; in first crossing lines, which are between the first non-display region and the second non-display region and correspond to the first control line, the second control line, the third control line, the fourth control line and the light-emitting control line, line segments extending along the second direction are within a range defined by three consecutive pixel columns in order to maximize pixels in the display region.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over FEI in view of Choi et al. 20210111231.
Regarding claim 25, FEI discloses 1, but does not discloses further including: a substrate and a transistor layer disposed on the substrate, wherein the transistor layer includes a first type transistor and a second type transistor; a first metal layer, a second metal layer, a gate metal layer, a capacitor metal layer, a third metal layer and a fourth metal layer, wherein a gate electrode of the first type transistor is in the first metal layer, a gate electrode of the second type transistor is in the gate metal layer, and source and drain electrodes of the first type transistor and the second type transistor are in the second metal layer; the capacitor metal layer is between the first metal layer and the second metal layer; the third metal layer is on a side of the second metal layer away from the substrate; and the fourth metal layer is on a side of the third metal layer away from the substrate; and at least a part of line segments in first crossing lines is in the fourth metal layer.
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However, fig. 8 of Choi disclose a display panel comprising a substrate 100 and a transistor layer disposed on the substrate, wherein the transistor layer includes a first type transistor T2 and a second type transistor T1 (fig. 6 of Choi); a first metal layer, a second metal layer, a gate metal layer, a capacitor metal layer, a third metal layer and a fourth metal layer, wherein a gate electrode of the first type transistor is in the first metal layer, a gate electrode of the second type transistor is in the gate metal layer, and source and drain electrodes of the first type transistor and the second type transistor are in the second metal layer; the capacitor metal layer is between the first metal layer and the second metal layer; the third metal layer is on a side of the second metal layer away from the substrate; and the fourth metal layer is on a side of the third metal layer away from the substrate; and at least a part of line segments in first crossing lines is in the fourth metal layer.
It would have been obvious to form a panel of FEI further including: a substrate and a transistor layer disposed on the substrate, wherein the transistor layer includes a first type transistor and a second type transistor; a first metal layer, a second metal layer, a gate metal layer, a capacitor metal layer, a third metal layer and a fourth metal layer, wherein a gate electrode of the first type transistor is in the first metal layer, a gate electrode of the second type transistor is in the gate metal layer, and source and drain electrodes of the first type transistor and the second type transistor are in the second metal layer; the capacitor metal layer is between the first metal layer and the second metal layer; the third metal layer is on a side of the second metal layer away from the substrate; and the fourth metal layer is on a side of the third metal layer away from the substrate; and at least a part of line segments in first crossing lines is in the fourth metal layer in order to form a complete display panel.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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