Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed January 23, 2026 has been entered. Claims 2, 4-8, 10-14, and 16-19 remain pending in the application. Examiner acknowledges amendments to the claims and related arguments which are addressed. Rejections have been maintained upon further search and consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 4-8, 10-14, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chou (U.S. Patent Pub. No. 2008/0307126) in view of Jo et al (U.S. Patent Pub. No. 2011/0126066), hereinafter referred to as Jo, and Shin (U.S. Patent Pub. No. 2008/0120464).
In regard to claim 2, Chou Paragraph 0005 teaches an SPI system including multiple devices on a bus (Chou Paragraph 0005, line 8) which contain memory (Fig. 1, item 124). Chou also teaches a method for utilizing this system including receiving commands based at least in part on a chip select signal (Paragraph 0005, lines 9-12).
Chou does not teach the remaining limitations of claim 2. However, Jo teaches a first device receiving a command for a read operation with a source address (Jo Paragraph 0077), followed by writing data from the read operation to a shared bus, and writing from the bus to a second memory device (Jo Paragraph 0078-0079). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosure of Chou with that of Jo in order to achieve direct memory transfer over SPI and improve the performance of multi-chip memory systems (Jo Paragraph 0007).
Jo does not disclose a single command simultaneously indicating a read and a write operation, however this is well known as a "MOVE" command in the art, and can be performed as a direct transfer between two linked devices according to the disclosure of Shin Paragraph 0011. If implemented in an SPI master-slave configuration as in Chou, data can be moved directly from one memory device to another (see Figs. 3-4 of Shin; Paragraph 0030, lines 1-6 disclose a move command comprising a read and write command, meaning data is stored based on a write command as well), achieving the claimed limitation. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the disclosure of Shin in order to allow for direct data transfer through a single move command and "perform data exchange rapidly" (Shin Paragraph 0052, line 5).
As for claim 4, the previously cited references teach the method of claim 2. Additionally, the disclosure of Chou requires chip enable before any data transmission from a controller to a memory device (Paragraph 0005, lines 9-12), which functionally achieves the claimed limitation.
As for claim 5, the previously cited references teach the method of claim 2. Additionally, Jo teaches a write command to the second device comprising a target address for writing (Jo Paragraph 0078), achieving the claimed limitation.
As for claim 6, the previously cited references teach the method of claim 2. Additionally, since the operation of SPI devices in Chou requires a chip enable (Chou Paragraph 0005, lines 9-12), and operate in accordance with a clock (Chou Paragraph 0005, lines 5-7), operations are always performed in accordance with a clock over SPI based at least in part on a chip select, achieving the claimed limitation.
As for claim 7, the previously cited references teach the method of claim 6, and Chou teaches a method wherein operation of a memory device over SPI in accordance with a clock is halted when a chip select signal is disabled (Chou Paragraph 0012; the SPI clock is ignored when chip select is disabled in order to perform a moving operation, lines 10-12), achieving the claimed limitation.
As for claim 8, Chou’s disclosure is a memory system (Fig. 1), and applicant is directed to the rejection of claim 2 for the remaining limitations of claim 8, as they are rejected based on the same rationale.
As for claim 14, Jo discloses forming a memory card (e.g. non-transitory computer readable medium) using the disclosed system (Jo Paragraph 0137), which would functionally include code for execution by some storage controller (e.g. processor) to carry out disclosed methods. Applicant is directed to the rejection of claim 2 for the remaining limitations of claim 14, as they are rejected based on the same rationale.
As for claims 10-13 and 16-19, Applicant is directed to the rejections of claims 3-7 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
Claims 2, 4-8, 10-14, and 16-19 are additionally rejected under 35 U.S.C. 103 as being unpatentable over Chou (U.S. Patent Pub. No. 2008/0307126) in view of Owens et al (U.S. Patent Pub. No. 2005/0138330), hereinafter referred to as Owens.
In regard to claim 2, Chou Paragraph 0005 teaches an SPI system including multiple devices on a bus (Chou Paragraph 0005, line 8) which contain memory (Fig. 1, item 124). Chou also teaches a method for utilizing this system including receiving commands based at least in part on a chip select signal (Paragraph 0005, lines 9-12).
Chou does not teach the remaining limitations of claim 2. However, Owens teaches a first memory device receiving a single command with a source address that simultaneously indicates a read operation for data and a write operation for the data at a second device (¶ 0023, lines 1-7, modules may be connected and disconnected i.e. not strictly internal and may be for ex. over serial ports (e.g. SPI); Fig. 4 move command; ¶ 0034; Fig. 5 transfer process; ¶ 0040; modules also include source and destination enable lines). A person of ordinary skill in the art could use SPI (like in Chou) for the data bus disclosed in Owens. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the disclosure of Chou with that of Owens in order to achieve direct memory transfer over SPI and benefit from techniques for higher performance and reduced power consumption (Owens ¶ 0020, lines 3-4).
As for claim 4, Chou and Owens teach the method of claim 2. Additionally, the disclosure of Chou requires chip enable before any data transmission from a controller to a memory device (Paragraph 0005, lines 9-12), which functionally achieves the claimed limitation.
As for claim 5, Chou and Owens teach the method of claim 2. Additionally, Chou teaches a write command to the second device comprising a target address for writing (¶ 0006), achieving the claimed limitation.
As for claim 6, Chou and Owens teach the method of claim 2. Additionally, since the operation of SPI devices in Chou requires a chip enable (Chou Paragraph 0005, lines 9-12), and operate in accordance with a clock (Chou Paragraph 0005, lines 5-7), operations are always performed in accordance with a clock over SPI based at least in part on a chip select, achieving the claimed limitation.
As for claim 7, Chou and Owens teach the method of claim 6, and Chou teaches a method wherein operation of a memory device over SPI in accordance with a clock is halted when a chip select signal is disabled (Chou Paragraph 0012; the SPI clock is ignored when chip select is disabled in order to perform a moving operation, lines 10-12), achieving the claimed limitation.
As for claim 8, Chou’s disclosure is a memory system (Fig. 1), and applicant is directed to the rejection of claim 2 for the remaining limitations of claim 8, as they are rejected based on the same rationale.
As for claim 14, Owens teaches a program memory used by the CPU 108 to control operations of device 100 in Fig. 1, which in regular operation would therefore include instructions for carrying out disclosed methods, acting as a computer-readable medium storing code executable to perform disclosed methods and achieving the claimed limitation. Applicant is directed to the rejection of claim 2 for the remaining limitations of claim 14, as they are rejected based on the same rationale.
As for claims 10-13 and 16-19, Applicant is directed to the rejections of claims 3-7 set forth above, as they are directed to the same limitations and therefore rejected based on the same rationale.
Response to Arguments
Applicant's arguments filed January 23, 2026 (starting page 6 of response) have been fully considered but they are not persuasive.
Arguments regarding independent claims 2, 8, and 14 were unpersuasive. The previously cited reference Shin has been cited to teach the concept of a move command used to indicate a read command at a receiving device and a write command to device(s) subsequent to the receiving device. As detailed in ¶ 0030, lines 1-7 disclose that the move command is specifically used by the memory interface unit to access a first storage device for reading, and to access a space in a second device where data is stored by a resulting command for writing. If implemented in combination with Jo and Chou as cited (for example, integrating the control and interfacing logic of Shin with that of the devices of Jo, because the buses of Jo would directly connect the storage devices to each other’s interfaces), a single move command would simultaneously indicate a read at one device and a subsequent write at a different device, even if the initiating move command later results in two separate commands. Additionally, the Applicant has not explained any reason that reference Owens fails to teach the claimed limitation. As such, rejections under 35 USC 103 are upheld.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZAKARIA MOHAMMED BELKHAYAT whose telephone number is (571)270-0472. The examiner can normally be reached Monday thru Thursday 7:30AM-5:30PM EST.
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/ZAKARIA MOHAMMED BELKHAYAT/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139