DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/24/2026 has been entered.
Response to Amendment
In response to communication filed on 08/24/2026, claims 1-6, 8-13, and 15-20 have been amended per the Applicant’s request. Claims 1-20 are presently pending in the application.
Response to Arguments
Applicant's arguments with respect to the claims have been considered but are moot in view of the new ground(s) of rejection. The independent claims have been amended to include new limitations that were never previously presented; thereby, these amendments change the scope of the claims. However, newly found prior art is applied.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kong et al. (NPL, “Recent Thermal Management Techniques for Microprocessors”, hereinafter “Kong”) in view of Liu et al. (NPL, “Dynamic Thermal Management for Multi-core Microprocessors Considering Transient Thermal Effects”, hereinafter “Liu”), and further in view of Vajapeyam (U.S. PG Pub. No. 2014/0181837 A1).
Regarding claim 1, Kong teaches one or more processors, comprising:
circuitry to:
determine that a combination of processing cores is operating according to one or more patterns of utilization associated with one or more historic thermal characteristics (Kong page 15 second to last paragraph, i.e., the entire paragraph, the Examiner interprets the thermal index of each core and thermal behaviors in the history window as the recited patterns)
Kong fails to explicitly teach the one or more historic thermal characteristics associated with a plurality of positions of the processing cores in the combination. However, in the same field of endeavor, Liu teaches the one or more historic thermal characteristics associated with a plurality of positions of the processing cores in the combination (Liu page 5, entire page). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kong by incorporating the teachings of Liu. The motivation would be for performing tasks migrations to reduce the temperature variations across the chip (Liu Abstract).
Kong as modified by Liu fails to explicitly teach control utilization of the combination of processing cores at least in part by scheduling threads on the processing cores to avoid the one or more patterns of utilization. However, in the same field of endeavor, Vajapeyam teaches control utilization of the combination of processing cores at least in part by scheduling threads on the processing cores to avoid the one or more patterns of utilization (Vajapeyam ¶0022). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kong and Liu by incorporating the teachings of Vajapeyam. The motivation would be for enhancing program performance by reducing local cache miss rates, proactively reducing the possibility of thermal hotspots, as well as by utilizing otherwise idle hardware (Vajapeyam ¶0022).
As to claim 2, Kong as modified by Liu and Vajapeyam also teaches the one or more processors of claim 1, the circuitry to cause the combination of processing cores to operate at a reduced capacity based at least on the determination (Vajapeyam ¶0022).
As to claim 3, Kong as modified by Liu and Vajapeyam also teaches the one or more processors of claim 1, the circuitry to load the historic thermal characteristics from a configuration file (Kong page 15, second to last paragraph, i.e., the default system configuration).
As to claim 4, Kong as modified by Liu and Vajapeyam also teaches the one or more processors of claim 1, wherein a central processing unit (CPU) comprises the combination of processing cores (Kong page 15, second to last paragraph, i.e., a multicore processor).
As to claim 5, Kong as modified by Liu and Vajapeyam also teaches the one or more processors of claim 1, wherein the combination of processing cores is masked based at least on the historic thermal characteristics of the combination of processing cores (Kong page 15, second to last paragraph, i.e., “If the thermal index of the core is high (more prone to be a hotspot), the value of this core is decreased faster” and “the scheduler gives higher priority to cores that have higher value”, i.e., masking the cores considered as hotspots).
As to claim 6, Kong as modified by Liu and Vajapeyam also teaches the one or more processors of claim 1, the circuitry to measure thermal characteristics based at least on an average temperature as measured by one or more thermal sensors located on a chip comprising the processing cores (Kong page 15 second paragraph, i.e., average temperature; and page 34 second paragraph, i.e., “The average temperature of each application is measured by per-core temperature sensors”), wherein the historic thermal characteristics are based at least on the measured thermal characteristics (Liu page 5, left column, second paragraph; and right column, Fig. 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kong by incorporating the teachings of Liu. The motivation would be for performing tasks migrations to reduce the temperature variations across the chip (Liu Abstract).
Claim 8 recites the limitations substantially similar to those of claim 1 and is similarly rejected.
Claim 9 recites the limitations substantially similar to those of claim 2 and is similarly rejected.
Claim 10 recites the limitations substantially similar to those of claim 3 and is similarly rejected.
As to claim 11, Kong as modified by Liu and Vajapeyam also teaches the system of claim 8, wherein a processor chip comprises the combination of processing cores (Kong page 5 second to last paragraph).
Claim 12 recites the limitations substantially similar to those of claim 5 and is similarly rejected.
Claim 13 recites the limitations substantially similar to those of claim 6 and is similarly rejected.
Claim 15 recites the limitations substantially similar to those of claim 1 and is similarly rejected.
Claim 16 recites the limitations substantially similar to those of claim 2 and is similarly rejected.
Claim 17 recites the limitations substantially similar to those of claim 3 and is similarly rejected.
Claim 18 recites the limitations substantially similar to those of claim 4 and is similarly rejected.
Claim 19 recites the limitations substantially similar to those of claim 5 and is similarly rejected.
As to claim 20, Kong as modified by Liu and Vajapeyam also teaches the machine-readable medium of claim 15, comprising further instructions, which if performed by one or more processors, cause the one or more circuits to cause one or more masked processing cores to enter a low power state (Kong page 32, second paragraph).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kong in view of Liu and Vajapeyam, and further in view of Alissa et al. (TW 202537366 A, hereinafter “Alissa”)
As to claim 7, Kong as modified by Liu and Vajapeyam teaches the one or more processors of claim 1, but fails to explicitly teach wherein the one or more patterns of utilization are associated with performance of a machine learning workload. However, in the same field of endeavor, Alissa teaches the one or more patterns of utilization are associated with performance of a machine learning workload (Alissa page 4, second to last paragraph). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Liu and Vajapeyam by incorporating the teachings of Alissa. The motivation would be to justify the cooling of multiple processing cores even when the cooling increases power consumption from the thermal management system (Alissa page 4, second to last paragraph).
As to claim 14, Kong as modified by Liu and Vajapeyam teaches the computer system of claim 8, but fails to explicitly teach wherein the one or more patterns of utilization are associated with performance of a machine learning workload by one or more processing cores of the combination of processing cores. However, in the same field of endeavor, Alissa teaches the one or more patterns of utilization are associated with performance of a machine learning workload by one or more processing cores of the combination of processing cores (Alissa page 4, second to last paragraph). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kong, Liu and Vajapeyam by incorporating the teachings of Alissa. The motivation would be to justify the cooling of multiple processing cores even when the cooling increases power consumption from the thermal management system (Alissa page 4, second to last paragraph).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER KHONG whose telephone number is (571)270-7127. The examiner can normally be reached Mon-Fri 8am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Rones can be reached at (571)272-4085. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER KHONG/Primary Examiner, Art Unit 2168
