DETAILED ACTION
Claims 1-9, 11-16, and 19-25 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 2/26/2026.
Maintained and New Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 12, 19, and 25 are rejected under 35 U.S.C. 102(a)(1 & 2) as being anticipated by Ould-Ahmed-Vall et al. (U.S. 2013/0339664).
As per claim 1:
Ould-Ahmed-Vall disclosed a system comprising:
a source data memory (Ould-Ahmed-Vall: Figures 1, 4A-B, and 9A-B elements 102 and 970, paragraphs 3, 33-34, 39-40, and 146-147)(The broadest reasonable interpretation of data memory is a memory that holds data. Memories such as disks, flash, solid state drives, RAMs, caches, and registers all are memories that hold data. The vector broadcast instruction can access input data elements from memory or source registers (i.e. source data memory) for broadcasting.);
a destination vector register having a register size (Ould-Ahmed-Vall: Figures 1, 4A-B, and 5A elements 102, 404A-B, and 506, paragraphs 6, 33-34, 39-40, and 53-54)(The vector broadcast instruction broadcasts an input data element to a destination register.); and
a processor (Ould-Ahmed-Vall: Figures 1 and 9B elements 100 and 990, paragraphs 4 and 147) configurable to:
receive a duplication instruction including first information specifying the source data memory, second information specifying a destination vector register, and third information specifying a size of a first data element in the source data memory (Ould-Ahmed-Vall: Figures 1, 4A-B, 6A, and 7A element 101 and 664, paragraph 2, 33-34, 39-40, 74, and 113)(The vector broadcast instruction specifies a source memory address/register for a first data element. The instruction specifies a destination register. The vector instruction includes a data element width field to indicate the size of the data element to be broadcasted.); and
execute the duplication instruction to cause the first data element to be loaded into the destination vector register a number of times equal to the register size of the destination vector register divided by the size of the first data element (Ould-Ahmed-Vall: Figures 1, 4A-B, and 5A-B elements 103, 502, and 514, paragraphs 2, 7, 33-34, 39-40, 53-54, and 57)(The vector broadcast instruction replicates the input data element to the destination register. An embodiment allows for no masking to the destination register.).
As per claim 12:
Claim 12 essentially recites the same limitations of claim 1. Therefore, claim 12 is rejected for the same reasons as claim 1.
As per claim 19:
Claim 19 essentially recites the same limitations of claim 1. Claim 19 additionally recites the following limitations:
a source data memory operable to store N data elements, wherein N is an integer greater than zero, and wherein each data element of the N data elements has a first size (Ould-Ahmed-Vall: Figures 1, 4A-B, and 9A-B element 970, paragraphs 3, 33-34, 39-40, and 146-147)(The broadest reasonable interpretation of data memory is a memory that holds data. Memories such as disks, flash, solid state drives, RAMs, caches, and registers all are memories that hold data. The vector broadcast instruction can access input data element(s) from memory or source registers (i.e. source data memory) for broadcasting. Figures 4A-B show an N value of one with data element sizes of 32-bits and 64-bits, respectfully.);
execute the duplication instruction to cause each data element of the N data elements to be loaded into consecutive locations in the destination vector register a number of times equal to the second register size of the destination vector register divided by a product of N and the first size (Ould-Ahmed-Vall: Figures 1, 4A-B, and 5A-B elements 103, 502, and 514, paragraphs 2, 7, 33-34, 39-40, 53-54, and 57)(The vector broadcast instruction replicates the input data element to the destination register. An embodiment allows for no masking to the destination register. The broadcasting fills out the destination register based on the number of data elements to replicate (i.e. N=1 in figures 4A-B), data element size, and destination register size.).
As per claim 25:
Ould-Ahmed-Vall disclosed the system of claim 1, wherein the duplication instruction is a single duplication instruction (Ould-Ahmed-Vall: Figures 4A-B, paragraphs 33 and 39), and wherein the processor is configurable to execute the single duplication instruction to:
cause the first data element to be loaded (Ould-Ahmed-Vall: Figures 1 and 4A-B elements 102, 401_A, and 401_B, paragraphs 2, 33-34, and 39-40)(The source data can be read/loaded from registers or memory.); and
cause the first data element to be duplicated the number of times equal to the register size of the destination vector register divided by the size of the first data element (Ould-Ahmed-Vall: Figures 1, 4A-B, and 5A-B elements 103, 502, and 514, paragraphs 2, 7, 33-34, 39-40, 53-54, and 57)(The vector broadcast instruction replicates the input data element to the destination register. An embodiment allows for no masking to the destination register. The broadcasting fills out the destination register based on the number of data elements to replicate (i.e. N=1 in figures 4A-B), data element size, and destination register size.).
New and maintained Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11-16, and 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ould-Ahmed-Vall et al. (U.S. 2014/0019712).
As per claim 1:
Ould-Ahmed-Vall disclosed a system comprising:
a source data memory (Ould-Ahmed-Vall: Figures 1-2 elements 201 and 205, paragraphs 41 and 45)(The broadest reasonable interpretation of data memory is a memory that holds data. Memories such as disks, flash, solid state drives, RAMs, caches, and registers all are memories that hold data. The VPCOMPRESSN instruction reads data elements from a source vector register (i.e. data memory).);
a destination vector register having a register size (Ould-Ahmed-Vall: Figures 1-2 elements 201 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction writes data elements to a destination vector register.); and
a processor configurable to:
receive a duplication instruction including first information specifying the source data memory, second information specifying a destination vector register, and third information specifying a size of a first data element in the source data memory (Ould-Ahmed-Vall: Figures 1-2 element 201, paragraph 41)(The VPCOMPRESSN instruction format includes a source register (i.e. source data memory), a destination register, and a prefix indicating the size of data elements.); and
execute the duplication instruction to cause the first data element to be loaded into the destination vector register a number of times equal to the register size of the destination vector register divided by the size of the first data element (Ould-Ahmed-Vall: Figures 1-2 elements 207-209, 303, 313 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction repeatedly writes data elements from a first source register to a destination vector register based on the corresponding number in a second source register. It would have been obvious to one of ordinary skill in the art that the first source data element can have a repeat number equal to or greater than the size of the destination register for the advantage of broadcasting a single data element to the entire destination register. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
As per claim 2:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein the third information occupies a less significant position in the duplication instruction than the first information, and wherein the third information occupies a less significant position in the duplication instruction than the second information (Ould-Ahmed-Vall: Figure 2 element 201, paragraphs 35 and 41)(Ould-Ahmed-Vall disclosed a format for a VPCOMPRESSN instruction that includes source registers, a destination register, and a prefix indicating a data element size, but doesn’t explicitly show the encoding order of elements within an encoded instruction. It would have been obvious to one of ordinary skill in the art to implement the prefix in the least significant position of the instruction encoding. In addition, according to “In re Japikse” (181 F.2d 1019, 86 USPQ 70 (CCPA 1950)), shifting the location of parts doesn’t give patentability over prior art.).
As per claim 3:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein the third information includes two bits in the duplication instruction, and wherein the two bits specify the size of the first data element (Ould-Ahmed-Vall: Figure 2 element 201, paragraphs 35 and 41)(The instruction prefix can indicate 32-bit and 64-bit data elements. Ould-Ahmed-Vall also discloses an embodiment allowing 8-bit and 16-bit data element sizes. It would have been obvious to one of ordinary skill in the art to implement a second prefix bit to further allow for selecting 8-bit and 16-bit data element sizes for replication.).
As per claim 4:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein the third information specifies the size of the first data element by specifying a byte, a half-word, a word, or a double word (Ould-Ahmed-Vall: Figure 2 element 201, paragraph 41)(The instruction prefix can indicate 32-bit and 64-bit data elements.).
As per claim 5:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein a first value of the third information specifies a byte length for the size of the first data element (Ould-Ahmed-Vall: Figure 2 element 201, paragraphs 35 and 41)(The instruction prefix can indicate 32-bit and 64-bit data elements. Ould-Ahmed-Vall also discloses an embodiment allowing 8-bit and 16-bit data element sizes. It would have been obvious to one of ordinary skill in the art to implement a second prefix bit to further allow for selecting 8-bit and 16-bit data element sizes for replication.).
As per claim 6:
Ould-Ahmed-Vall disclosed the system of claim 5,
wherein a second value of the third information specifies a half-word length for the size of the first data element (Ould-Ahmed-Vall: Figure 2 element 201, paragraphs 35 and 41)(The instruction prefix can indicate 32-bit and 64-bit data elements. Ould-Ahmed-Vall also discloses an embodiment allowing 8-bit and 16-bit data element sizes. It would have been obvious to one of ordinary skill in the art to implement a second prefix bit to further allow for selecting 8-bit and 16-bit data element sizes for replication.).
As per claim 7:
Ould-Ahmed-Vall disclosed the system of claim 6,
wherein a third value of the third information specifies a word length for the size of the first data element (Ould-Ahmed-Vall: Figure 2 element 201, paragraph 41)(The instruction prefix can indicate 32-bit and 64-bit data elements.).
As per claim 8:
Ould-Ahmed-Vall disclosed the system of claim 7,
wherein a fourth value of the third information specifies a double-word length for the size of the first data element (Ould-Ahmed-Vall: Figure 2 element 201, paragraph 41)(The instruction prefix can indicate 32-bit and 64-bit data elements.).
As per claim 9:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein to execute the duplication instruction, the processor is configurable to cause the first data element to be loaded into consecutive locations in the destination vector register the number of times equal to the register size of the destination vector register divided by the size of the first data element (Ould-Ahmed-Vall: Figures 1-3 elements 207-209, 303, 313 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction repeatedly writes data elements from a first source register to a destination vector register based on the corresponding number in a second source register. It would have been obvious to one of ordinary skill in the art that the first source data element can have a repeat number equal to or greater than the size of the destination register for the advantage of broadcasting a single data element to the entire destination register. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art. This causes the first source data element to be loaded into the destination register a number of times equal to dividing the destination register size by the data element size.).
As per claim 11:
Ould-Ahmed-Vall disclosed the system of claim 1,
wherein the source data memory is operable to store a plurality of data elements, and wherein the destination vector register is operable to store a plurality of data elements (Ould-Ahmed-Vall: Figure 1, paragraphs 35 and 41).
As per claim 12:
Claim 12 essentially recites the same limitations of claim 1. Therefore, claim 12 is rejected for the same reasons as claim 1.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 2. Therefore, claim 13 is rejected for the same reason(s) as claim 2.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 3. Therefore, claim 14 is rejected for the same reason(s) as claim 3.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 4. Therefore, claim 15 is rejected for the same reason(s) as claim 4.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 9. Therefore, claim 16 is rejected for the same reason(s) as claim 9.
As per claim 19:
Claim 19 essentially recites the same limitations of claim 1. Claim 19 additionally recites the following limitations:
a source data memory operable to store N data elements, wherein N is an integer greater than zero, and wherein each data element of the N data elements has a first size (Ould-Ahmed-Vall: Figures 1-2 elements 201 and 205, paragraphs 35, 41, and 45)(The broadest reasonable interpretation of data memory is a memory that holds data. Memories such as disks, flash, solid state drives, RAMs, caches, and registers all are memories that hold data. Source register 2 holds 8 data elements (i.e. A-H) of a first data element size.);
execute the duplication instruction to cause each data element of the N data elements to be loaded into consecutive locations in the destination vector register a number of times equal to the second register size of the destination vector register divided by a product of N and the first size (Ould-Ahmed-Vall: Figures 1-2 elements 207-209, 303, 313 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction repeatedly writes data elements from a first source register to a destination vector register based on the corresponding number in a second source register. It would have been obvious to one of ordinary skill in the art that the first source data element (i.e. N=1) can have a repeat number equal to or greater than the size of the destination register for the advantage of broadcasting a single data element to the entire destination register. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claims 6-7. Therefore, claim 20 is rejected for the same reason(s) as claims 6-7.
As per claim 21:
The additional limitation(s) of claim 21 basically recite the additional limitation(s) of claim 5. Therefore, claim 21 is rejected for the same reason(s) as claim 5.
As per claim 22:
The additional limitation(s) of claim 22 basically recite the additional limitation(s) of claim 8. Therefore, claim 22 is rejected for the same reason(s) as claim 8.
As per claim 23:
Ould-Ahmed-Vall disclosed the system of claim 1, wherein N equals one (Ould-Ahmed-Vall: Figures 1-2 elements 207-209, 303, 313 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction repeatedly writes data elements from a first source register to a destination vector register based on the corresponding number in a second source register. It would have been obvious to one of ordinary skill in the art that the first source data element (i.e. N=1) can have a repeat number equal to or greater than the size of the destination register for the advantage of broadcasting a single data element to the entire destination register. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
As per claim 24:
The additional limitation(s) of claim 24 basically recite the additional limitation(s) of claim 2. Therefore, claim 24 is rejected for the same reason(s) as claim 2.
As per claim 25:
Ould-Ahmed-Vall disclosed the system of claim 1, wherein the duplication instruction is a single duplication instruction (Ould-Ahmed-Vall: Figure 2 element 203-209, paragraphs 44-47)(The VPCOMPRESSN instruction is a single instruction.), and wherein the processor is configurable to execute the single duplication instruction to:
cause the first data element to be loaded (Ould-Ahmed-Vall: Figure 2 element 205, paragraph 45)(The source data can be read/loaded from a register.); and
cause the first data element to be duplicated the number of times equal to the register size of the destination vector register divided by the size of the first data element (Ould-Ahmed-Vall: Figures 1-2 elements 207-209, 303, 313 and 209, paragraphs 35, 41, and 47)(The VPCOMPRESSN instruction repeatedly writes data elements from a first source register to a destination vector register based on the corresponding number in a second source register. It would have been obvious to one of ordinary skill in the art that the first source data element can have a repeat number equal to or greater than the size of the destination register for the advantage of broadcasting a single data element to the entire destination register. In addition, according to “In re Rose” (105 USPQ 237 (CCPA 1955)), changes in size or range doesn’t give patentability over prior art.).
Response to Arguments
The arguments presented by Applicant in the response, received on 2/26/2026 are partially considered persuasive.
Applicant argues for claims 1, 12, and 19:
“The Office acknowledged that "figure 11 [of Applicant's application] shows a data memory that can be accessed by load instructions."2 Applicant agrees that Applicant's specification describes that, "As illustrated in FIG. 11, load and store instructions access memory here shown schematically as memory 1151."3 Applicant's specification also describes that "During execute 2 stage 1132 (E2) load instructions send the address to memory."4 Thus, FIG. 11 provides support for a system comprising a source data memory as recited in claim 1.
…
Applicant's specification describes that "The scr2 field specifies a register in a corresponding register file as the second source operand."6 Applicant's specification also describes that "The registers of local register file 525 can only be used as addresses in load/store instructions, not as store data or as sources for 64 bit arithmetic and logical instructions of load/store unit 515."7 Thus, Applicant's application provides support for a system comprising a source data memory and a processor configurable to "receive a duplication instruction including first information specifying the source data memory," as recited in claim 1.
As a result, Applicant's application provides full support for the amendments filed on June 30, 2025.”
This argument is found to be persuasive for the following reason. The previous non-final office action issued on 11/26/2025 made no written description rejections indicating a lack of support for any claim limitations. Thus, the examiner previously agreed with the above argument indirectly by not including any written description rejections or specification objections in the last office action.
Applicant argues for claims 1, 12, and 19:
“A user of Ould-Ahmed-Vall's processor would have needed to perform additional operations to configure the SRC register before executing the VPCOMPRESSN instruction, much less to execute the VPCOMPRESSN instruction in the specific manner proposed by the Office. However, according to Applicant's specification, the proposed approach combines the load and duplication operations into a single operation, whereas other approaches (e.g., Ould-Ahmed-Vall) require multiple instructions:
…
A person of ordinary skill in the art cannot execute the VPCOMPRESSN instruction described by Ould-Ahmed-Vall without first establishing the contents of the SRC2 register using a separate instruction. Therefore, Ould-Ahmed-Vall fails to disclose or suggest a system comprising a source data memory and a processor configured to "execute [a] duplication instruction to cause [a] first data element to be loaded into [a] destination vector register a number of times equal to [a] register size of the destination vector register divided by [a] size of the first data element," as recited in claim 1.
In addition, new claim 25 recites that "the duplication instruction is a single duplication instruction, and [] the processor is configurable to execute the single duplication instruction to: cause the first data element to be loaded; and cause the first data element to be duplicated a number of times equal to the register size of the destination vector register divided by the size of the first data element." As discussed above, Ould-Ahmed-Vall requires a separate instruction to fill the contents of the SRC2 register that is used in the VPCOMPRESSN instruction to copy the data elements stored in the SRC1 register. Thus, Ould-Ahmed-Vall fails to disclose or suggest a single duplication instruction to "cause [a] first data element to be loaded; and cause the first data element to be duplicated," as recited in claim 25.”
This argument is not found to be persuasive for the following reason. The VPCOMPRESSN instruction of the Ould-Ahmed-Vall (U.S. 2014/0019712) reference is a single instruction that replicates source register data into a destination register according to a second source register. The source registers are read/loaded from the register file for performing the instruction. The fact that the source register data read by the VPCOMPRESSN instruction was written by other instructions only indicates instruction dependencies. The VPCOMPRESSN instruction is still a single instruction that performs a replication function of source data into a destination register.
The VBROADCASTSD and VBROADCASTSS instructions of the other Ould-Ahmed-Vall (U.S. 2013/0339664) reference performs a slight variation on a similar concept. The 32-bit (i.e. VBROADCASTSS) or 64-bit (i.e. VBROADCASTSD) source data can originate from memory or from a register. This loaded data from memory or the register file is replicated into each and every data element position in the destination register. This instruction is a single instruction that causes the data element to be replicated in the destination register equal to the destination register size divided by the data element size. As noted in the rejection above, embodiments allow for no masking.
Thus, each Ould-Ahmed-Vall reference reads upon all of the independent claims, as well as newly added claim 25.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183