DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Arguments
Rejections under Double Patenting: Applicant’s amendment to claim 1 has overcome the rejections under Double Patenting with regard to parent application now Patent 10476818.
Regarding the Double Patenting rejections over claim 1 of U.S. Patent No. 11178076 B2 and claim 1 of U.S. Patent No. 11843550 B2, the Applicant’s arguments are considered but are moot as the amendment changes the scope of the claim. A new reference is applied addressing the modified limitation and the Double Patenting rejections in regard to the above parent applications are maintained.
Rejections under 35 USC 102
Applicant’s Argument: Applicant argues that the prior art fails to teach the amended limitation, previously recited in the alternative in claim 3, that has now been incorporated into claim 1.
Examiner’s Response: Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The amendment changes the scope of the invention. A new reference is applied in a new grounds of rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 1-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11178076 B2 (hereinafter ‘076) in view of Trivedi et al. (“Trivedi”) (US 7768939 B1). Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of ‘818
Claim 1 of ‘076
At least one non-transitory storage medium storing instructions for being executed by programmable circuitry, the programmable circuitry for being used in association with network interface circuitry, the instructions, when executed, by the programmable circuitry resulting in performance of operations comprising: subjecting access to at least one queue to at least one spin lock, the at least one queue being for use in processing of packet data received via the network interface circuitry, the at least one spin lock to be provided in response to at least one request of at least one entity; and determining whether to indicate occurrence of at least one other request based at least in part upon whether the at least one other request is made while the access to the at least one queue is subject to the at least one spin lock, the at least one other request being for obtaining of the at least one spin lock, wherein: the at least one requesting entity is associated with one or more sockets: and at least one other requesting entity is associated with one or more other sockets and is to make the at least one other request
At least one non-transitory storage medium storing instructions for being executed by programmable circuitry, the programmable circuitry for being used in association with network interface circuitry, the instructions, when executed, by the programmable circuitry resulting in performance of operations comprising: subjecting access to at least one queue to at least one spin lock, the at least one queue being for use in processing of packet data received via the network interface circuitry, the at least one spin lock to be provided in response to at least one request of at least one entity while the at least one requesting entity is in a polling state of the at least one requesting entity; determining whether to indicate occurrence of at least one other request based at least in part upon whether the at least one other request is made while the access to the at least one queue is subject to the at least one spin lock, the at least one other request being for obtaining of the at least one spin lock, the at least one other request to be made by at least one other entity while the at least one other entity is in a polling state of the at least one other entity; and releasing the at least one spin lock; wherein: the at least one entity is associated with at least one socket; and the network interface circuitry is for use in media access control (MAC) layer processing.
Claim 1 teaches multiple connections but does not teach sockets for the other entity.
Trivedi teaches these connections are sockets, thus at least one requesting entity is associated with one or more sockets, and at least one other requesting entity is associated with one or more other sockets [Column 9 ll 25-53 Figure 2, shows sockets pertaining to a connection to a device, thus one entity pertains to one socket and a different entity pertains to a different socket, ].
It would have been obvious to one of ordinary skill in the art before the invention to specify sockets associated with the connection. Claim 1 teaches the connections to other entities and it is known in the art the connections comprise sockets as in Trivedi who teaches TCP sockets are used to manage TCP connections see Column 1.
Claims 2-4, 6-9, 11-14 rejected based on claim 1 of ‘076 in view of Trivedi.
Claim 5 rejected based on claim 6 of ‘076 in view of Trivedi.
Claim 1-15 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 11843550 B2 (hereinafter ‘550) in view of Trivedi et al. (“Trivedi”) (US 7768939 B1). Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim 1 of ‘818
Claim 1 of ‘550
At least one non-transitory storage medium storing instructions for being executed by programmable circuitry, the programmable circuitry for being used in association with network interface circuitry, the instructions, when executed, by the programmable circuitry resulting in performance of operations comprising: subjecting access to at least one queue to at least one spin lock, the at least one queue being for use in processing of packet data received via the network interface circuitry, the at least one spin lock to be provided in response to at least one request of at least one entity; and determining whether to indicate occurrence of at least one other request based at least in part upon whether the at least one other request is made while the access to the at least one queue is subject to the at least one spin lock, the at least one other request being for obtaining of the at least one spin lock, wherein: the at least one requesting entity is associated with one or more sockets: and at least one other requesting entity is associated with one or more other sockets and is to make the at least one other request
At least one non-transitory storage medium storing instructions for being executed by programmable circuitry, the programmable circuitry for being used in association with network interface circuitry, the instructions, when executed, by the programmable circuitry resulting in performance of operations comprising: subjecting access to at least one queue to at least one spin lock, the at least one queue being for use in processing of packet data received via the network interface circuitry, the at least one spin lock to be provided in response to at least one request of at least one entity while the at least one requesting entity is in a polling state of the at least one requesting entity; determining whether to indicate occurrence of at least one other request based at least in part upon whether the at least one other request is made while the access to the at least one queue is subject to the at least one spin lock, the at least one other request being for obtaining of the at least one spin lock, the at least one other request to be made by at least one other entity while the at least one other entity is in a polling state of the at least one other entity; and releasing the at least one spin lock; wherein: the at least one entity is associated with at least one socket; the network interface circuitry is for use in media access control (MAC) layer processing and/or physical (PHY) layer processing; and the instructions are associated, at least in part, with a driver entity.
Claim 1 teaches multiple connections but does not teach sockets for the other entity.
Trivedi teaches these connections are sockets, thus at least one requesting entity is associated with one or more sockets, and at least one other requesting entity is associated with one or more other sockets [Column 9 ll 25-53 Figure 2, shows sockets pertaining to a connection to a device, thus one entity pertains to one socket and a different entity pertains to a different socket].
It would have been obvious to one of ordinary skill in the art before the invention to specify sockets associated with the connection. Claim 1 teaches the connections to other entities and it is known in the art the connections comprise sockets as in Trivedi who teaches TCP sockets are used to manage TCP connections see Column 1.
Claims 2-4, 6-9, 11-14 rejected based on claim 1 of ‘550 in view of Trivedi.
Claim 5 rejected based on claim 5 of ‘550 in view of Trivedi.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-15 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hagersten (EP 0817042 A2) in view of Trivedi et al. (“Trivedi”) (US 7768939 B1).
Regarding claim 1, Hagersten teaches:
At least one non-transitory storage medium storing instructions for being executed by programmable circuitry, the programmable circuitry for being used in association with network interface circuitry, the instructions, when executed, by the programmable circuitry resulting in performance of operations comprising:
subjecting access to at least one queue to at least one spin lock, the at least one queue being for use in processing of packet data received via the network interface circuitry [page 17-20, Figure 14-15a shows, the queue via home agent control unit 410 for processing requests via queues 404, 402, subject to spin lock operations, the queue being for processing packets received from the network via the queues, RTSs, RTOs, see “during operation home agent 102 receives transaction requests from network 14 through input header queue 84.” Following this, “For this example, it is assumed that each of RTS transaction requests RTS(1)-RTS(7) correspond to requests from spinning processors that are each contending for access to the same locked memory region. It is further assumed that the RTO transaction RTO(1) is an unrelated transaction request.”], the at least one spin lock to be provided in response to at least one request of at least one entity [page 17-20 show requests from network considered to include a requesting entity, Figure 14-15a shows request RTO(2) Figure 15(b) corresponding to at least one request, and the spin lock provided to this high priority queue 402, “ When the transaction for request RTS(3) completes, request RTO(2) will be passed to home agent control unit 410 through transaction blocking unit 408. Since RTO(2) bypasses requests RTS(4)-RTS(7) via the high priority queue 402, it is serviced before the servicing of RTS(4)-RTS(7). Accordingly, the lock bit for the memory region will be set, and the processors issuing RTS(4)-RTS(7) will not detect a free lock and will not initiate atomic test-and-set operations.” Wherein lock bit being set initiates spin lock “If the test of the lock bit indicates that the memory region is currently locked, the process initiates a software loop wherein the lock bit is continuously read until the lock bit is detected as cleared, at which time the process reinitiates the atomic test-and-set operation” see page 3];
and determining whether to indicate occurrence of at least one other request based at least in part upon whether the at least one other request is made while the access to the at least one queue is subject to the at least one spin lock, the at least one other request being for obtaining of the at least one spin lock [page 17-20, Figure 15B, other requests being RTSs received, placed into queue 404, corresponding to “determining whether to indicate occurrence” and this is based on RTSs made while spin lock in effect for queue 402, “If the test of the lock bit indicates that the memory region is currently locked, the process initiates a software loop wherein the lock bit is continuously read until the lock bit is detected as cleared, at which time the process reinitiates the atomic test-and-set operation” see page 3, the initiating of atomic test-and-set operations being “indicate occurrence”], wherein the at least one requesting entity is associated with a connection [page 17-20, Figure 14-15a shows request RTO(2) Figure 15(b) corresponding to at least one request, wherein requests received via network 14, shown in Figure 1 to include plurality of entities SMP nodes]; and the at least one other requesting entity is associated with a connection [page 17-20, Figure 15B, other requests being RTSs received, placed into queue 404, corresponding to any of entities as in Figure 1 including a second entity] and is to make the at least one other request [page 17-20, Figure 15B, other requests being RTSs received, placed into queue 404, corresponding to any of entities as in Figure 1 including a second entity].
Hagersten teaches multiple connections as in Figure 1 wherein over the network 14 requests from the other nodes may be received as in page 17-20 but does not teach sockets.
Trivedi teaches these connections are sockets, thus at least one requesting entity is associated with one or more sockets, and at least one other requesting entity is associated with one or more other sockets [Column 9 ll 25-53 Figure 2, shows sockets pertaining to a connection to a device, thus one entity pertains to one socket and a different entity pertains to a different socket].
It would have been obvious to one of ordinary skill in the art before the invention to specify sockets associated with the connection. Hagersten shows in Figure 1 connections and it is known in the art the connections comprise sockets as in Trivedi who teaches TCP sockets are used to manage TCP connections see Column 1.
Regarding claim 2, Hagersten-Trivedi teaches:
The at least one non-transitory storage medium of claim 1, wherein: the at least one spin lock is to be provided in response to the at least one request of the at least one requesting entity while the at least one requesting entity is in a polling state of the at least one requesting entity [Hagersten page 17-20, Figure 14-15a shows request RTO(2) Figure 15(b) corresponding to at least one request from one requesting entity, and the spin lock subjected to queue 404, in 402, which triggers spin lock on queue 404, “ When the transaction for request RTS(3) completes, request RTO(2) will be passed to home agent control unit 410 through transaction blocking unit 408. Since RTO(2) bypasses requests RTS(4)-RTS(7) via the high priority queue 402, it is serviced before the servicing of RTS(4)-RTS(7). Accordingly, the lock bit for the memory region will be set, and the processors issuing RTS(4)-RTS(7) will not detect a free lock and will not initiate atomic test-and-set operations.” Wherein lock bit being set initiates spin lock, during which “If the test of the lock bit indicates that the memory region is currently locked, the process initiates a software loop wherein the lock bit is continuously read until the lock bit is detected as cleared, at which time the process reinitiates the atomic test-and-set operation” see page 3, continuously reading corresponding to a polling state];
and/or the at least one other request is to be made by at least one other entity while the at least one other requesting entity is in a polling state of the at least one other entity.
Regarding claim 3, Hagersten-Trivedi teaches:
The at least one non-transitory storage medium of claim 1, wherein: the network interface circuitry is for use in media access control (MAC) layer processing and/or physical (PHY) layer processing; the instructions are associated, at least in part, with a Linux operating system- associated driver entity;
and/or the programmable circuitry comprises at least one central processing unit (CPU) core of a host computer [Hagersten page 6, figure 1, system associated with SMP nodes with multiple processors 16A-16B contending for access to memory regions].
Regarding claim 4, Hagersten-Trivedi teaches:
The at least one non-transitory storage medium of claim 1, wherein the operations also comprise one or more of: releasing the at least one spin lock [Hagersten page 3 shows lock may be released, “For both implementations, when a memory region corresponding to a contended spin-lock is released, all N spinning processors will generate RTS transactions bound for the cache line.”]; and/or determining, based at least in part upon whether the at least one queue contains remaining packet data to be processed, whether to enter an idle state.
Regarding claim 5, Hagersten-Trivedi teaches:
The at least one non-transitory storage medium of claim 1, wherein: the determining whether to indicate the occurrence of the at least one other request is based, at least in part, upon whether at least one other requesting entity successfully obtained the at least one spin lock as result of making the at least one other request [Hagersten page 17-20, Figure 15B, other requests being RTSs received and placed into queue 404 corresponding to “indicate the occurrence of the at least one other request” and this placement in queue is based on queue 404 detecting lock bit for access and not obtaining spin lock, “If the test of the lock bit indicates that the memory region is currently locked, the process initiates a software loop wherein the lock bit is continuously read until the lock bit is detected as cleared, at which time the process reinitiates the atomic test-and-set operation” see page 3];
and/or when the instructions are associated with a driver entity that is for use in association with a new application programming interface (NAPI) compliant interface.
Regarding claims 6-15, see similar rejections for claim 1-5 which teaches the physical structure performing the corresponding method.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY L. VOGEL whose telephone number is (303)297-4322. The examiner can normally be reached Monday-Friday 8AM-4:30 PM MT.
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/JAY L VOGEL/Primary Examiner, Art Unit 2478