DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 21-25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2021/0027671 by Lee et al. (“Lee”) in view of U.S. Pub. No. 2020/0312244 by Yang et al. (“Yang”).
As to claim 9, Lee discloses a display device (Lee, stretchable display device 100, Figure 1), comprising:
a stretchable lower substrate (Lee, The lower substrate DS is a substrate which supports and protects several components of the stretchable display device 100. The lower substrate DS which is a soft substrate or a flexible substrate may be configured by an insulating material which is pliable, bendable or stretchable. ¶ [0041]);
a pattern layer disposed on the lower substrate and including a plurality of plate patterns (Lee, Referring to FIGS. 1 and 2, a plurality of sub pixels SPX which configures the plurality of pixels PX is disposed on the plurality of first substrates ST1, Figures 1 and 2, ¶ [0059]) and a plurality of line patterns (Lee, Referring to FIG. 2, the plurality of connection substrates CS has a curved shape on a flat surface. Figure 2, ¶ [0062]);
a plurality of pixels disposed on the plurality of plate patterns (Lee, Referring to FIGS. 1 and 2, a plurality of sub pixels SPX which configures the plurality of pixels PX is disposed on the plurality of first substrates ST1, Figures 1 and 2, ¶ [0059]);
a plurality of connection lines disposed on the plurality of line patterns to connect the plurality of pixels (Lee, Referring to FIG. 2, the plurality of connection substrates CS has a curved shape on a flat surface. Figure 2, ¶ [0062])(Lee, Referring to FIGS. 1 and 2, the plurality of connection substrates CS may be disposed between the plurality of first substrates ST1, between the plurality of second substrates ST2, or between the plurality of first substrates ST1 and the plurality of second substrates ST2. The plurality of connection substrates CS may be substrates which connect adjacent first substrates ST1, adjacent second substrates ST2, or the first substrate ST1 and the second substrate ST2 which are adjacent to each other. Figures 1 and 2, ¶ [0061]) (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 and the plurality of upper connection lines 180 may be disposed below and above the plurality of connection substrates CS, respectively. The plurality of connection substrates CS, the plurality of lower connection lines 120, and the plurality of upper connection lines 180 which overlap each other may be formed to have the same shape. Figures 2 and 3, ¶ [0095]); and
pixel circuits formed in the plurality of pixels (Lee, sub pixels SPX, Figures 1 and 2),
Lee does not expressly teach
each of the pixel circuits including a voltage divider connected between a high potential voltage line and a low potential voltage line.
Yang teaches a pixel circuit and display device wherein
each of the pixel circuits (Yang, pixel circuit, Figure 5) including a voltage divider (Yang, voltage divider sub-circuit 12, Figure 5) connected between a high potential voltage line (Yang, power source positive terminal Vdd, Figure 5) and a low potential voltage line (Yang, power source negative terminal Vss, Figure 5). As shown in figure 5 of Yang, the voltage divider sub-circuit 12 is connected between the VDD and VSS through various intervening components.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee’s pixel circuits to include Yang’s voltage divider because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Lee’s pixel circuits as modified by Yang’s voltage divider is known to yield a predictable result of providing a controlled voltage to the LED since this improves the control capabilities of the pixel. Thus, a person of ordinary skill would have appreciated including in Lee’s pixel circuits the ability to do Yang’s voltage divider since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Thus, Lee, as modified by Yang, teaches the voltage divider in a pixel circuit which is connected to the positive and negative power source terminals.
As to claim 21, Lee discloses a display device (Lee, stretchable display device 100, Figure 1), comprising:
a flexible substrate (Lee, The lower substrate DS is a substrate which supports and protects several components of the stretchable display device 100. The lower substrate DS which is a soft substrate or a flexible substrate may be configured by an insulating material which is pliable, bendable or stretchable. ¶ [0041]);
a plurality of island shaped structures disposed on the flexible substrate (Lee, Referring to FIGS. 1 and 2, a plurality of sub pixels SPX which configures the plurality of pixels PX is disposed on the plurality of first substrates ST1, Figures 1 and 2, ¶ [0059]), each of the plurality of island shaped structures being spaced apart from each other and including a stack of multiple layers (Lee, upper substrate US and lower substrate DS, Figure 1); As shown in figures 1 and 2 of Lee, the first substrates ST1 are spaced from each other.
a plurality of pixels disposed on or in the plurality of island shaped structures (Lee, Referring to FIGS. 1 and 2, a plurality of sub pixels SPX which configures the plurality of pixels PX is disposed on the plurality of first substrates ST1, Figures 1 and 2, ¶ [0059]),
wherein each pixel among the plurality of pixels includes sub pixels (Lee, sub pixels SPX, Figures 1 and 2), and
Lee does not expressly disclose
each of the sub pixels includes a voltage divider configured to internally generate a reference voltage for the corresponding sub pixel.
Yang teaches a pixel circuit and display device wherein
each of the sub pixels (Yang, pixel circuit, Figure 5) includes a voltage divider (Yang, voltage divider sub-circuit 12, Figure 5) configured to internally generate a reference voltage for the corresponding sub pixel (Yang, The voltage divider sub-circuit 12 is configured to regulate an equivalent resistance value of the voltage divider sub-circuit 12 in an output path through which the drive current is output to the light-emitting device, based on a voltage division control signal received by the voltage division control signal terminal SC and applied common voltage such that initialization of the pixel circuit is implemented. ¶ [0063 and 0119]).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee’s pixel circuits to include Yang’s voltage divider because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Lee’s pixel circuits as modified by Yang’s voltage divider is known to yield a predictable result of providing a controlled voltage to the LED since this improves the control capabilities of the pixel. Thus, a person of ordinary skill would have appreciated including in Lee’s pixel circuits the ability to do Yang’s voltage divider since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Thus, Lee, as modified by Yang, teaches the voltage divider in a pixel circuit which supplies a signal to the LED.
As to claim 22, Lee, as modified by Yang, teaches the display device wherein one row of pixels included in the plurality of island shaped structures are commonly connected to a same scan signal line (Lee, the plurality of sub pixels may be connected to various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, a compensation signal line. ¶ [0044]) (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 is disposed on the lower substrate DS. The plurality of lower connection lines 120 may refer to wiring lines which electrically connect the plurality of lower pads 130 which is adjacent to each other. The plurality of lower connection lines 120 may be configured by one of various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, and a compensation signal line, but is not limited thereto. Figures 2 and 3, ¶ [0096]).
As to claim 23, Lee, as modified by Yang, teaches the display device wherein one row of pixels included in the plurality of island shaped structures are commonly connected to a same emission signal line (Lee, the plurality of sub pixels may be connected to various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, a compensation signal line. ¶ [0044]) (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 is disposed on the lower substrate DS. The plurality of lower connection lines 120 may refer to wiring lines which electrically connect the plurality of lower pads 130 which is adjacent to each other. The plurality of lower connection lines 120 may be configured by one of various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, and a compensation signal line, but is not limited thereto. Figures 2 and 3, ¶ [0096]).
As to claim 24, Lee, as modified by Yang, teaches the display device further comprising:
a plurality of first connection lines extending in a first direction and being connected between a first pair of adjacent island shaped structures among the plurality of island shaped structures (Lee, first upper connection line 181, Figure 2); and
a plurality of second connection lines extending in a second direction and being connected between a second pair of adjacent island shaped structures among the plurality of island shaped structures, the second direction being different than the first direction (Lee, second upper connection line 182, Figure 2)(Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 and the plurality of upper connection lines 180 may be disposed below and above the plurality of connection substrates CS, respectively. The plurality of connection substrates CS, the plurality of lower connection lines 120, and the plurality of upper connection lines 180 which overlap each other may be formed to have the same shape. Figures 2 and 3, ¶ [0095]),
wherein the plurality of first connection lines and the plurality of second connection lines include at one of a curvy shape, a zig-zag shape, a wavy shape, a sinusoidal shape or a coiled shape (Lee, the plurality of connection substrates CS may have a sine wave shape. However, the shape of the plurality of connection substrates CS is not limited thereto and the plurality of connection substrates CS may extend with a zigzag pattern or may be formed with various shapes such as a shape extended by connecting a plurality of rhombus-shaped substrates at vertexes. Figure 2, ¶ [0062]).
As to claim 25, Lee, as modified by Yang, teaches the display device wherein the plurality of first connection lines include a low potential voltage line, a scan signal line, a high potential voltage line and an emission signal line (Lee, the plurality of sub pixels may be connected to various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, a compensation signal line. ¶ [0044]), and
wherein the plurality of second connection lines include a plurality of data lines (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 is disposed on the lower substrate DS. The plurality of lower connection lines 120 may refer to wiring lines which electrically connect the plurality of lower pads 130 which is adjacent to each other. The plurality of lower connection lines 120 may be configured by one of various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, and a compensation signal line, but is not limited thereto. Figures 2 and 3, ¶ [0096]).
As to claim 27, Lee, as modified by Yang, teaches wherein areas between the plurality of island shaped structures have a modulus of elasticity that is greater than a modulus of elasticity of the plurality of island shaped structures (Lee, Modulus of the plurality of first substrates ST1 and the plurality of second substrates ST2 may be higher than that of the lower substrate DS. In some embodiments, the modulus is an elastic modulus which represents a ratio being deformed by a stress with respect to a stress applied to the substrate. For instance, the modulus of elasticity may be the ratio between stress and strain. The higher the modulus, the higher a degree of hardness. Therefore, the plurality of first substrates ST1 and the plurality of second substrates ST2 may be a plurality of rigid substrates having larger rigidity as compared with the lower substrate DS. For example, the modulus of the plurality of first substrates ST1 and the plurality of second substrates ST2 may be 1000 times higher than the modulus of the lower substrate DS, ¶ [0049]). Lee teaches the substrates ST1 and ST2 as being more rigid than the lower substrate DS. Therefore, the areas between the substrates are more elastic than the substrates.
Claims 10, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2021/0027671 by Lee et al. (“Lee”) in view of U.S. Pub. No. 2020/0312244 by Yang et al. (“Yang”), and in further view of U.S. Pub. No. 2020/0118494 by Park et al. (“Park”).
As to claim 10, Lee, as modified by Yang, teaches the display device wherein each of the pixel circuits includes:
a light emitting diode (Yang, organic light-emitting diode D1, Figure 5);
However, Lee, as modified by Yang, does not expressly teach the rest of the pixel circuit including
a driving transistor including a gate electrode connected to a first node that is connected between the high potential voltage line and a second node, the driving transistor being configured to generate a driving current flowing from the high potential voltage line to the low potential voltage line to drive the light emitting diode;
a storage capacitor connected between the first node and a third node; a first transistor connected between the third node and one of a plurality of data lines, the first transistor including a gate electrode connected to a scan signal line;
a second transistor connected between the first node and the second node, the second transistor including a gate electrode connected to the scan signal line;
a third transistor connected between the third node and a fourth node, the third transistor including a gate electrode connected to an emission signal line;
a fourth transistor connected between the second node and a fifth node corresponding to the first electrode of the light emitting diode, the fourth transistor including a gate electrode connected to the emission signal line; and
a fifth transistor connected between the fourth node and the fifth node, the fifth transistor including a gate electrode connected to the scan signal line.
Park teaches a display device including
a driving transistor (Park, driving transistor DRT, Figure 2) including a gate electrode connected to a first node (Park, node N3, Figure 2) that is connected between the high potential voltage line (Park, driving voltage VDD, Figure 2) and a second node (Park, node N2, Figure 2), the driving transistor being configured to generate a driving current flowing from the high potential voltage line to the low potential voltage line to drive the light emitting diode (Park, The driving transistor (DRT) is a transistor that supplies a driving current to a light emitting device (EL) to drive the light emitting device (EL). Figure 2, ¶ [0110])(Park, The driving transistor (DRT) can be electrically connected between a driving voltage line (DVL) and the second node (N2). Particularly, the source node or the drain node of the driving transistor (DRT) can be electrically connected to the driving voltage line (DVL) at a driving voltage node (Nvd). Figure 2, ¶ [0111]);
a storage capacitor (Park, storage capacitor Cst, Figure 2) connected between the first node (Park, node N3, Figure 2) and a third node (Park, node N4, Figure 2);
a first transistor (Park, first scan transistor SCT1, Figure 2) connected between the third node (Park, node N4, Figure 2) and one of a plurality of data lines (Park, data lines DL, Figure 2), the first transistor including a gate electrode connected to a scan signal line (Park, scan lines SCL, Figure 2);
a second transistor (Park, second scan transistor SCT2, Figure 2) connected between the first node (Park, node N3, Figure 2) and the second node (Park, node N2, Figure 2), the second transistor including a gate electrode connected to the scan signal line (Park, scan lines SCL, Figure 2);
a third transistor (Park, second light emission control transistor EMT2, Figure 2) connected between the third node (Park, node N4, Figure 2) and a fourth node (Park, node Nr, Figure 2), the third transistor including a gate electrode connected to an emission signal line (Park, light emission control lines EML, Figure 2);
a fourth transistor (Park, first light emission control transistor EMT1, Figure 2) connected between the second node (Park, node N2, Figure 2) and a fifth node (Park, node N1, Figure 2) corresponding to the first electrode of the light emitting diode (Park, light emitting device EL, Figure 2), the fourth transistor including a gate electrode connected to the emission signal line (Park, light emission control lines EML, Figure 2); and
a fifth transistor (Park, third scan transistor SCT3, Figure 2) connected between the fourth node (Park, node Nr, Figure 2) and the fifth node (Park, node N1, Figure 2), the fifth transistor including a gate electrode connected to the scan signal line (Park, scan lines SCL, Figure 2).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Lee’s pixel circuit to include Park’s pixel circuit because such a modification is the result of simple substitution of one known element for another producing a predictable result. More specifically, Lee’s pixel circuit and Park’s pixel circuit perform the same general and predictable function, the predictable function being providing a pixel circuit for a display device. Since each individual element and its function are shown in the prior art, albeit shown in separate references, the difference between the claimed subject matter and the prior art rests not on any individual element or function but in the very combination itself – that is in the substitution of Lee’s pixel circuit by replacing it with Park’s pixel circuit. Thus, the simple substitution of one known element for another producing a predictable result renders the claim obvious.
Thus, Lee, as modified by Yang and Park, teaches the pixel circuit with the voltage divider.
As to claim 18, Lee, as modified by Yang and Park, teaches the display device wherein the plurality of connection lines include:
a plurality of first connection lines extending in a first direction (Lee, first upper connection line 181, Figure 2); and
a plurality of second connection lines extending in a second direction different than the first direction (Lee, second upper connection line 182, Figure 2)(Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 and the plurality of upper connection lines 180 may be disposed below and above the plurality of connection substrates CS, respectively. The plurality of connection substrates CS, the plurality of lower connection lines 120, and the plurality of upper connection lines 180 which overlap each other may be formed to have the same shape. Figures 2 and 3, ¶ [0095]).
As to claim 19, Lee, as modified by Yang and Park, teaches the display device wherein the plurality of first connection lines includes the scan signal line, the emission signal line, the high potential voltage line, and the low potential voltage line (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 is disposed on the lower substrate DS. The plurality of lower connection lines 120 may refer to wiring lines which electrically connect the plurality of lower pads 130 which is adjacent to each other. The plurality of lower connection lines 120 may be configured by one of various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, and a compensation signal line, but is not limited thereto. Figures 2 and 3, ¶ [0096]) and
wherein the plurality of second connection lines include the plurality of data lines (Lee, Referring to FIGS. 2 and 3, the plurality of lower connection lines 120 is disposed on the lower substrate DS. The plurality of lower connection lines 120 may refer to wiring lines which electrically connect the plurality of lower pads 130 which is adjacent to each other. The plurality of lower connection lines 120 may be configured by one of various wiring lines such as a gate line, a data line, an emission signal line, a high potential power line, a low potential power line, a reference voltage line, and a compensation signal line, but is not limited thereto. Figures 2 and 3, ¶ [0096]).
Allowable Subject Matter
Claims 1-8 are allowed.
The following is an examiner’s statement of reasons for allowance:
As to claim 1, Park (U.S. Pub. No. 2020/0118494) discloses a pixel (Park, circuit of a sub-pixel (SP), Figure 2) comprising:
a light emitting diode (Park, light emitting device EL, Figure 2);
a driving transistor (Park, driving transistor DRT, Figure 2) including a gate electrode connected to a first node (Park, node N3, Figure 2) that is connected between the high potential voltage line (Park, driving voltage VDD, Figure 2) and a second node (Park, node N2, Figure 2), the driving transistor being configured to generate a driving current flowing from the high potential voltage line to the low potential voltage line to drive the light emitting diode (Park, The driving transistor (DRT) is a transistor that supplies a driving current to a light emitting device (EL) to drive the light emitting device (EL). Figure 2, ¶ [0110])(Park, The driving transistor (DRT) can be electrically connected between a driving voltage line (DVL) and the second node (N2). Particularly, the source node or the drain node of the driving transistor (DRT) can be electrically connected to the driving voltage line (DVL) at a driving voltage node (Nvd). Figure 2, ¶ [0111]);
a storage capacitor (Park, storage capacitor Cst, Figure 2) connected between the first node (Park, node N3, Figure 2) and a third node (Park, node N4, Figure 2);
a first transistor (Park, first scan transistor SCT1, Figure 2) connected between the third node (Park, node N4, Figure 2) and one of a plurality of data lines (Park, data lines DL, Figure 2), the first transistor including a gate electrode connected to a scan signal line (Park, scan lines SCL, Figure 2);
a second transistor (Park, second scan transistor SCT2, Figure 2) connected between the first node (Park, node N3, Figure 2) and the second node (Park, node N2, Figure 2), the second transistor including a gate electrode connected to the scan signal line (Park, scan lines SCL, Figure 2);
a third transistor (Park, second light emission control transistor EMT2, Figure 2) connected between the third node (Park, node N4, Figure 2) and a fourth node (Park, node Nr, Figure 2), the third transistor including a gate electrode connected to an emission signal line (Park, light emission control lines EML, Figure 2); and
Park does not expressly teach
a voltage divider connected between the high potential voltage line and the low potential voltage line, the voltage divider being configured to divide a voltage corresponding to a difference between a high potential voltage supplied to the high potential voltage line and a low potential voltage supplied to the low potential voltage line to generate a reference voltage and output the reference voltage to the fourth node.
Additional prior art of Yang (U.S. Pub. No. 2020/031224) teaches a pixel circuit with a voltage divider (Yang, voltage divider sub-circuit 12, Figure 5) connected between a high potential voltage line (Yang, power source positive terminal Vdd, Figure 5) and a low potential voltage line (Yang, power source negative terminal Vss, Figure 5). As shown in figure 5 of Yang, the voltage divider sub-circuit 12 is connected between the VDD and VSS through various intervening components. However, Yang does not teach the generation of a reference voltage to output to the fourth node as claimed.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claims 2-8, these claims are allowable as they depend upon allowable independent claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 11-17, 20, 26, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 11, Lee, as modified by Yang and Park, does not expressly teach the display device wherein the voltage divider is configured to divide a voltage corresponding to a difference of a high potential voltage supplied to the high potential voltage line and a low potential voltage supplied to the low potential voltage line to generate a reference voltage and output the reference voltage to the fourth node.
Yang (U.S. Pub. No. 2020/031224) teaches a pixel circuit with a voltage divider (Yang, voltage divider sub-circuit 12, Figure 5) connected between a high potential voltage line (Yang, power source positive terminal Vdd, Figure 5) and a low potential voltage line (Yang, power source negative terminal Vss, Figure 5). As shown in figure 5 of Yang, the voltage divider sub-circuit 12 is connected between the VDD and VSS through various intervening components. However, Yang does not teach the generation of a reference voltage to output to the fourth node as claimed.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claim 12, this claim is objected to for the same reasons as claim 11 as claim 12 depends upon objected dependent claim 11.
As to claim 13, Lee, as modified by Yang and Park, does not expressly teach the display device wherein the voltage divider includes a plurality of auxiliary transistors connected in series between the high potential voltage line and the low potential voltage line.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claims 14-17, these claims are objected to for the same reasons as claim 13 as these claims depend upon objected dependent claim 13.
As to claim 20, Lee, as modified by Yang and Park, does not expressly teach the display device wherein a number of the plurality of second connection lines is less than a number of the plurality of first connection lines.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 26, Lee, as modified by Yang, does not expressly teach the display device wherein a number of the plurality of first connection lines is less than a number of the plurality of second connection lines.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to claim 28, Lee, as modified by Yang, does not expressly teach the display device wherein the voltage divider in each of the sub pixels includes two transistors connected in series.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
Conclusion
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623