DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
No Information Disclosure Statement has been submitted.
The Examiner would like to remind Applicants about Duty of Disclosure, Candor, and Good Faith (See 37 C.F.R. F56 and MPEP2001).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 7, 9, 12-13, 15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeong et al., US 2019/0393353 (corresponding to US 10,892,366).
In re Claim 1, Jeong discloses an array substrate, comprising a substrate 10 and at least one transistor T (Fig. A) located on a side of the substrate 10, wherein each transistor T of the at least one transistor comprises an active layer 45, a first ohmic contact layer 1ΩCL, a first gate 20 and a first electrode 50S, and the active layer 45 comprises metal oxide ([0022-0023]); along a thickness direction of the substrate 10, the first ohmic contact layer 1ΩCL (between source electrode 50S and the metal oxide channel layer 45, [0026]; marked 1ΩCL as in Fig. A) is located on a side of the active layer 45 facing away from the substrate 10, and the first electrode 50S and the first gate 20 are located on a side of the first ohmic contact layer 1ΩCL facing away from the substrate 10; the active layer 45 comprises a channel region (a portion of 45 marked as CH in Fig. A; [0028]) and a first ohmic contact region (a portion of 45 underneath 1ΩCL, marked as 1OCR in Fig. A), and a vertical projection of the first gate 20 on the active layer 45 overlaps the channel region CH; and the first ohmic contact layer 1ΩCL is in contact connection with the first ohmic contact region 1OCR of the active layer 45, and the first electrode 50S is electrically connected to the first ohmic contact layer 1ΩCL (Figs. 3 and A, [0022 – 0044]).
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Fig. A. Jeong’s Fig. 3B annotated to show the details cited
In re Claim 2, Jeong discloses the array substrate according to claim 1, wherein along a first (horizontal) direction, a distance from a boundary of a side of the first ohmic contact layer 1ΩCL close to the channel region CH is dl, and a distance from a boundary of a side of the first electrode close to the channel region is d2, wherein dl = d2 (that is within the claimed range d1≤ d2, therefore anticipates the range (see MPEP2131.03.I); and the first(horizontal) direction is a direction of the first ohmic contact region 1OCR pointing to the channel region CH (Fig. A).
In re Claim 3, Jeong discloses the array substrate according to claim 1, wherein the first gate 20 and the first electrode 50S are located in a same layer (Fig. A).
In re Claim 4, Jeong discloses the array substrate according to claim 1, wherein the array substrate further comprises a first gate insulating layer 30, and along the thickness direction of the substrate 10, the first gate insulating layer 30 is located between the first electrode 50S and the active layer 45, and the first ohmic contact layer 1ΩCL is located between the first gate insulating layer 30 and the active layer 45; and a vertical projection of the first ohmic contact layer 1ΩCL on the active layer 45 coincides with the first ohmic contact region 1OCR. (Fig. A).
In re Claim 5, Jeong discloses the array substrate according to claim 4, wherein the first ohmic contact region 1OCR abuts onto the channel region CH (Fig. A).
In re Claim 6, Jeong discloses the array substrate according to claim 4, wherein the active layer 45 further comprises a first doping region 1DR abutting onto the first ohmic contact region 1OCR and the channel region CH separately (Fig. A).
In re Claim 7, Jeong discloses the array substrate according to claim 1, wherein the array substrate further comprises a first gate insulating layer 30, and along the thickness direction of the substrate 10, the first gate insulating layer 30 is located between the first electrode 50S and the active layer 45, and the first ohmic contact layer 1ΩCL is located between the first gate insulating layer 30 and the first electrode 50S; the first gate insulating layer 30 is provided with a first via (wherein 1ΩCL is located) through which the first ohmic contact layer 1ΩCL is in contact connection with the active layer 45; along a first (horizontal) direction, a first boundary of the first electrode 50S is located on a side of a second boundary of the first via (wherein 1ΩCL is located) facing away from the channel region CH, wherein the first boundary is a boundary of a side of the first electrode 50S close to the channel region CH, and the second boundary is a boundary of a side of the first via (wherein 1ΩCL is located) close to the channel region CH; and the first direction is a direction of the first ohmic contact region 1OCR pointing to the channel region CH (Fig. A).
In re Claim 9, Jeong discloses all limitations of claim 9 including that along the thickness direction of the substrate 10, a length of an overlapping region between the first electrode 50S and the first via (wherein 1ΩCL is located) in the first (horizontal) direction is d6; and along the thickness direction of the substrate 10, within a region in which the first via (wherein 1ΩCL is located) is located, a length of a region other than the overlapping region between the first via (wherein 1ΩCL is located) and the first electrode 50S in the first direction is d7 (Fig. A), wherein d7 = d6 that within the claimed range of d7 ≥ d6, therefore anticipated that range (see MPEP2131.03.I).
In re Claim 12, Jeong discloses the array substrate according to claim 1, wherein the each transistor further comprises a second electrode and a second ohmic contact layer; the second ohmic contact layer 2ΩCL is located on the side of the active layer 45 facing away from the substrate 10, and the second electrode 50D is located on a side of the second ohmic contact layer 2ΩCL facing away from the substrate 10; the active layer 45 further comprises a second ohmic contact region 2OCR located on a side of the channel region CH away from the first ohmic contact region 1OCR; and the second ohmic contact layer 2ΩCL is in contact connection with the second ohmic contact region 2OCR of the active layer 45, and the second electrode 50D is electrically connected to the second ohmic contact layer 2OCR (Fig. A).
In re Claim 13, Jeong discloses the array substrate according to claim 1, wherein the each transistor further comprises a second electrode 50D, and along the thickness direction of the substrate 10, the second electrode 50D is located on a side of the first gate 20 facing away from the substrate 10; the active layer 45 further comprises a second doping region 2DR located on a side of the channel region CH facing away from the first ohmic contact region 1OCR; and the second electrode 50D and the active layer 45 are in contact connection in the second doping region 2DR. (Fig. A).
In re Claim 15, Jeong discloses a preparation method for an array substrate, comprising: preparing an active layer 45, a first ohmic contact layer 1ΩCL, a first gate 20 and a first electrode 50S on a side of the substrate 10 to form at least one transistor T (Fig. A), wherein the active layer 45 is metal oxide ([0022-0023]); along a thickness direction of the substrate 10, the first ohmic contact layer 1ΩCL is located on a side of the active layer 45 facing away from the substrate 10, and the first electrode 50S and the first gate 20 are located on a side of the first ohmic contact layer 1ΩCL facing away from the substrate 10; the active layer 45 comprises a channel region CH and a first ohmic contact region 1OCR, and a vertical projection of the first gate 20 on the active layer 45 coincides with the channel region CH; and the first ohmic contact layer 1ΩCL is in contact connection with the first ohmic contact region 1OCR of the active layer 45, and the first electrode 50S is electrically connected to the first ohmic contact layer 1ΩCL. (Figs. 3 and A, [0022 – 0044]).
In re Claim 17, Jeong discloses the preparation method according to claim 15, wherein preparing the active layer 45, the first ohmic contact layer 1ΩCL and the first electrode 50S on the side of the substrate 10 comprises: preparing the active layer 45 on the side of the substrate 10; preparing a first gate insulating layer 30 on the side of the active layer 45 facing away from the substrate 10; preparing a first via (wherein 1ΩCL is located) on the first gate insulating layer 30; and preparing the first ohmic contact layer 1ΩCL and the first electrode 50S on a side of the first gate insulating layer 30 facing away from the substrate 10, wherein the first ohmic contact layer 1ΩCL is in contact connection with the active layer 45 through the first via (wherein 1ΩCL is located), and along a direction of the first ohmic contact region 1OCR pointing to the channel region CH, a first boundary of the first electrode 50S is located on a side of a second boundary of the first via (wherein 1ΩCL is located) facing away from the channel region CH, the first boundary is a boundary of a side of the first electrode 50S close to the channel region CH, and the second boundary is a boundary of a side of the first via (wherein 1ΩCL is located) close to the channel region CH. (Fig. A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8 and 10 -11 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong as applied to claim 7 above.
In re Claim 8, Jeong discloses all limitations of Claim 8, including that a length of the first electrode 50S in the first direction is d5; and along the thickness direction of the substrate 10, a length of an overlapping region between the first electrode 50S and the first via (wherein 1ΩCL is located) in the first direction is d6 (Fig. A), except for that d6 ≥ (1/2)*d5.
The difference between the Applicant’s Claim 8 and Jeong’s reference is in the specified ratio of the lengths. It is known in the art that the length is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the ratio of d6 ≥ (1/2)*d5, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 10, Jeong discloses all limitations of Claim 10 including that along the thickness direction of the substrate 10, the first electrode 50S and the first via (wherein 1ΩCL is located) overlap, and a length of an overlapping region between the first electrode 50S and the first via (wherein 1ΩCL is located) in the first (horizontal) direction is d6; and a length in the first direction of a region in which the first via (wherein 1ΩCL is located) is located is d8, except for that 10% d6/d8 <90%. The difference between the Applicant’s claim 10 and Jeong’s reference is in the specified ratio of lengths.
It is known in the art that the length is a result effective variable – because volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the ratio of 10% d6/d8 <90%, since such a modification would have involved a mere change in the size of a component. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984) (MPEP2144.04.IV.A).
In re Claim 11, Jeong discloses all limitations of Claim 11, including that the first electrode 50S comprises a first conductive base layer 1CBL (Fig. A) and a first conductive electrode layer 1CEL that are stacked, and along the thickness direction of the substrate 10, the first conductive base layer 1CBL is located on a side of the first conductive electrode layer 1CBL close to the first gate insulating layer 30, and the first conductive base layer 1CBL is in contact connection with the first conductive electrode layer 1CBL, except for that the first ohmic contact layer 1ΩCL and the first conductive base layer 1CBL have a same film structure.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to make the first ohmic contact layer 1ΩCL and the first conductive base layer 1CBL withe a same film structure since it was known in the art that it simplifies manufacturing process. (MPEP2144.I.)
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin at al., US 2012/0193049 (corresponding to US 12,148,390), in view of Jeong.
In re Claim 19, Lin discloses a display panel, comprising an array substrate, wherein the array substrate comprises a substrate 800 (Fig. 9) and at least one transistor (Toxide 1) located on a side of the substrate 800, wherein each transistor (Toxide 1) of the at least one transistor (Toxide 1) comprises an active layer 816 (Figs. 1-9, [0030-0095]).
Lin does not indicate that each transistor (Toxide 1) a first ohmic contact layer, a first gate and a first electrode, and the active layer comprises metal oxide; along a thickness direction of the substrate, the first ohmic contact layer is located on a side of the active layer facing away from the substrate, and the first electrode and the first gate are located on a side of the first ohmic contact layer facing away from the substrate; the active layer comprises a channel region and a first ohmic contact region, and a vertical projection of the first gate on the active layer overlaps the channel region; and the first ohmic contact layer is in contact connection with the first ohmic contact region of the active layer, and the first electrode is electrically connected to the first ohmic contact layer.
Jeong teaches a transistor T (Fig. A) comprising ) a first ohmic contact layer 1ΩCL, a first gate 20 and a first electrode 50S, and the active layer 45 comprises metal oxide; along a thickness direction of the substrate 10, the first ohmic contact layer 1ΩCL is located on a side of the active layer 45 facing away from the substrate 10, and the first electrode 50S and the first gate 20 are located on a side of the first ohmic contact layer 1ΩCL facing away from the substrate 10; the active layer 45 comprises a channel region CH and a first ohmic contact region 1OCR, and a vertical projection of the first gate 20 on the active layer 45 overlaps the channel region CH; and the first ohmic contact layer 1ΩCL is in contact connection with the first ohmic contact region 1OCR of the active layer 45, and the first electrode 50S is electrically connected to the first ohmic contact layer 1OCR. (Figs. 3 and A, [0022 – 0044]).
To reject a claim based on this rationale set forth in MPEP 2143 (B), Office personnel must resolve the Graham factual inquiries. Then, Office personnel must articulate the following:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In the instant case, examiner articulates the following:
(1) Lin’s reference contains a display panel which differed from the claimed device by the substitution of some components (at least on transistor) with a transistor of the specified structure;
(2) Jeong’s device with transistor of the specified structure and its functions were known in the art;
(3) Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, one of ordinary skill in the semiconductor art could have substituted one known element (Lin’s transistor) for another (Jeong’s transistor), and the results of the substitution would have been predictable, because Jeong’s device successfully functions;
(4) In view of the facts of the case under consideration, there appear to be no additional findings (re, e.g. long-felt need, unexpected results, commercial success, etc.) needed, based on the Graham factual inquiries.
Lin taken with Jeong teaches a display device comprising the display panel according to claim 19.
Allowable Subject Matter
Claims 14, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 14: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 14 as: “the first gate is electrically connected to the first metal layer”, in combination with limitations of Claim 1 on which it depends.
In re Claim 16: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 16 as: “etching the active material layer and the first ohmic contact material layer using a halftone mask in a same process to form the active layer and the first ohmic contact layer”, in combination with limitations of Claim 15 on which it depends.
In re Claim 18: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 18 as: “performing ion implantation on the active layer using the first gate as a blocking layer to form a first doping region”, in combination with limitations of Claim 15 on which it depends.
Conclusion
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893