Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Election/Restrictions
Claim 20 is withdrawn from further consideration pursuant to the 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse of Group I and Species A in the reply filed on March 2, 2025. Applicant has stated that Claims 1-19 read on the elected species, which is acknowledged by the Examiner.
The arguments present the opinion that there is no excess examination burden without providing any reasoning and/or evidence to which the examiner disagrees for reasons detailed in the requirement for the restriction.
Therefore, the restriction is maintained and made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-10, 11, 13-16, 18, and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim (US 2024/0072092 A1), hereinafter as L1.
Regarding Claim 1, L1 discloses an image sensor (see FIG. 7 element 500A and [0107] ln. 1 “the image sensor 500A”) comprising:
a pixel array (see FIG. 7, element 100, and [0065] ln. 1 “the first semiconductor chip 100 may include a pixel array region”) in which a plurality of pixels are arranged (see [0069] ln. 1 “the first semiconductor chip 100 may include a first semiconductor substrate 110 having a pixel array (11 in FIG. 1) in which a plurality of pixels PX are arranged”), wherein each of the plurality of pixels includes a first photodiode (see FIG. 7, element LPD, [0024] ln. 8 “large photodiode LPD”), a second photodiode (see FIG. 7, element SPD, [0024] ln. 7 “small photodiode SPD”), a first transmission gate (see FIG. 7 element TG2, [0044] ln. 7 “second transfer transistor” where TG2 represents the first transmission gate as described), a second transmission gate (see FIG. 7 element TG1, [0044] ln. 6 “first transfer transistor” where TG1 represents the second transmission gate as described), and a plurality of active regions (see FIG. 7, and [0073] ln. 3 “device isolation pattern ISO may be formed in the first semiconductor substrate 110 and may define an active region in which the first semiconductor devices 150 are to be formed” defining two active regions between the ISO elements in the first semiconductor substrate, with one being between the ISO elements of the SPD area and one between the ISO elements of the LPD area. Also see [0096] ln. 1 “Second semiconductor devices 250 formed in an active region defined by the device isolation pattern ISO may be formed on a lower surface of the second semiconductor substrate 210” for a third active region defined at the second semiconductor devices 250”); and
a logic circuit (see FIG. 7 elements 300 A and 300, [0065] “main region 300 A of the third semiconductor chip 300 may include a logic circuit region including a row driver, a readout circuit, a ramp signal generator, and a timing controller (see “12” to “15” in FIG. 1)”) configured to control the plurality of pixels (see FIG. 1 where the elements 12 to 15 described to contain a controller in the previous circuitry are connected to the pixel array, see [0018] ln. 2 “pixel array 11”),
wherein a light receiving area of the first photodiode is larger than a light receiving area of the second photodiode (see FIG. 7 where the photodiode LPD is larger than the photodiode SPD and see [0024] ln. 6 “small photodiode SPD having a small light-receiving area…a large photodiode LPD having a light-receiving area larger than that of the small photodiode SPD”), the plurality of active regions include a first active region (a first active region is located between the ISO regions of the SPD element, as defined prior), a second active region (a second active region is located between the ISO regions of the LPD element, as defined prior) and a third active region (a third active region is located at the second semiconductor elements 250, as described prior), wherein the first active region is disposed adjacent to the first transmission gate (see FIG. 7 where the described first transmission gate TG2 is adjacent to the described first active region), wherein the second active region is disposed adjacent to the second transmission gate (see FIG. 7 where the described second transmission gate TG1 is adjacent to the described second active region), wherein the third active region is electrically connected to the second active region by a wiring pattern (see FIG. 7, element 120, 220, P3a’, and P3b’, [0078] ln. 9 “first and second wire structures 120 and 220” [0112] ln. 10 “third path P3a′…third path P3b’” where the second active area is connected to the third active region at element 250 through the wiring structures 120 and 220 along the paths P3a’ and P3b’ in FIG. 7), and
the first active region and the second active region are disposed on a main substrate (see FIG. 7, element 110, [0069] ln. 2 “first semiconductor substrate 110” where the described first and second active regions are disposed therein), which includes the first photodiode and the second photodiode (see FIG. 7 where the first and second photodiodes LPD and SPD are disposed within the active regions of the first semiconductor substrate 110), and the third active region is disposed on a sub-substrate (see FIG. 7, element 210, [0077] ln. 3 “second semiconductor substrate 210” where the defined third active region is disposed therein) that is attached to the main substrate (see FIG. 7 where the second semiconductor substate 210 is attached to the first semiconductor substate 110).
Regarding Claim 4, L1 discloses the image sensor of claim 1, wherein the first active region provides a first floating diffusion region (see FIG. 7 [0048] ln. 3 “first floating diffusion node FD1” where FD1 is disposed in the first active region), and the second active region and the third active region provide a second floating diffusion region (see FIG. 7 [0048] ln. 9 “third floating diffusion node FD 3” where FD3 is disposed in and defined as the third active region and is connected to the second active region at the element 155b [0074] ln. 4 “source/drain regions 155a and 155b”), and
the third active region is disposed on the first photodiode (see FIG. 7 where the third active region at the elements 250 is disposed in the second semiconductor substrate 210, which is disposed on the first semiconductor substrate 110) in a direction substantially perpendicular to a first surface (see FIG. 7 and the surface at the top of the first semiconductor substrate 110) of the main substrate (see FIG. 7 where the third active region defined FD3 is perpendicular to the first surface defined above the substrate 110).
Regarding Claim 5, L1 discloses the image sensor of claim 1, wherein each of the plurality of pixels includes a plurality of switch transistors (see FIG. 7, elements SW1 and SW2, [0044] ln. 4 “The pixel PX may include a plurality of transistors…first transistor SW1, a second switch transistor SW2”) and at least one source-follower transistor (see FIG. 7, elements 150 and SF, [0075] ln. 1 “The first semiconductor devices 150 may include a transistor such as…source follower transistor SF”), and the at least one source-follower transistor is disposed on the main substrate (see FIG. 7 where the source follower transistor SF is included in the first semiconductor devices 150 is in the first semiconductor substrate 110).
Regarding Claim 6, L1 discloses the image sensor of claim 5, wherein the plurality of switch transistors are disposed on the sub-substrate (see FIG. 7 where the switch transistors SW1 and SW2 are disposed in the second semiconductor substrate 210).
Regarding Claim 7, L1 discloses the image sensor of claim 1, wherein each of the plurality of pixels further includes a first micro lens, a second micro lens (see FIG. 7 element ML1 [0103] ln. 8 “micro lenses ML1 and ML2”), and an internal separation film (see FIG. 7, element 180, 181, and 185, [0071] ln. 2 “a pixel isolation structure 180”, and [0072] ln. 12 “the pixel isolation structure 180 may include an insulating layer 181… and a conductive layer 185 filling the trench on the insulating layer 181” where element 180 is shown to be made up of element 181 and 185 in FIG. 7 in the key at the bottom of the page), wherein the first micro lens is attached to a second surface of the main substrate (see FIG. 7 where the second surface is defined to be below the photodiodes, on the bottom of the substrate 110) and is disposed on the first photodiode (see FIG. 7 where ML2 is disposed on the photodiode LPD), wherein the second micro lens is attached to the second surface of the main substrate (see FIG. 7 where the micro lens ML1 is on the bottom surface of the substrate 110) and is disposed on the second photodiode (see FIG. 7 where ML1 is disposed on the photodiode SPD), wherein the internal separation film is disposed between the first photodiode and the second photodiode (see FIG. 7 and [0071] ln. 4 “the pixel isolation structure 180, the first and second photodiodes SPD and LPD may be physically and electrically isolated from each other”).
Regarding Claim 8, L1 discloses the image sensor of claim 7, wherein the internal separation film extends from the first surface to the second surface of the main substrate (see FIG. 7 where the pixel isolation structure 180 extends across the whole surface of the first semiconductor substrate 110).
Regarding Claim 9, L1 discloses the image sensor of claim 7, wherein at least a portion of the sub-substrate (element 210) overlaps the internal separation film (see FIG. 7 where the second semiconductor substrate 210 overlaps the pixel isolation structure 180 formed by elements 181 and 185 between LPD and SPD).
Regarding Claim 10, L1 discloses the image sensor of claim 1, wherein each of the plurality of pixels further includes a capacitor element (see FIG. 7 element 280 [0081] ln. 3 “having a capacitor 280” that is connected to the second active region (see Fig. 7, elements 122 and 123, [0080] ln. 9 “wiring vias 123 connected to the plurality of wiring lines 122” where the second active region defined between the ISO elements of the LPD element is connected to the capacitor element 280 through the wiring vias 123 and lines 122.
Regarding Claim 11, L1 discloses the image sensor of claim 1, wherein the pixel array further includes a pixel separation film (see FIG. 7, element 180, 181, and 185, [0071] ln. 2 “a pixel isolation structure 180”, and [0072] ln. 12 “the pixel isolation structure 180 may include an insulating layer 181…and a conductive layer 185 filling the trench on the insulating layer 181” where element 180 is shown to be made up of element 181 and 185 in FIG. 7 in the key at the bottom of the page) and a charge blocking region (see FIG. 7, element 181, where the insulating layer 181 between the photodiodes would block charges being transferred between the two photodiodes LPD and SPD) wherein the pixel separation film is disposed between the plurality of pixels (see FIG. 7 and [0072] ln. 1 “the pixel isolation structure 180 may be disposed between each of the plurality of pixels PX” which includes the insulating 181), and
the charge blocking region is disposed around the pixel separation film (see FIG. 7 where the insulating layer 181 is the on the outside of the pixel separation structure 180 and therefore surrounds it), and the charge blocking region is doped with a conductive type impurity (see [0072] ln. 17 “the conductive layer 185 may include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, or a metal-containing layer” where the layer is conductive and is doped with an impurity such as polysilicon and is included in the surrounded insulating area 181) that is different from that of the photodiode (see [0020] “the photoelectric conversion element may be a light sensing element such as an inorganic photodiode or an organic photodiode” where when the photodiode is organic, it would be doped differently than the inorganic conductive layer 185. The photodiode would have to be doped differently from the conductive layer 185 and insulating layer 181 in order for the charge to be absorbed and insulated by this region.).
Regarding Claim 13, L1 discloses an image sensor (see FIG. 7 element 500A and [0107] ln. 1 “the image sensor 500A”) comprising:
a main substrate including a plurality of pixel regions (see [0069] ln. 1 “the first semiconductor chip 100 may include a first semiconductor substrate 110 having a pixel array (11 in FIG. 1) in which a plurality of pixels PX are arranged”) and a plurality of photodiodes (see FIG. 7, elements SPD and LPD, and [0024] ln. 6 “the pixel PX may include a small photodiode SPD…and a large photodiode LPD”), wherein the plurality of pixel regions is separated from each other by a pixel separation film (see FIG. 7, element 180, 181, and 185, [0071] ln. 2 “a pixel isolation structure 180” and [0072] ln. 1 “the pixel isolation structure 180 may be disposed between each of the plurality of pixels PX” and [0072] ln. 12 “the pixel isolation structure 180 may include an insulating layer 181…and a conductive layer 185 filling the trench on the insulating layer 181” where element 180 is shown to be made up of element 181 and 185 in FIG. 7 in the key at the bottom of the page), and the plurality of photodiodes is disposed in the plurality of pixel regions (see [0044] ln. 1 “pixel PX may include a plurality of photodiodes”);
a sub-substrate (see FIG. 7, element 210, [0077] ln. 3 “second semiconductor substrate 210”) disposed on a first surface of the main substrate (see FIG. 7 where the second semiconductor substate 210 is attached to the first semiconductor substate 110);
an optical region (see FIG. 7, where the region is at the element 160 and below, see [0103] ln. 3 “insulating material layer 160”) disposed on a second surface of the main substrate (a second surface is defined at the bottom of the photodiodes between element 160 and the photodiodes, where a first surface is at the top of the photodiodes) and including a plurality of color filters (see FIG. 7, element CF, [0103] ln. 4 “a color filter CF disposed on the insulating material layer 160”) and a plurality of micro lenses (see FIG. 7, elements ML1 and ML2 [0103] ln. 5 “micro lenses ML1 and ML2”),
wherein some transistor among a plurality of transistors included in each of the plurality of pixel regions are disposed on the main substrate (see FIG. 7, element 150, [0073] ln. 1 “the first semiconductor devices 150…may be disposed on the upper surface of the first semiconductor substrate 110” and [0074] ln. 1“The first semiconductor devices 150…may include transistors including a gate electrode 152, a gate insulating film 151, and source/drain regions 155 a and 155 b” and elements TG1 and TG2, [0044] ln. 5 “first transfer transistor TG1…second transfer transistor TG2”), and the other transistors among the plurality of transistors are disposed on the sub-substrate (see FIG. 7, element 250, SW1, and SW2, [0096] ln. 1 “second semiconductor devices 250…may be formed on a lower surface of the second semiconductor substrate 210… the second semiconductor devices 250 may include at least one element among elements included in the pixel circuit (PX_C in FIG. 2)” which includes transistors and [0044] ln. 10 “first switch transistor SW1, a second switch transistor SW2” which are formed in the second semiconductor substate 210) and
the some transistors and the other transistors do not overlap each other in a direction substantially perpendicular to the first surface of the main substrate (see FIG. 7 where the transistors of the first semiconductor substrate 110 and the transistors of the second semiconductor substrate 210 do not overlap each other in a perpendicular direction).
Regarding Claim 14, L1 discloses the image sensor of claim 13, wherein the plurality of transistors include a plurality of transmission transistors (see FIG. 7, elements TG1 and TG2, [0044] ln. 5 “first transfer transistor TG1…second transfer transistor TG2”), a plurality of switch transistors (see FIG. 7, elements SW1 and SW2, [0044] ln. 10 “first switch transistor SW1, a second switch transistor SW2”), and at least one source-follower transistor (see FIG. element 150, [0075] ln. 1 “the first semiconductor devices 150 may include transistors such as…the source follower transistor SF”), and
the plurality of transmission transistors and the at least one source-follower transistor are disposed on the main substrate (see FIG. 7 where the two transfer transistors TG1 and TG2, and the source follower transistor SF included in element 150 are disposed in the first semiconductor substrate 110), and the plurality of switch transistors are disposed on the sub-substrate (see FIG. 7 where the two switch transistors SW1 and SW2 are disposed in the second semiconductor substrate 210).
Regarding Claim 15, L1 discloses the image sensor of claim 13, wherein the plurality of transistors include a plurality of transmission transistors (elements TG1 and TG2), a plurality of switch transistors (elements SW1 and SW2), and a select transistor (see FIG. 7 and FIG. 2, element SX and 250, [0044] ln. 8 “source follower transistor SF”, and [0096] ln. 4 “the second semiconductor devices 250 may include at least one element among the elements included in the pixel circuit (PX_C in FIG. 2)” where a source follower transistor SF is shown to be included) and
the plurality of transmission transistors are disposed on the main substrate (see FIG. 7 where the transmission transistors TG1 and TG2 are disposed in the first semiconductor substrate 110), and the select transistor and the plurality of switch transistors are disposed on the sub-substrate (see FIG. 7, [0115] ln. 7 “select transistor SX may be formed on the second semiconductor substrate 210” and [0110] ln. 3 “the second switching transistor SW2 may be formed on the lower surface of the second semiconductor substrate 210” where the second semiconductor device 250 that includes a select transistor SX as described and the switch transistors SW1 and SW2 are disposed in the second semiconductor substrate 210).
Regarding Claim 16, L1 discloses the image sensor of claim 13, wherein in each of the plurality of pixel regions, the some transistors and the other transistors are disposed at different positions from each other (the transistors disposed in the first semiconductor substrate 110 and the transistors in the second semiconductor substrate 210 are in different positions from each other) on a plane that is parallel to an upper surface of the main substrate (the transistors of the two substrates are on parallel surfaces to each other, and parallel to the surface at the bottom of the photodiodes).
Regarding Claim 18, L1 discloses the image sensor of claim 13, wherein the plurality of photodiodes include a plurality of first photodiodes and a plurality of second photodiodes (see [0022] ln. 1 “the plurality of pixels PX may have a multilayer structure. The multilayer pixel PX may include a plurality of stacked photoelectric conversion elements”, and [0060] ln. 1 “the photoelectric conversion element of each pixel PX may include a large photodiode LPD and a small photodiode SPD”, and
one of the pluralities of first photodiodes and one of the pluralities of second photodiodes are disposed in each of the plurality of pixel regions (see [0044] ln. 1 “pixel PX may include a plurality of photodiodes, for example, a large photodiode LPD having a large light-receiving area and a small photodiode SPD having a small light-receiving area” expressing how each of the plurality of pixels PX includes two photodiodes.
Regarding Claim 19, L1 discloses the image sensor of claim 18, wherein a light receiving area of each of the plurality of first photodiodes is larger than a light receiving area of each of the plurality of second photodiodes (see [0024] ln. 6 “the pixel PX may include a small photodiode SPD having a small light-receiving area…and a large photodiode LPD having a light-receiving area larger than that of the small photodiode SPD” where LPD and SPD are the plurality of first and second photodiodes).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under U.S.C. 103 as being unpatentable over Lim (US 2024/0072092 A1), hereinafter as L1, in view of Park (US 2023/0076351 A1) hereinafter as P1.
Regarding Claim 2, L1 discloses the image sensor of claim 1,
L1 does not disclose wherein the sub-substrate is a silicon on insulator (SOI) substrate. P1 discloses wherein the sub-substrate (see FIG. 5, element 210, [0059] ln. 5 “a second substrate 210”) is a silicon on insulator (SOI) substrate (see [0074] ln. 1 “second substrate 210 may be a bulk silicon or silicon-on-insulator (SOI) substrate”).
The second substrate being a SOI substrate as disclosed by P1 is incorporated into the disclosure of L1. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of P1 into L1 as there is motivation for using an SOI substate to obtain predictable results-there is motivation to use SOI substrate as said SOI improves semiconductor performance by reducing parasitic capacitance within the device and therefore improves proficiency.
Regarding Claim 3, L1 and P1 disclose the image sensor of claim 2, and L1 further discloses wherein a thickness of the sub-substrate is less than a thickness of the main substrate (see FIG. 7 where the thickness of the first semiconducting substrate 110 is thicker than the second semiconductor substrate 210).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for indicating allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
Claim 12, “in a direction substantially perpendicular to a first surface of the main substrate, the sub-substrate overlaps the first photodiode and does not overlap the second photodiode” – as instantly claimed and in combination with the additionally claimed limitations.
Claim 17, “the plurality of transistors include a select transistor, a reset transistor, a first switch transistor, and a second switch transistor, wherein the select transistor is connected between at least one source-follower transistor and a column line, wherein the reset transistor is connected to a power node, wherein the first switch transistor is connected between a gate of the source-follower transistor and the reset transistor, and wherein the second switch transistor is connected to a node that is between the reset transistor and the first switch transistor” - as instantly claimed in combination with the additionally claimed limitations.
All claims depending on the current claims incorporate the same allowable subject matter. None are present at the time of filing.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights