Prosecution Insights
Last updated: April 19, 2026
Application No. 18/244,858

THREE-DIMENSIONAL SCANNING SYSTEM AND THREE-DIMENSIONAL SCANNING METHOD

Non-Final OA §103
Filed
Sep 11, 2023
Examiner
SARMA, ABHISHEK
Art Unit
2621
Tech Center
2600 — Communications
Assignee
Scantech (Hangzhou) Co. Ltd.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
85%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
478 granted / 572 resolved
+21.6% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
18 currently pending
Career history
590
Total Applications
across all art units

Statute-Specific Performance

§101
4.4%
-35.6% vs TC avg
§103
73.0%
+33.0% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
4.8%
-35.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 572 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application is being examined under the pre-AIA first to invent provisions. In the response to this Office Action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. Election/Restrictions Applicant's election without traverse of Species I: Figure 2 in the reply filed on 10/22/2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Foreign Publication CN110715618 A to Du et al. (hereinafter "Du", included in IDS provided by Applicant) in view of U.S. Patent Application Publication 2016/0153768 A1 to Stettner (hereinafter "Stettner"). Regarding Claims 1 and 14, Du teaches a three-dimensional scanning system and a three-dimensional scanning method comprising: a scanning apparatus configured to acquire first raw image data of a scanning target (Claims 1, 6; Figs. 1-9; Para. 34-100 of Du; a dynamic three-dimensional scanning method, including the following steps: S101. Collect a surface image of a measured object to obtain an original image. S102. Perform downsampling processing on the original image to obtain a two-dimensional feature data point set after downsampling. S103. Convert the down-sampled two-dimensional feature data point set into a three-dimensional feature data point set. S104. Register the three-dimensional feature data point set to the same coordinate system… dynamic three-dimensional scanning device further includes an image processor 110 and a real-time data preview calculator 120; the image processor 110 is disposed on the mobile processing unit 100 and is electrically connected to the pattern projector 200 and the battery, respectively. Module 300 and at least two image acquisition sensors 400; the real-time data preview calculator 120 is set in the mobile processing unit 100, is electrically connected to the image processor 110, or is set in a host computer, and communicates with the image processor 110 through a wireless / wired communication module 140 communication connection; The image processor 110 is configured to perform image downsampling processing on the original image, so that the resolution of the image after the downsampling is the set resolution; Extract the two-dimensional feature points of the down-sampled image to obtain a first two-dimensional feature data point set, and the first two-dimensional feature data point set is used as the down-sampled two-dimensional feature data point set; or / and Perform image downsampling processing on the original image, so that the resolution of the image after the downsampling is the set resolution; Extracting the two-dimensional feature points of the down-sampled image to obtain a first two-dimensional feature data point set; The real-time data preview calculator 120 is configured to perform time-series downsampling processing on the first two-dimensional feature data point set according to the set sampling density, to obtain a second two-dimensional feature data point set, and the second two-dimensional feature data point set is used as the next The two-dimensional feature data point set after sampling; Converting the down-sampled two-dimensional feature data point set into a three-dimensional feature data point set; The 3D feature data point set is registered to the same coordinate system); a computing module provided in the scanning apparatus and configured to perform computational preprocessing on the first raw image data to obtain valid first feature data (Figs. 2-9; Para. 43-100 of Du; dynamic three-dimensional scanning device further includes an image processor 110 and a real-time data preview calculator 120; the image processor 110 is disposed on the mobile processing unit 100 and is electrically connected to the pattern projector 200… image processor 110 is a high-performance hardware processing unit, which is set in a dynamic three-dimensional scanning device and can pre-process the acquired images… image processor 110 may use one or a combination of a CPU, a GPU, a DSP, an FPGA, and an ARM, and the embodiment of the present application is not limited. Further, the image processor 110 is further configured to: Restore the resolution of the down-sampled image to the resolution of the original image according to the first two-dimensional feature data point set to obtain the original resolution image; Set the gray value of the image area of the original resolution image that is smaller than the set threshold to the preset gray level, mark the image area of the original resolution image where the gray value is not set to the preset gray level, and obtain a processed image; Compress the processed image to obtain a compressed image); and a modeling terminal connected to the scanning apparatus and configured to perform modeling processing based on the first feature data to generate a three-dimensional model of the scanning target (Figs. 9-12; Para. 43-104 of Du; dynamic three-dimensional scanning device disclosed in the embodiment of the present invention further includes a model generation module 150, and the model generation module 150 is electrically connected to the real-time data preview calculator 120 and is configured to 3D feature data point set to generate a 3D model). Du does not explicitly disclose a first field programmable gate array (FPGA) module. However, Stettner teaches a first field programmable gate array (FPGA) module (Figs. 2-5; Para. 31-53 of Stettner; Some of the data analysis is accomplished by the embedded computer 28 whose program is referred to as firmware… the embedded computer 28 is a field programmable gate array). Therefore, at the time when the invention was filed, it would have been obvious to a person of ordinary skill in the art to include a first field programmable gate array (FPGA) module using the teachings of Stettner in order to modify the system taught by Du. The motivation to combine these analogous arts would have been to a provide dimensioning system that rapidly measures the dimensions of the surface of any object having any size and shape (Para. 3-17 of Stettner). Regarding Claims 2 and 15, the combination of Du and Stettner teaches that the first FPGA module comprises a first feature processing unit configured to perform feature recognition on the first raw image data, the feature recognition comprising marker recognition and/or laser point recognition (Figs. 2-5; Para. 31-53 of Stettner; Some of the data analysis is accomplished by the embedded computer 28 whose program is referred to as firmware… the embedded computer 28 is a field programmable gate array… Figs. 2-9; Para. 43-100 of Du; pattern projector 200 may use a laser projection device… pattern projector 200 projects a specific optical pattern on the surface of the object to be measured. The specific optical pattern may be, for example, a cross-line pattern formed by light emitted from three or more laser projection devices; then, the image acquisition sensor 400 collects an image of the surface of the measured object in the projected area. the dynamic three-dimensional scanning apparatus further includes an image processor 110… image processor 110 is a high-performance hardware processing unit, which is set in a dynamic three-dimensional scanning device and can pre-process the acquired images… image processor 110 may use one or a combination of a CPU, a GPU, a DSP, an FPGA, and an ARM, and the embodiment of the present application is not limited… optimization calculator 140, which is disposed in the mobile processing unit 100 and is electrically connected to the image processor 110… data optimization calculator 140 is used… Save compressed image; Restore the compressed image to the original resolution image; Extract the two-dimensional feature points of the original resolution image to obtain the third two-dimensional feature data point set; Converting the third two-dimensional feature data point set into a third three-dimensional feature data point set; Register the third three-dimensional feature data point set to the same coordinate system). Regarding Claims 3 and 16, the combination of Du and Stettner teaches that the first FPGA module further comprises a first image signal processing unit connected to the first feature processing unit and configured to perform image signal processing on the first raw image data and transmit the processed first raw image data to the first feature processing unit (Figs. 2-5; Para. 31-53 of Stettner; Some of the data analysis is accomplished by the embedded computer 28 whose program is referred to as firmware… the embedded computer 28 is a field programmable gate array… Figs. 2-4, 7-9; Para. 43-56, 80-100 of Du; image processor 110 is a high-performance hardware processing unit, which is set in a dynamic three-dimensional scanning device and can pre-process the acquired images… image processor 110 may use one or a combination of a CPU, a GPU, a DSP, an FPGA, and an ARM, and the embodiment of the present application is not limited. Further, the image processor 110 is further configured to: Restore the resolution of the down-sampled image to the resolution of the original image according to the first two-dimensional feature data point set to obtain the original resolution image; Set the gray value of the image area of the original resolution image that is smaller than the set threshold to the preset gray level, mark the image area of the original resolution image where the gray value is not set to the preset gray level, and obtain a processed image; Compress the processed image to obtain a compressed image… optimization calculator 140, which is disposed in the mobile processing unit 100 and is electrically connected to the image processor 110). Regarding Claim 4, the combination of Du and Stettner teaches that the first FPGA module further comprises a first extraction unit connected to the first feature processing unit and configured to perform sub-pixel extraction on a recognition result of feature recognition of the first raw image data (Figs. 2-5; Para. 31-53 of Stettner; Some of the data analysis is accomplished by the embedded computer 28 whose program is referred to as firmware… the embedded computer 28 is a field programmable gate array… Figs. 2-4, 7-9; Para. 43-56, 80-100 of Du; The size of the original image is M × N, and it is down-sampled by S times, that is, the image in the original image S × S window is turned into a pixel. The value of this pixel is the average value of all pixels in the window. After downsampling, an image of (M / S) × (N / S) size is obtained... After the image is down-sampled, the two-dimensional feature points of the down-sampled image are extracted… image processor 110 is a high-performance hardware processing unit, which is set in a dynamic three-dimensional scanning device and can pre-process the acquired images). Allowable Subject Matter Claims 5-7 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. None of the references, either singularly or in combination, teach or fairly suggest the three-dimensional scanning system according to claim 1, wherein the scanning apparatus further comprises at least two first acquisition modules and a transmission module, wherein the at least two first acquisition modules are connected to the first FPGA module and configured to scan the scanning target to acquire the first raw image data of the scanning target and transmit the first raw image data to the first FPGA module, and wherein the transmission module is connected to the first FPGA module and configured to transmit the valid first feature data in the first field programmable gate array module to the modeling terminal. None of the references, either singularly or in combination, teach or fairly suggest the three-dimensional scanning method according to claim 14, further comprising: scanning the scanning target to acquire the first raw image data of the scanning target and transmit the first raw image data to the first FPGA module with at least two first acquisition modules connected to the first FPGA module; and transmitting the valid first feature data in the first FPGA module to the modeling terminal with a transmission module connected to the first FPGA module. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABHISHEK SARMA whose telephone number is (571)272-9887. The examiner can normally be reached on Mon - Fri 8:00-5:00. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached on 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABHISHEK SARMA/ Primary Examiner, Art Unit 2621
Read full office action

Prosecution Timeline

Sep 11, 2023
Application Filed
Dec 27, 2025
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
85%
With Interview (+1.6%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 572 resolved cases by this examiner. Grant probability derived from career allow rate.

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