Prosecution Insights
Last updated: October 02, 2026
Application No. 18/245,099

METHODS FOR DEPOSITING PIEZOELECTRIC MATERIALS, AND MATERIALS DEPOSITED THEREWITH

Non-Final OA §103
Filed
Mar 13, 2023
Priority
Oct 16, 2020 — provisional 63/092,820 +1 more
Examiner
KLIMOWICZ, WILLIAM JOSEPH
Art Unit
2688
Tech Center
2600 — Communications
Assignee
Qorvo US Inc.
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
1060 granted / 1311 resolved
+18.9% vs TC avg
Strong +18% interview lift
Without
With
+18.2%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
46 currently pending
Career history
1351
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
44.7%
+4.7% vs TC avg
§102
29.6%
-10.4% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1311 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 19, 2026 has been entered. Examiner Comments The Examiner has cited particular columns and line numbers, paragraphs, or figures in the reference(s) as applied to the claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant, in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Deinz et al. (US 2019/0296710 A1). As per claim 1, Deinz et al. (US 2019/0296710 A1) discloses a method of depositing material onto a substrate (e.g., 4), and a structure formed thereby, as per claim 14, the method comprising: depositing a first seed material (e.g., 31) onto a wafer substrate (e.g., 4) at a pressure of 10 milliTorr (mTorr) to 20 mTorr (e.g., see, inter alia, paragraph [0072]) to form a pre-seed layer (31), the wafer substrate (4) having a face that defines a normal (e.g., a perpendicular line) to the substrate (4), the pre-seed layer (31) having a surface roughness (e.g., see, inter alia, paragraph [0078]); depositing a second seed material (e.g., 51 - which is considered a seed layer since its texture and incidence of its c-axis is adopted by the bulk piezoelectric layer (52)) onto at least a portion of the pre-seed layer (31) at an off- normal incidence angle (e.g., see, inter alia, paragraphs [0065, 0066, 0074]) relative to the normal to the substrate to form a seed layer (e.g. 51) on the portion of the pre-seed layer (31), the pre-seed layer being different that the pre-seed layer (e.g., the seed layer (51) is different from the pre-seed layer (31) at least in terms of its thickness - see, inter alia, paragraphs [0071, 0086] and Figs. 3A-3D of Deinz et al. (US 2019/0296710 A1)); and depositing a bulk piezoelectric material (e.g., 52) onto at least a portion of the seed layer (51) to form a bulk piezoelectric layer having a c-axis tilt of about 35 degrees or greater (e.g., see, inter alia, paragraph [0080]) relative to the normal to the substrate and a surface roughness (e.g., see, inter alia, paragraph [0078]). Additionally, as per amended claims 1 and 14, Deinz et al. (US 2019/0296710 A1) further discloses wherein the bulk piezoelectric material (e.g., 52) being different than the second seed material (e.g., 51). More concretely, the seed layer (51) is different from the bulk piezoelectric layer (52), in at least one aspect. As set forth in paragraph [0058] of Deinz et al. (US 2019/0296710 A1), the layer (51) of the crystalline bulk layer 50, is formed in a first growth step, with metal atoms deposited at a first incidence angle α; the bulk piezoelectric material (e.g., 52) is formed by the deposition of metal atoms at a second incidence angle β, wherein β is different from α – see paragraph [0058] of Deinz et al. (US 2019/0296710 A1). Note claims 1 and 14 do not require that the composition of the bulk piezoelectric material (e.g., 52) is different than the second seed material (e.g., 51), only that the two materials are different is some aspect (which claims 1 and 14, as presently drafted, fail to specify). As such, Deinz et al. (US 2019/0296710 A1) is still seen to meet the limitation “the bulk piezoelectric material being different than the second seed material.” As per claim 1 (and analogously, claim 14), Deinz et al. (US 2019/0296710 A1) remains silent with respect to wherein the pre-seed layer has a surface roughness from 1 nanometer (nm) to 10 nm, and wherein the surface roughness of the bulk piezoelectric material is 4.5 nm or less. As per claim 3 (and analogously, claim 15), Deinz et al. (US 2019/0296710 A1) remains silent with respect to wherein the surface roughness of the pre-seed layer is from 3 nm to 5 nm. Deinz et al. (US 2019/0296710 A1), however, readily recognizes that the surfaces of the corresponding pre-seed layer and the bulk piezoelectric material can be "roughened" in order to advantageously "improve the ability of the subsequently grown bulk layer crystals to orient during the deposition." See paragraph [0078] of Deinz et al. (US 2019/0296710 A1). As such, as per claims 1, 3, 14, and 15, the Examiner maintains that it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the instant invention to satisfy the claimed range(s) and/or dimension(s) (i.e., the surface roughness from 1 nanometer (nm) to 10 nm, and wherein the surface roughness of the bulk piezoelectric material is 4.5 nm or less) as set forth in claim 1 as well as claim 3 (and claims 14 and 15), particularly in light of the teachings of Deinz et al. (US 2019/0296710 A1) as a whole, through routine optimization/experimentation. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 105 USPQ 233, 235 (CCPA 1955). Additionally, it has been held that determining the optimal value of a result effective variable would have been obvious and ordinarily within the skill of the art. In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980). As per claim 2, wherein the first seed material (31) is deposited at a pressure of 12 mTorr to 18 mTorr (e.g., see, inter alia, paragraph [0072]). As per claim 4, wherein the second seed material (e.g., 51) is deposited at a pressure of less than 5 mTorr (e.g., see, inter alia, paragraph [0075]). As per claim 5, wherein the off-normal incidence angle for depositing the second seed material (e.g., 51) is deposited at an off-normal incidence angle of greater than 10 degrees (e.g., see, inter alia, paragraph [0066]). As per claim 6, wherein the off-normal incidence angle for depositing the second seed material is up to about 85 degrees (e.g., see, inter alia, paragraph [0066]). As per claim 7, wherein the bulk piezoelectric material (52) is deposited at a "second" off-normal angle of incidence relative to the normal of the substrate (e.g., see, inter alia, paragraph [0066]) (e.g., see, inter alia, paragraph [0080]). As per claim 8, wherein the second off-normal angle of incidence is an angle up to and about 40 degrees (e.g., see, inter alia, paragraph [0080]). As per claim 9, wherein the bulk piezoelectric material is deposited at a pressure of less than 5 mTorr (e.g., see, inter alia, paragraph [0081]). As per claim 10 (and analogously, claim 18), wherein the bulk piezoelectric layer (52) comprises a hexagonal crystal structure piezoelectric material having a c- axis having an orientation distribution in a range from (i) 12 degrees to 52 degrees or (ii) 75 degrees to 90 degrees, relative to the normal of the face of the substrate (4) (e.g., see, inter alia, paragraphs [0003, 0023, 0026, 0084]). As per claim 11 (and analogously, claim 19), wherein the bulk piezoelectric layer (52) is about 1,000 Angstroms to about 30,000 Angstroms thick (e.g., see paragraph [0017]) - as per claim 11 and claim 19, although Deinz et al. (US 2019/0296710 A1) does not set forth that the thickness varies by less than 2 % over an area of the bulk piezoelectric layer (52), it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention, to provide a consistent bulk layer thickness (such that the thickness varies by less than 2%) in order to simply provide a high-yield production method, that yields more uniform chips derived from the wafer during production. As per claim 12 (and analogously, claim 20), wherein the first seed material (pre-seed layer) (e.g., 31), the second seed material (seed layer) (e.g., 51) and the bulk piezoelectric material (layer) (e.g., 52) are the same or different and are selected from metal nitrides, metal oxides, metal oxynitrides, metal carbides, refractory metals, and combinations thereof (e.g., see, inter alia, paragraphs [0071, 0082, 0086]). As per claim 13, wherein materials of the first seed material (e.g., 31), the second seed material (e.g., 51) and the bulk piezoelectric material (e.g., 52) are the same or different and are selected from aluminum nitride, titanium nitride, hafnium nitride, tantalum nitride, zirconium nitride, vanadium nitride, niobium nitride, gallium nitride, zinc oxide, tungsten oxide, hafnium oxide, molybdenum oxide, hafnium oxynitride, titanium oxynitride, tantalum oxynitride, titanium carbide, niobium carbide, tungsten carbide, tantalum carbide, zirconium, hafnium, tungsten, molybdenum, and combinations thereof (e.g., see, inter alia, paragraphs [0071, 0082, 0086]). As per claim 16, wherein the seed layer (e.g. 51) has the first c-axis tilt and the bulk piezoelectric layer (e.g., 52) has the second c-axis tilt that substantially aligns with the first c-axis tilt. (e.g., see, inter alia, paragraph [0013]). As per claim 17, wherein the second c-axis tilt is about 35 degrees to about 52 degrees (e.g., see, inter alia, paragraphs [0013, 0016]). Response to Arguments Applicant's arguments filed August 19, 2026 have been fully considered but they are not persuasive. Applicant states: Amended claim 1 recites "the bulk piezoelectric material being different than the second seed material." Applicant respectfully submits that the mapping is off-base. For example, portion 51 and portion 52 in Deniz consist of the same material, and portion 51 and portion 52 do not map to the claimed seed layer and the claimed bulk piezoelectric layer. Portion 51 and portion 52 are different portions of the same bulk layer, which is an active piezoelectric material. (Emphasis added). For example, [0058] of Deniz refers to "A first portion 51 of a crystal line bulk layer 50 (FIG. 3B) is deposited onto the seed layer 31 in the first growth step shown in FIG. 3A" and "in a second growth step, shown in FIG. 3C, the atoms in the deposition flux 10 are deposited at a second incidence angle 3, resulting in the second portion 52 of the bulk layer 50." Thus, Deniz has two phases in forming two portions of the same bulk layer. See p. 7 of the Response filed on August 19, 2026. The Examiner disagrees, based upon the presently drafted claim language. That is, as set forth in the rejection, supra, Deinz et al. (US 2019/0296710 A1) further discloses wherein the bulk piezoelectric material (e.g., 52) being different than the second seed material (e.g., 51). More concretely, the seed layer (51) is different from the bulk piezoelectric layer (52), in at least one aspect. As set forth in paragraph [0058] of Deinz et al. (US 2019/0296710 A1), the layer (51) of the crystalline bulk layer 50, is formed in a first growth step, with metal atoms deposited at a first incidence angle α; the bulk piezoelectric material (e.g., 52) is formed by the deposition of metal atoms at a second incidence angle β, wherein β is different from α – see paragraph [0058] of Deinz et al. (US 2019/0296710 A1). Note claims 1 and 14 do not require that the composition of the bulk piezoelectric material (e.g., 52) is different from the second seed material (e.g., 51), only that the two materials are different is some aspect (which claims 1 and 14, as presently drafted, fail to specify). As such, Deinz et al. (US 2019/0296710 A1) is still seen to meet the limitation “the bulk piezoelectric material being different than the second seed material.” Additionally, the Applicant opines: Second the Action asserts that the claimed surface roughness ranges are obvious as routine optimization of Deniz. Office Action, 5-6. Claim 1 continues to recite "wherein the pre-seed layer having a surface roughness from 1 nanometer (nm) to 10 nm" and the bulk piezoelectric layer having "a surface roughness of 4.5 nm or less." Applicant submits that this assertion is off-base. Applicant's Specification describes a technical problem where baseline films exhibit a degraded c-axis tilt of about 10 degrees "due to smoothing of the bottom electrode from CMP process." Applicant's Specification, [0014]. To address this problem, Applicant's Specification describes test wafers that receive electrode CMP processes and are formed with a thin pre-seed layer. Applicant's Specification, [0103]. Introducing this thin pre-seed layer at a high pressure provides a rough surface that allows subsequent seed crystal planes "to align themselves with the incoming flux." Applicant's Specification, [0103]. This pre-seed layer acts as a functional masking layer, as the rough surface of the pre-seed layer "renders a seed layer deposited thereon indifferent to incoming surface roughness variations of the bottom electrode." Applicant's Specification, [0026]. This engineered structure provides c-axis piezoelectric layers with "less variation in the tilt axis behavior," which provides "devices that function more consistently." Id. For example, claim 1 continues to recite the parameters that generate this functional masking layer by "depositing a first seed material onto a wafer substrate at a pressure of 10 milliTorr (mTorr) to 20 mTorr to form a pre-seed layer," to achieve a pre-seed layer "having a surface roughness from 1 nanometer (nm) to 10 nm." As described above, the engineered roughness masks the smooth electrode and enables the subsequently deposited bulk piezoelectric layer to achieve the "a bulk piezoelectric layer having a c-axis tilt of about 35 degrees or greater relative to the normal to the substrate and a surface roughness of 4.5 nm or less," recited by claim 1. Deniz is not understood to describe or render obvious the above-noted features of amended claim 1. See p. 8 of the Response filed on August 19, 2026. The Examiner disagrees. As per claim 1 (and analogously, claim 14), Deinz et al. (US 2019/0296710 A1) remains silent with respect to wherein the pre-seed layer has a surface roughness from 1 nanometer (nm) to 10 nm, and wherein the surface roughness of the bulk piezoelectric material is 4.5 nm or less. As per claim 3 (and analogously, claim 15), Deinz et al. (US 2019/0296710 A1) remains silent with respect to wherein the surface roughness of the pre-seed layer is from 3 nm to 5 nm. Deinz et al. (US 2019/0296710 A1), however, readily recognizes that the surfaces of the corresponding pre-seed layer and the bulk piezoelectric material can be "roughened" in order to advantageously "improve the ability of the subsequently grown bulk layer crystals to orient during the deposition." See paragraph [0078] of Deinz et al. (US 2019/0296710 A1). As such, as per claims 1, 3, 14, and 15, the Examiner maintains that it would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the instant invention to satisfy the claimed range(s) and/or dimension(s) (i.e., the surface roughness from 1 nanometer (nm) to 10 nm, and wherein the surface roughness of the bulk piezoelectric material is 4.5 nm or less) as set forth in claim 1 as well as claim 3 (and claims 14 and 15), particularly in light of the teachings of Deinz et al. (US 2019/0296710 A1) as a whole, through routine optimization/experimentation. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 105 USPQ 233, 235 (CCPA 1955). Additionally, it has been held that determining the optimal value of a result effective variable would have been obvious and ordinarily within the skill of the art. In re Boesch, 617 F.2d 272, 276, 205 USPQ 215, 219 (CCPA 1980). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to William J Klimowicz whose telephone number is (571)272-7577. The examiner can normally be reached Monday-Thursday, 8:00AM-6PM, ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Lim can be reached at (571)270-1210. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WILLIAM J KLIMOWICZ/ Primary Examiner, Art Unit 2688
Read full office action

Prosecution Timeline

Show 5 earlier events
May 04, 2026
Response Filed
May 21, 2026
Final Rejection mailed — §103
Jul 01, 2026
Interview Requested
Aug 04, 2026
Examiner Interview Summary
Aug 04, 2026
Applicant Interview (Telephonic)
Aug 19, 2026
Request for Continued Examination
Aug 20, 2026
Response after Non-Final Action
Sep 04, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+18.2%)
2y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1311 resolved cases by this examiner. Grant probability derived from career allowance rate.

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