Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 March 2026 has been entered.
Response to Arguments
Applicant's arguments filed 19 March 2026 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Haghighat.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-13, 18, 25 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (US 2024/0291611 as supported by the corresponding passages and figures of WO 2022/077138) in view of Matsumura et al. (WO 2022/029900) and Haghighat et al. (US 2023/0300806 as supported by U.S. Provisional application No. 63/049,932, especially para. 95). For dependent claims herein, the motivation to combine is the same as the parent claim unless otherwise noted.
Regarding claim 1, Sun discloses a user equipment (fig. 3), comprising: a transceiver (item 330); one or more memories (item 306) that store processor-executable code; and one or more processors (item 302) configured to execute the processor-executable code and cause the user equipment to (para. 81-82): receive a radio resource control (RRC) configuration (fig. 12, RRC AP SRS-ResourceSet; para. 133) via the transceiver, wherein the RRC configuration includes a plurality of indications specifying a plurality of time occasions (fig. 12, AP SRS-ResourceSet) relative to a reference slot (para. 133; note: slot offsets) for transmission of a sounding reference signal (SRS) by the user equipment (para. 32, Aperiodic SRS; figs. 9-10 and 13; paras. 130, 132 (especially the last sentence) and 134; note: slot offset between the slot of the DCI and the slot of the AP-SRS), the plurality of indications comprising a first indication of a time from the reference slot (fig. 12, any of the slot offsets), the plurality of indications further comprising a second indication of a time from the reference slot (fig. 12, any of another of the slot offsets), receive a downlink control information (DCI) comprising a bit field (para. 133, third-from-last sentence), and transmit the SRS via the transceiver (figs. 7 (step 714) and 12-13; paras. 126, 131 and 134; note: SRS transmission at the indicated slot or the next available slot based on the indicated slot offset).
However, Sun fails to disclose the plurality of indications comprising a first indication for a first SRS resource set of a first quantity of slots offset from the reference slot, the plurality of indications further comprising a second indication for a second SRS resource set of a second quantity of slots offset from the reference slot, wherein the first quantity of slots is different from the second quantity of slots, receive a downlink control information (DCI) comprising a bit field, and transmit the SRS via the transceiver and via a first slot that is identified based on a mapping of a value carried by the bit field to the first indication or the second indication. However, Matsumura and Haghighat disclose these features (Matsumura, figs. 1, 5A, 7B, 10 and 16; note: fig. 5A shows different slot offset values where each value is a quantity of slots from a reference slot; paras. 26-30 and 60,
“The SRS request field that triggers A-SRS is included, for example, in the DCI formats 0_1, 0_1, 1_1, 1_2, 2_3.
As in the example of FIG. 1, among the values (code points) of the 2-bit SRS request field, three values 01, 10 and 11 other than the value 00 are associated with (mapped) one or more SRS resource sets.
The size of the SRS request field in the DCI format 0_2, 1_2 may be 0, 1, 2, or 3 bits. As in the example of FIG. 2, among the values (code points) of the 1-bit SRS request field, the value 1 is associated (mapped) with one or more SRS resource sets.
The time between the A-SRS trigger and the SRS transmission is the value k (slot offset) set by the RRC.
The SRS resource set information element (SRS-ResourceSet) includes a slot offset and an A-SRS resource trigger list (aperiodicSRS-ResourceTriggerList) for A-SRS. That is, the slot offset and the A-SRS resource trigger list are set for each SRS resource set. If no slot offset is set, the UE applies no offset (value 0). The A-SRS resource trigger list contains one or more A-SRS resource trigger (aperiodicSRS-ResourceTrigger) information elements (states, IDs). The A-SRS resource trigger indicates a DCI code point that sends an SRS according to the SRS resource set settings it is included in.
As in the example of FIG. 5A, among the values from 0 to 32 of the slot offset, the number of candidates set by the RRC parameter may be 16 or less. In this case, as in the example of FIG. 5B, the list index specified by the slot offset field may be from 1 to 16 (or 0 to 15), and the size of the slot offset field is 4 bits. May be good. As a result, the number of MAC CE octets (overhead) can be reduced.”;
Haghighat, figs. 2-4 and 9-10, and paras. 99, 102-103 and 117-161; note: SRS resource sets having different slotOffset values (para. 99, first sentence) and using an SRS resource set based on a DCI (para. 99, second sentence).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have the plurality of indications comprising a first indication for a first SRS resource set of a first quantity of slots offset from the reference slot, the plurality of indications further comprising a second indication for a second SRS resource set of a second quantity of slots offset from the reference slot, wherein the first quantity of slots is different from the second quantity of slots, receive a downlink control information (DCI) comprising a bit field, and transmit the SRS via the transceiver and via a first slot that is identified based on a mapping of a value carried by the bit field to the first indication or the second indication in the invention of Sun. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, providing specific signaling for an SRS trigger and effecting an SRS transmission as is known in the art (Matsumura, figs. 1, 5A, 7B and 16, and paras. 26-30 and 60; Haghighat, figs. 2-4 and 9-10, and paras. 99, 102-103 and 117-161; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Regarding claim 2, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the plurality of indications comprises: a first delay value; and a second delay value (Sun, fig. 12; slotOffset 0, slotOffset 1, etc.; Matsumura, fig. 5A and para. 60; Haghighat, fig. 10 and paras. 99 and 117).
Regarding claim 3, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 2, wherein: the first delay value indicates a first available slot (Sun, para. 102; para. 114, especially the last two sentences; para. 115; note: the base station determines an available (valid) slot; para. 133, especially the second sentence; note: each offset indicates a first available (valid) slot; fig. 13 and para. 134; note: the UE determines an available (valid) slot; Matsumura, fig. 5A and para. 60); and the second delay value indicates a second available slot (Sun, figs. 12-13; note: slot offsets; Matsumura, fig. 5A and para. 60; Haghighat, fig. 10 and paras. 99 and 117).
Regarding claim 4, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the plurality of indications comprises: a first delay value (Sun, fig. 12; note: an offset is a delay value); and an indication to use a first available slot (figs. 7 (step 714) and 12-13; paras. 102 and 114-115; note: a base station determines the available (valid) slot; paras. 126, 131 and 134; note: the UE determines the available (valid) slot; note: SRS transmission at the indicated slot or the next available slot based on the indicated DCI slot offset and based on an RRC configuration).
Regarding claim 5, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 4, wherein the indication to use the first available slot comprises a value of zero (Matsumura, fig. 5A and para. 60; note: the first offset is zero).
Regarding claim 6, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein: the plurality of indications are for a specified SRS resource set (Sun, fig. 12, RRC AP SRS-ResourceSet; Matsumura, fig. 1 and para. 30; Haghighat, fig. 10 and paras. 99 and 117); and a time domain behavior of the specified SRS resource set is aperiodic (Sun, para. 128, Aperiodic (AP) SRS; paras. 117, 124, 130 and 141; Matsumura, fig. 1 and para. 30; Haghighat, fig. 10 and paras. 99 and 117).
Regarding claim 9, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the one or more processors are further configured to execute the process-executable code and cause the user equipment to: select the first indication based on the value carried in by the bit field (Matsumura, figs. 1 and 5A, and paras. 26-30; note: DCI having an index for an offset).
Regarding claims 10, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the DCI comprises a DCI format 0_1, a DCI format 0_2, a DCI format 1_1, or a DCI format 1_2; and the bit field is a single bit (Matsumura, paras. 26-28).
Regarding claim 11, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 9, wherein the plurality of indications map: a first value of the bit field to a first delay value for the transmission of the SRS; and a second value of the bit field to a second delay value for the transmission of the SRS (Sun, fig. 12; note: a DCI slot offset of the RRC-configured slot offsets; Matsumura, figs. 1 and 5A; paras. 26-30; note: indexes for slot offsets; Haghighat, fig. 10 and paras. 99 and 117).
Regarding claim 12, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 9, wherein the plurality of indications map: a first value of the bit field to a first delay value for the transmission of the SRS; and a second value of the bit field to an indication to use a first available slot for the transmission of the SRS (Sun, fig. 12; note: a DCI slot offset of the RRC-configured slot offsets; para. 134 and fig. 13; note: indication of slot offset for next (first) available (valid) slot; Matsumura, figs. 1 and 5A, and paras. 26-30 and 60; note: m-bit SRS trigger field in DCI).
Regarding claim 13, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 9, wherein: the bit field is dedicated for indicating which of a plurality of delay values is to be used for the transmission of the SRS (Sun, fig. 12; note: a DCI slot offset of the RRC-configured slot offsets; Matsumura, figs. 1 and 5A, and paras. 26-30 and 60; note: m-bit SRS trigger field in DCI), the bit field is reallocated for indicating which of the plurality of delay values is to be used for the transmission of the SRS (Sun, fig. 12 and paras. 81, 98, 100 and 117-118; note: a DCI slot offset of any RRC-configured slot offset where the DCI is used for dynamic (repeated) channel quality estimation and improved communications; Matsumura, figs. 1 and 5A, and paras. 26-30 and 60; note: m-bit SRS trigger field in DCI), or an SRS request field is used to indicate the bit field (Matsumura, fig. 1 and paras. 26-30; note: SRS trigger field is the bit field to enact a UE SRS transmission).
Regarding claim 18, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the one or more processors are further configured to execute the processor-executable code and cause the user equipment to: responsive to determining that a bit field of the DCI for the plurality of indications is disabled (Sun, para. 134; para. 123, third sentence; note: disabled in its broadest reasonable interpretation is an offset that is not valid - specification of the instant application, para. 129),
Regarding claim 25, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the one or more processors are further configured to execute the processor-executable code and cause the user equipment to: determine an available slot for the transmission of the SRS based on the first indication (Sun, fig. 13 and para. 134; Matsumura, fig. 5A and para. 60); and transmit the SRS during the available slot (Sun, fig. 13 and para. 134; Matsumura, fig. 5A and para. 60; Haghighat, fig. 10 and paras. 99 and 117).
Regarding claim 30, these limitations are rejected on the same ground as claim 1.
Regarding claim 31, Sun in view of Matsumura and Haghighat teaches and makes obvious the user equipment of claim 1, wherein the DCI comprising the bitfield carrying the value mapped to the first indication or the second indication triggers the transmission of the SRS and does not schedule a data transmission (Sun, para. 133, third-from-last sentence; Haghighat, paras. 99 and 117; Haghighat, para. 131; note: RNTIs indicating an SRS offset for SRS transmission or DCI for PDSCH scheduling).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat as applied to claim 1 above, and in further view of Wei et al. (US 12,336,018).
Sun discloses the user equipment of claim 1, wherein the RRC configuration comprises the plurality of indications (fig. 12, RRC slotOffset 0, slotOffset 1, etc.) and Haghighat discloses RRC signaling for SRS resource sets (para. 241, last sentence). However, Sun in view of Matsumura and Haghighat fails to teach and make obvious the RRC configuration comprising a first field and a second field for the plurality of indications. Wei discloses bit fields for an RRC message (col. 4, lines 45-62; note: RRC information element fields include offsets and a slotOffset field). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have the RRC configuration comprise a first field and a second field for the plurality of indications in the invention of Sun in view of Matsumura and Haghighat. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, physically implementing (or formatting) RRC signaling with various information as is known in the art (Wei, col. 4, lines 45-62; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat as applied to claim 9 above, and in further view of Go et al. (US 2024/0031097).
Sun in view of Matsumura and Haghighat teaches and makes obvious SRS resource sets for a bandwidth part (Matsumura, figs. 7B and 10; Haghighat, paras. 223 and 232) but fails to teach and make obvious the user equipment of claim 9, wherein the one or more processors are further configured to execute the processor-executable code and cause the user equipment to: receive a radio resource control (RRC) message specifying that the value of the bit field applies to a subset of a plurality of SRS resource sets defined for a bandwidth part.
However, Go discloses this feature (fig. 9; para. 231, especially the first two sentences; para. 238, especially the second and fourth sentences; note: SRS resource sets of a BWP transmitting in respective slots based on respective DCI codepoints). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to receive a radio resource control (RRC) message specifying that the value of the bit field applies to a subset of a plurality of SRS resource sets defined for a bandwidth part in the invention of Sun in view of Matsumura and Haghighat. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, facilitating aperiodic SRS transmissions for a BWP as is known in the art (Go, fig. 9 and paras. 231 and 238; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat as applied to claim 1 above, and in further view of Liu et al. (US 2024/0031097).
Sun in view of Matsumura and Haghighat teaches and makes obvious selecting a first indication based on a value of a bit field (Matsumura, figs. 1 and 5A, and paras. 26-30; note: DCI having an index for an SRS transmission offset) but fails to teach and make obvious the user equipment of claim 1, wherein: the one or more processors are further configured to execute the processor-executable code and cause the user equipment to receive a group common downlink control information (DCI); the group common DCI includes a bit field for indicating at least one delay parameter for the transmission of the SRS; and the processor and the memory are further configured to select the first indication based on a value of the bit field.
However, Liu discloses a group common DCI comprising a delay parameter for a transmission of SRS (para. 99, third sentence; para. 192; note: triggered SRS offset). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to receive a group common downlink control information (DCI), the group common DCI includes a bit field for indicating at least one delay parameter for the transmission of the SRS, and have the processor and the memory further configured to select the first indication based on a value of the bit field in the invention of Sun in view of Matsumura and Haghighat. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, providing a transmission parameter to more than on UE as is known in the art (Liu, paras. 99 and 192; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat and Liu as applied to claim 19 above, and in further view of Harada et al. (WO 2021/140671).
Regarding claims 20-21, Sun in view of Matsumura and Haghighat and Liu teaches and makes obvious a group common DCI is a format 2_3 DCI (Liu, para. 196, first two sentences) but fails to teach and make obvious the user equipment of claim 19, wherein: the group common DCI comprises a component carrier block that includes the bit field, the group common DCI comprises a payload that includes the bit field, and the bit field comprises a plurality of bits that are mapped to a plurality of component carriers scheduled by the group common DCI.
However, Harada discloses these features (figs. 3-4; para. 37, “For example, in the example shown in FIG. 2, the DCI transmitted from the base station 20 via the PDCCH of CC # 1 causes the PDSCH transmission (or PUSCH transmission) of CC # 2 and CC # 3 to the terminal 10. Is scheduled. Further, it is assumed that SUL is not set for CC # 2 and SUL is set for CC # 3. In this case, in the DCI SRS request field, in addition to 2 bits for triggering the transmission of the aperiodic SRS in CC # 2, 3 bits for triggering the transmission of the aperiodic SRS in CC # 3 A total of 5 bits may be included. The terminal 10 that has received the DCI via the PDCCH of the CC # 1 has a CC based on a 2-bit value for triggering the transmission of the aperiodic SRS in the CC # 2 included in the SRS request field included in the DCI. Non-periodic SRS transmission in CC # 3 based on a 3-bit value for performing aperiodic SRS transmission in # 2 and triggering aperiodic SRS transmission in CC # 3 included in the SRS request field. Periodic SRS transmission may be performed.”; note: a DCI payload in its broadest reasonable interpretation (specification of the instant application, fig. 12 and para. 135) is the bits that include an SRS bit field; note: the bit field comprises bits that are mapped to component carriers scheduled for SRS transmission).
Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have the group common DCI comprise a component carrier block that includes the bit field, the group common DCI comprise a payload that includes the bit field, and the bit field comprise a plurality of bits that are mapped to a plurality of component carriers scheduled by the group common DCI in the invention of Sun in view of Matsumura and Haghighat and Liu. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, controlling a UE to transmit on available frequency resources as is known in the art (Harada, fig. 12 and para. 37; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat and Liu as applied to claim 19 above, and in further view of Go et al. (US 2024/0031097).
These limitations are rejected on the same ground as claim 15 based on Sun in view of Matsumura and Haghighat as described in the rejection of claim 15.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Sun in view of Matsumura and Haghighat and Liu as applied to claim 25 above, and in further view of Choi et al. (US 2020/0382250).
Sun in view of Matsumura and Haghighat fails to teach and make obvious the user equipment of claim 25, wherein the one or more processors are further configured to execute the processor-executable code and cause the user equipment to: verify that the transmission of the SRS does not collide with a higher priority uplink signal or uplink channel scheduled during the candidate slot. However, Choi discloses this feature (paras. 271-274; note: verifying in its broadest reasonable interpretation as claimed is determining or identifying an SRS resource set collision, transmitting the higher priority resource set and dropping the lower priority resource set). Therefore, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to verify that the transmission of the SRS does not collide with a higher priority uplink signal or uplink channel scheduled during the candidate slot in the invention of Sun in view of Matsumura and Haghighat. The motivation to have the modification and/or well-known benefits of the modification include, but are not limited to, handling transmission scheduling conflicts as is known in the art (Choi, paras. 271-274; MPEP 2143(I)(A)(B)(C)(D) - note: e.g., applying known techniques having predictable results).
Allowable Subject Matter
Claims 14, 16-17, 22-23 and 27-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Kevin C. Harper/
Primary Examiner, Art Unit 2462