Prosecution Insights
Last updated: July 17, 2026
Application No. 18/246,559

OPTICAL WAVEGUIDE ELEMENT, OPTICAL MODULATOR, OPTICAL MODULATION MODULE, AND OPTICAL TRANSMISSION DEVICE

Non-Final OA §103§112
Filed
Mar 24, 2023
Priority
Mar 24, 2021 — JP 2021-050410 +1 more
Examiner
CHIEM, DINH D
Art Unit
2874
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sumitomo Osaka Cement Co., Ltd.
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
393 granted / 542 resolved
+4.5% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
33 currently pending
Career history
590
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
83.9%
+43.9% vs TC avg
§102
13.9%
-26.1% vs TC avg
§112
0.7%
-39.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 542 resolved cases

Office Action

§103 §112
DETAILED ACTION Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 3, 2026 has been entered. Claims 1-16 are under consideration. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 has been amended to include the limitation a first insulating layer which is formed on the substrate and which is entirely disposed only between two adjacent electrodes among the plurality of electrodes—is not consistent with the limitation wherein a height of the first insulating layer from a surface of the substrate is higher than heights of the two adjacent electrodes. PNG media_image1.png 412 519 media_image1.png Greyscale The portion of the first insulating layer having a height higher than heights of two adjacent electrodes would no longer be entirely disposed only between two adjacent electrodes. For examination purposes, the examiner shall consider the height of the first insulating layer has a portion higher than the electrodes and a portion in between the two adjacent electrodes. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi et al. (US 2019/0302566 A1, herein “Oishi”) in view of Ichikawa et al. (US 8,644,647 B2, herein “Ichikawa”). Regarding claim 1, Oishi discloses an optical waveguide (optical waveguide modulator 1) comprising: a substrate (1); an optical waveguide (2) formed on the substrate; a plurality of electrodes (43, 33, 43) for controlling a light wave propagating through the optical waveguide (2); and the intermediate step of photoresist layer (53) provided for forming the electrodes in the structure as shown in Fig. 2. Oishi does not explicitly teach a first insulating layer which is formed on the substrate and which has a portion disposed between two adjacent electrodes and a portion disposed higher than the electrodes. Ichikawa teaches an optical control device such as a waveguide type optical modulator (col. 1, lines 14-19) as shown in Fig. 4. The optical control device has waveguide 2, electrodes (4, 5), and insulator (low dielectric constant film 8). The insulator (8) has a portion provided between the adjacent electrodes (4, 5), and a portion higher than the adjacent electrodes (4, 5). PNG media_image2.png 227 323 media_image2.png Greyscale It would have been obvious to one having ordinary skill at the time of filing to recognize the Ichikawa and Oishi are in the same field of endeavor, optical modulator and optical control circuits, and the modification of the insulator in Ichikawa would be modifiable to the optical modulator of Oishi by forming the insulator in between the electrodes in Oishi optical modulator. Ichikawa teaches the motivation for using an insulator between the electrodes for the ability to adjust the impedance or microwave refractive index in the control electrode. Furthermore, the insulator disposed between the signal electrode and ground electrodes give a degree of freedom in wiring of the control electrodes (Ichikawa: Col. 4, lines 54-67). Claim 2. Oishi in view of Ichikawa (herein “Oishi / Ichikawa ”) teach two electrodes are disposed at positions sandwiching the optical waveguide in a plane of the substrate (Oishi: Fig. 3). Claim 3. Oishi / Ichikawa teach a clearance between the two electrodes is 15 micron or less. Mattis teaches the structure of Fig. 1 is in micrometer-scale structure, having a width of approximately 5 microns and a height of less than 1 micron (Mattis: Para [0081]). Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi / Ichikawa as applied to claim 1 above, and further in view of Mattis et al. (US 2021/0336050 A1, herein “Mattis”). Claims 15-16. Oishi / Ichikawa teach the optical waveguide device according to claim 1, wherein Oishi / Ichikawa teach the optical waveguide (2 in Fig. 2) is formed on a main surface of the substrate (1). The substrate in Oishi’s device have has a reference surface is a surface of a portion of the main surface (1) of the substrate where the optical waveguide is not formed. Two adjacent electrodes (3, 4) are formed on the reference surface. The two adjacent electrodes (3, 4) are disposed at a position sandwiching the optical waveguide in the main surface of the substrate (2). Each of the two adjacent electrodes extends along the optical waveguide (top view in Fig. 1A) while maintaining a cross-sectional shape is stepped thick as a distance from the adjacent optical waveguide increases. Oishi / Ichikawa further teach a portion of the insulator (Ichikawa: low dielectric constant film 8) are formed between two adjacent electrodes and a portion of the insulator (8) has a height higher than a height of each of the two adjacent electrodes from the reference surface. However, Oishi / Ichikawa do not teach the first insulating layer partially covers a surface of each of the two adjacent electrodes, facing the first insulator, without covering the entire facing surface of the either electrode. Mattis teach an optical control circuit in Fig. 1 wherein the waveguide (102) is formed on the substrate (104), an insulating layer 104a is formed above the waveguide (104) and between two electrodes (108a and 106a). The insulating layer (104a) is higher than the two adjacent electrodes (108a and 106a) and the insulating layer (104a) partially covers electrode (108a) and electrode (106a) leaving a portion of both electrodes exposed such that a metalized region (114, 116) can form an electrical connection to the optical control circuit using vias. PNG media_image3.png 302 543 media_image3.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to recognize the exposed electrode regions, as shown in Mattis, is a design feature that is easily modifiable in semiconductor manufacturing process. Mattis teaches a motivation for having access to the electrodes (108a, 106a) may be configured to apply a voltage signal of design-specific, or implementation-specific magnitude to control electrode 106 via the metallized region 116 (Para [0074]). Claims 4-10 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi / Ichikawa and in further view of Ishikawa et al. (JP-2018-28623- A, herein “Ishikawa”). Regarding claims 4-8 and 10, Oishi / Ichikawa teach the invention of claim 1 but do not teach the thickness of the first insulating layer from the surface of the substrate is 1 micron or more and 10 micron or less. Oishi / Ichikawa also do not teach the height of the first insulating layer and the height of the two electrodes from the surface of the substrate is 5 micron or less. Ishikawa teaches the insulating layer (resin film 30) is formed of a resin formed over the waveguide having a thickness of 4 micron (Para [0029]). Ishikawa further teaches providing a protective layer 68 as a second insulating layer covering a plurality of electrodes different from the two electrodes formed on the substrate (Para [0028]). The invention of Ishikawa is drawn to one of an optical modulation (Mach-Zehnder) (Para [0010]). It would have bene obvious to one having ordinary skill in the art to recognize the insulating layer of Ishikawa taught using the technique of spin-coated would have been modifiable to the invention of Oishi / Okamoto / Mattis. One would be motivated to optimize the insulation layer to provide optical TIR and electrical isolation between the two electrodes. Regarding claim 9, Oishi / Ichikawa and in further view of Ishikawa teach the invention of claim 8, but do not teach the second insulating layers are formed as individual insulating layers separated from each other covering respective bias electrodes of the Mach-Zehnder optical waveguide. It would have been obvious to one of ordinary skill in the art at the time the invention was made to duplicate the insulating layers to provide additional insulation since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8 (1977). Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Oishi / Ichikawa in further view of Nakata et al. (JP-2020-166160-A, herein “Nakata”). Oishi / Ichikawa teach the invention of claim 1, but do not teach an optical modulator comprising a housing that houses the optical waveguide device; and optical fiber that inputs light to the optical waveguide device; and an optical fiber that guides light output by the optical device to outside the housing. Nakata teaches a modulation in a housing (102) having an optical fiber (114) that inputs light to the optical waveguide device and an optical fiber that guides light output (120) by the optical waveguide device to outside the housing (Fig. 1). Within the housing the modulator is provided with a drive circuit (Para [0005]) and an electronic circuit (106) that generates an electrical signal for causing the optical waveguide device to perform a modulation operating It would have been obvious to one having ordinary skill in the art to recognize optical modulator functions inside a protective housing provided with input output optical waveguides. One would be motivated to provide a housing to protect the modulator from environmental damage. The drive circuit and electronic circuit would be necessary for the Mach-Zehnder modulator to operate. Response to Arguments Applicant’s arguments with respect to claims 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIN D CHIEM/Examiner, Art Unit 2874 /THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
Read full office action

Prosecution Timeline

Mar 24, 2023
Application Filed
Apr 29, 2025
Non-Final Rejection mailed — §103, §112
Jul 29, 2025
Response Filed
Dec 30, 2025
Final Rejection (signed) — §103, §112
Feb 09, 2026
Final Rejection mailed — §103, §112
Apr 03, 2026
Request for Continued Examination
Apr 07, 2026
Response after Non-Final Action
Jun 24, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
89%
With Interview (+16.4%)
3y 0m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 542 resolved cases by this examiner. Grant probability derived from career allowance rate.

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