DETAILED ACTION
The instant action is in response to application 4 April 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Germany on 5 October 2020.
Response to Arguments
The specification objections have been withdrawn.
The claim objections have been withdrawn.
The 112(b) rejections have been withdrawn.
Applicant’s remarks on the merits have been considered but are not persuasive. Applicant argues that Yamaguchi does not teach “wherein two respective portions of the capacitor electrical conductors extend in the inner space of the power module and are respectively bonded to the inner DC electrical conductors”. Judging by applicants remarks, it appeared applicant thought examiner was referring to the external snubber circuit. However, the RC snubber is external, the internal capacitor is clearly shown within the module. As such, this argument is not persuasive. Even if the office pointed to the external capacitor however,, making things separate or integral (MPEP 2144.04V) is not patentable nor is changing the location of parts (MPEP 2144.04VI). As such, the rejection should (unfortunately) be sustained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-10, 12, 15, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi (US 20120106220).
As to claim 1, Yamaguchi discloses Electrical system comprising: a power module (Fig. 7) comprising: a first substrate (26n), a second substrate (26p) facing said first substrate, the first and second substrates defining between them an inner space of the power module (the encapsulated area between the two substrates), two switches (Swp, Swn) connected in series, forming a switching leg and supported by the first or second substrate (Fig. 1 is supported by 26p or 26n, depending on which way gravity/normal force goes) and extending in the inner space (20, area between switches and SC) of the power module, and inner electrical conductors extending in the inner space (26p, 24p, 34p, 36, 24n, 34n, 26n) of the power module and connecting the switching leg, the inner electrical conductors including two inner DC electrical conductors (24p, 34n) for receiving a DC voltage; a DC link capacitor (SC) connected in parallel to the switching leg and comprising two capacitor electrical conductors (items connecting 26p SC and 26n) facing each other and extending at least partially outside the inner space (it has area outside the encapsulated space 20 between 26p/26n which are fed a differential voltage for the capacitor and switches – See Fig. 1) of the power module and respectively connected to the inner DC electrical conductors for stabilizing the DC voltage (capacitors do not change voltage quickly).
Fig. 7 does not explicitly teach an overmolding encapsulating at least partially the substrates, the switches, the inner electrical conductors, the DC link capacitor with its capacitor electrical conductors wherein two respective portions of the capacitor electrical conductors extend in the inner space of the power module and are respectively bonded to the inner DC electrical conductors.
Fig. 20B teaches an overmolding (70) encapsulating at least partially the substrates, the switches, the inner electrical conductors, the DC link capacitor (19) with its capacitor electrical conductors (See Fig. 20B, which shows only an RC circuit outside of the connected power module) the DC link capacitor (19) with its capacitor electrical conductors wherein two respective portions of the capacitor electrical conductors extend in the inner space of the power module and are respectively bonded to the inner DC electrical conductors. .
It would have been obvious to one of ordinary skill in the art to combine the teachings of Fig. 7 and Fig. 20B to provide further protection for the power module.
He does not explicitly teach soldering. This however is old and well known and therefore not patentable (See MPEP 2144.03 and US 6144269 Claim 2, US 6407532 Claim 5, US 20150187502 Claim 15).
As to claims 3, 17, 19 Yamaguchi (Fig. 7) does not teach wherein each substrate comprises a non-conductive core layer with an inner surface oriented towards the other substrate, an inner conductive layer being applied on this inner surface of the core layer, and wherein the inner conductive layer of at least one of the substrates forms at least one of the inner DC electrical conductors (Fig. 2 discloses the non-conductive core layers with the claimed features, and the substrates are electrical conductors).
Yamaguchi Fig. 2 teaches wherein each substrate comprises a non-conductive core layer with an inner surface oriented towards the other substrate, an inner conductive layer being applied on this inner surface of the core layer, and wherein the inner conductive layer of at least one of the substrates forms at least one of the inner DC electrical conductors (Fig. 2 discloses the non-conductive core layers with the claimed features, and the substrates are electrical conductors).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Fig. 7 and Fig. 2 to reduce heat losses.
As to claim 4, Yamaguchi teaches wherein the inner conductive layer of one of the substrates forms both inner DC electrical conductors (See Fig. 7).
As to claim 5, Yamaguchi teaches wherein the inner conductive layer of one of the substrates forms one of the inner DC electrical conductors and the inner conductive layer of the other of the substrates forms the other of the inner DC electrical conductors (Taught by Fig. 7).
As to claims 7-8, 16, 18, 20 Yamaguchi discloses a capacitor. He does not explicitly teach wherein the capacitor electrical conductors are two electrically conducting films, wherein the films are rolled up together. However, rolled film capacitors are old and well known and therefore not patentable (See MPEP 2144.03 and US 4240127 Claim 1, US 425034 Claim 5, US 4578736 Claim 8).
As to claim 9 this appears to be a method claim corresponding to claim 1 and is obvious for similar reasons.
As to claim 10, Yagamuchi teaches further comprising: obtaining the DC link capacitor; separating two respective portions of the capacitor electrical conductors; and wherein connecting the capacitor electrical conductors to the inner DC electrical conductors comprises inserting the separated portions into the inner space of the power module and connecting the separated portions to the DC electrical conductors (this appears to correspond to the soldering claim above, and is obvious for similar reasons).
As to claims 12, 15 Yamaguchi (Fig.7) does not disclose wherein, for each substrate, an outer conductive layer is being applied on an outer surface of the core layer, opposite the inner surface of the core layer, and further comprising a cooling system for cooling each outer conductive layer (See Fig. 2 showing heat sinks 44/48 on the outer surface).
Yamaguchi Fig. 2 teaches wherein, for each substrate, an outer conductive layer is being applied on an outer surface of the core layer, opposite the inner surface of the core layer, and further comprising a cooling system for cooling each outer conductive layer (See Fig. 2 showing heat sinks 44/48 on the outer surface).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Fig. 7 and Fig. 2 to reduce heat losses.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached on 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839
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