Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments in “Remarks – 04/07/2026- Applicant Arguments/Remarks Made in an Amendment”, with the “Amendment/Req. Reconsideration-After Non-Final Reject -01/09/2026", have been fully considered, but they are not persuasive, because of the following:
Applicant’s amendment of claims 1-6, 8-10 and 13-15 necessitated the shift in new grounds of rejection detailed above in section below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitake et al. (US 2002/0195609 A; hereinafter Yoshitake) in view of Weiss et al. (US 2011/0204322 A1; hereinafter Weiss).
Regarding Independent Claim 1; Yoshitake (Fig.1B) discloses an optoelectronic device, comprising: a first current spreading layer (12, [0029]) made of a semiconductor material of a first conductivity type,
an active layer (13; [0029]) arranged on the first current spreading layer (12) for generating light, a second current spreading layer (14; [0030]) of a semiconductor material of a second conductivity type arranged on the active layer (13), a contact layer (16; [0030]) arranged on the second current spreading layer (14), a roughening layer (17; [0033]) arranged on the contact layer (16) and having a roughened surface (top surface) for coupling out light generated in the active layer (13), and a metal layer (23; [0033]) arranged on the contact layer (16),
and
wherein the second current spreading layer (14), the contact layer (16), and the roughening layer (17) are separate, successively stacked layers (see Fig.1B).
Yoshitake does not particularly disclose wherein the optoelectronic device is a thin film light emitting diode.
Weiss (Fig.2) in a related art discloses an optoelectronic device wherein the optoelectronic device is a thin film light emitting diode ([0054]-[0055]).
Therefore, it would have been obvious in the art before the effective filling of the application to have a thin film light emitting diode as the optoelectronic device for dramatically reducing material use while unlocking nanoscale control over light and electricity.
Regarding Claim 2. Weiss as applied in claim 1, Yoshitake ([0073]-[0074]) discloses in a related art an optoelectronic device wherein the roughening layer has a roughness of at least 100 nm and a surface of the metal layer has a roughness of less than 100 nm.
Regarding Claim 3. (Currently amended) The optoelectronic device according to claim 1, Yoshitake (Fig.8) discloses further comprising a carrier (70 or 71) on which the first current spreading layer (72; [0061]) is arranged.
Regarding Claim 4. (Currently amended) The optoelectronic device Yoshitake (Fig.8) discloses according to claim 3, wherein at least one mirror layer (78 is a highly reflective material; [0060]) is arranged between the carrier (70 or 71) and the first current spreading layer (72).
Regarding Claim 5. (Currently amended) The optoelectronic device according to claim 1, Yoshitake ([0029]) discloses wherein one of the conductivity type is a p-type conductivity (it is well known in the art to choose any desired conductivity type layer as the first or second layer and they are used interchangeably).
Regarding Claim 6. (Currently amended) The optoelectronic device according to claim 1, Yoshitake (Fig.1-8 [0030]) discloses wherein the second current spreading layer (14), the contact layer (16) and the roughening layer (17) are an epitaxially grown layer stack.
Regarding Claim 8, Weiss as applied in claim 1, Yoshitake ([0081] and [0094]) discloses in a related art an optoelectronic device wherein the first current spreading layer, the active layer, the second current spreading layer, the contact layer and/or the roughening layer comprise InGaAlP or AlGaAs.
Regarding Claim 13. Yoshitake in view of Weiss as applied in claim 9, Yoshitake does not particularly disclose using wet etching.
Weiss (Fig.2) in a related art discloses wherein the exposure of the contact area (where 4 is formed) is performed by a wet etching step ([0076]).
Therefore, it would have been obvious in the art before the effective filling of the application to use wet etching since
Regarding Claim 14. Yoshitake in view of Weiss as applied in claim 13, Yoshitake ([0063]) discloses wherein a second resist layer (referred to as resin mask) is deposited and structured above the roughening layer before the wet etching step.
Claim(s) 9-10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshitake et al. (US 2002/0195609 A; hereinafter Yoshitake).
Regarding Claim 9. Yoshitake (Fig.1-9) discloses a method for manufacturing an optoelectronic device, wherein a structure is provided comprising a first current spreading layer (112; [0068]) made of a semiconductor material of a first conductivity type, an active layer (113) for generating light arranged on said first current spreading layer (112), a second current spreading layer (114) made of a semiconductor material of a second conductivity type arranged on said active layer (113), a contact layer (116; [0069]) arranged on said second current spreading layer (114/115), and a roughening layer (117; [0069]) arranged on said contact layer (116), a surface of the roughening layer (top surface) is roughened, a contact area of the contact layer (116) is exposed, and a metal layer (118; [0070]) is deposited on the exposed contact area (116; see Fig.9C).
Yoshitake (Fig.9) does not particularly disclose a first resist layer is deposited and structured on the roughening layer before roughening the surface of the roughening layer.
Yoshitake (Figs.1-16; [0063]) discloses wherein a first resist layer is deposited and structured on the roughening layer (referred to as laser ridge surface) before roughening the surface of the roughening layer, and
wherein the first resist layer is structured such that no resist layer is located above the contact area of the contact layer.
Therefore, it would have been obvious in the art before the effective filing date of the claimed invention to use resin for roughening the roughen layer to precisely remove unwanted parts of the layer.
Regarding Claim 10. Yoshitake as applied in claim 9, Yoshitake (Fig.1-9) discloses wherein to roughen the surface of the roughening layer (117), the roughening layer (117) is etched in at least a first region (left 118) and simultaneously the roughening layer is etched in at least a second region (right 118) above the contact region of the contact layer (116).
Regarding Claim 15. Yoshitake as applied in claim 9, Yoshitake (Fig.1-16) discloses wherein a passivation layer (81) is deposited on the structure after roughening the surface of the roughening layer, and a portion of the passivation layer (81) adjacent to the contact region is removed after exposing the contact region (see [0063]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842. The examiner can normally be reached on M-F 9-5.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAJAR KOLAHDOUZAN/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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