DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendments and remarks filed September 3, 2025. Claim 1-44 are currently pending. Claims 7-9, 14-18 and 21-44 are currently withdrawn from consideration as being drawn to non-elected inventions, see response on May 11, 2025.
Response to Arguments
Applicant's arguments filed September 3, 2025 have been fully considered but they are not persuasive.
In regards to the Applicant’s arguments that the combination of Kawahito and Machida fails to teach “the first capacitor layer is capacitively coupled to the first channel layer with a first capacitance, the first capacitance corresponds to a capacitance between the first capacitor layer and the first channel layer, the first capacitor layer is capacitively coupled to the semiconductor layer with a second capacitance, and the second capacitance corresponds to a capacitance between the first capacitor layer and the semiconductor layer” (pages 21 and 22 of Applicant’s Arguments), Examiner respectfully disagrees. Both references teach that the capacitive layer (Kawahito, 28, fig. 21, Machida, n-type region in MEM 223, fig. 13) of a second conductivity type (n-type) is embedded in the substrate layer of a first conductivity (p-type, Kawahito, 21, fig. 21, Machida, 232, fig. 13). It is well known when there is a junction between an n-type material and a p-type material there is a junction capacitance. The depletion region forms due to the diffusion of electrons and holes, creating an electric field, which acts as an insulating layer between the two conducting regions of the junction. Applying a voltage across the junction stores charge in this depletion region and the charge storage creates capacitance, which is dependent on the width of the depletion region and the area of the junction. Therefore both references there would be a capacitance between the substrate of p-type and the capacitor layer n-type. The Machida reference is used to show the capacitor layer is under the gate and channel region, unlike the Kawahito reference, this increase the well size when potential is applied to the gate providing for reduced dark current and higher quality image formation (Machida, paragraph 165-169). Machida shows a junction between the capacitor layer (n-type in MEM 223) and the channel layer (p-type in MEM 223). As noted earlier this junction will have a junction capacitance, due to the formation of a charge depletion region as described above for storing charge creating a capacitance. From these arguments the combination of Kawahito and Machida does teach these newly added limitations and is proper.
In regards to the Applicant’s arguments that Cheng does not teach the reflecting portion is not overlapping the capacitor layers while in plan view reflecting light to the photoelectric conversion section, therefore there is no reason to combine Cheng with the combination of Kawahito, Machida and Cazaux (pages 23-24 of Applicant’s Arguments), Examiner respectfully disagrees. Cazaux teaches a light shielding layer (664) over the capacitive layers blocking light to the capacitive layers (MEMs) and allowing light to the photoelectric regions (P8, PZ, P4) (see fig. 6, paragraph 69), also the materials of the light shielding layer are metal, which reflects light (paragraph 69). Cazaux does not specifically teach a reflection portion that reflects light toward the photoelectric conversion region. Cheng was brought in to show the use of a reflection grid (216/222) that surrounds the photoelectric conversion element (204) and is placed above (242) and overlapping circuitry (232/240), the grid is used to reflect light toward respective photoelectric conversion elements (204), reducing crosstalk between pixels, while not allowing light to enter below the grid structures (see fig. 2 and 3). One of ordinary skill in the art would have further included a reflecting portion similar to Cheng with the shielding layer covering the capacitor layers of Kawahito as modified by Machida and Cazaux in order to ensure light is guided to the photosensor reducing cross talk and noise providing for higher quality image formation. Since, Cazaux already teaches a metal light shielding film over the MEMs to not allow direct light to enter the MEMs, then adding a reflecting portion similar to Cheng would make sense to not only block light into the MEMs, but reflect light instead into the photoelectric conversion element for increased light detection and reduced cross-talk for higher quality image capture. From this argument the rejection of claim 13 is proper in view of Kawahito, Machida, Cazaux and Cheng.
Claims 1-6, 10-13, 19 and 20 remains proper.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) in view of Machida (US 20140084138).
Re claim 1: Kawahito teaches a sensor comprising a plurality of pixels (fig. 1 and 21), wherein each of the plurality of pixels (X11 - Xnm) includes a semiconductor layer (21) of a first conductivity type (p-type), wherein the semiconductor layer (21) includes a first surface (surface where gate 37/38/32/31 are located thereon, see fig. 21) and a photoelectric conversion section (PD), and the photoelectric conversion section (PD) is configured to convert light incident on the semiconductor layer (21) into a charge (paragraph 16); a first channel layer (21 under 37) of the first conductivity type (p-type) on a first side of the photoelectric conversion section (PD) (see fig. 21, 29 is on the right/first side of the PD), wherein the first channel layer (p-type/21) is below the first surface of the semiconductor layer (21) (see fig. 21, paragraph 219), the first channel (21 under 37) is in the semiconductor layer (21) (the channel 21 under 37 is in the semiconductor layer 21, see fig. 21); a first gate electrode (37) above the first channel layer (21 under 37) (see fig. 21), wherein the first gate electrode (37) is outside of the semiconductor layer (21) (see fig. 21); and a first capacitor layer (28) below a first pinned layer (p-type) and accumulates a specific amount of the charge (fig. 21, paragraph 216) and the first capacitor layer (28) is in the semiconductor layer (21), the first capacitor layer (28) is of a second conductivity type (n-type) different from the first conductivity type (p-type) (see fig. 21) and the first capacitor layer (28) is capacitively coupled to the semiconductor layer (21) with a second capacitance (any junction between a p type and an n type layer has a junction capacitance, fig. 21 there is a junction between capacitor layer 28 and semiconductor layer 21, therefor there is a junction capacitance), and the second capacitance corresponds to a capacitance between the first capacitor layer (28) and the semiconductor layer (21) (any junction between a p type and an n type layer has a junction capacitance, fig. 21 there is a junction between capacitor layer 28 and semiconductor layer 21, therefore there is a junction capacitance), but does not specifically teach the first capacitor layer is below the first channel layer and accumulates the specific amount of the charge and the first capacitor layer is capacitively coupled to the first channel layer with a first capacitance the first capacitance corresponds to a capacitance between the first capacitor layer and the first channel layer. Machida teaches a first channel of a first conductivity type (p-type in MEM 223) on a first side of a photoelectric conversion section (221) (see fig. 13), wherein the first channel layer (p-type in MEM 223) is below a first surface of a semiconductor layer (top part of 232 where gate 222 is located thereon) (see fig. 13, the p-type in MEM 223 is below the first surface of the semiconductor layer 232), and the first channel layer (p-type in MEM 223) is in the semiconductor layer (232) (see fig. 13); a first gate electrode (222) above the first channel layer (p-type layer in MEM 223), wherein the first gate electrode (222) is outside the semiconductor layer (232) (see fig. 13), and a first capacitor layer (n-type layer in MEM 223) below the first channel layer (p-type) and accumulates a specific amount of the charge (paragraphs 167, fig. 13), the first capacitor layer (n-type in ) is in the semiconductor layer (232), the first capacitor layer (n-type in 223) is of a second conductivity type (n-type) different from the first conductivity type (p-type) (see fig. 13), the first capacitor layer (n-type in 223) is capacitively coupled to the first channel layer (p-type in 223) with a first capacitance, the first capacitance corresponds to a capacitance between the first capacitor layer (n-type in 223) and the first channel layer (p-type in 223) (any junction between a p type and an n type layer has a junction capacitance, fig. 13 there is a junction between capacitor layer n-type in 223 and the first channel layer a p-type in 223, therefore there is a junction capacitance), the first capacitor layer (n-type in 223) is capacitively coupled to the semiconductor layer (p-type of 232) with a second capacitance (any junction between a p type and an n type layer has a junction capacitance, fig. 13 there is a junction between capacitor layer n-type in 223 and the semiconductor layer 232 a p-type, therefore there is a junction capacitance), and the second capacitance corresponds to a capacitance between the first capacitor layer (n-type in 223) and the semiconductor layer (p-type 232) (any junction between a p type and an n type layer has a junction capacitance, fig. 13 there is a junction between capacitor layer n-type in 223 and the semiconductor layer 232 a p-type, therefore there is a junction capacitance). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first capacitor layer below the first channel layer of Kawahito similar to Machida in order to increase the well size when potential is applied to the gate providing for reduced dark current and higher quality image formation (Machida, paragraph 165-169).
Re claim 2: Kawahito as modified by Machida teaches the sensor, wherein each of the plurality of pixels further includes: a second channel layer (Kawahito, 21 under 38, Machida, p-type layer in MEM 223) of the first conductivity type (Kawahito, p-type, Machida, p-type) on a second side of the photoelectric conversion section (Kawahito, PD, see fig. 21), wherein the second channel layer (Kawahito, 21 under 38, Machida, p-type layer in MEM 223) is in the semiconductor layer (Kawahito, the channel 21 under 37 is in the semiconductor layer 21, see fig. 21, Machida, see fig. 13, p-type of 223 is in semiconductor layer 232); a second gate electrode (Kawahito, 38, Machida, 222) above the second channel layer (Kawahito, fig. 21, Machida, fig. 13), wherein the second gate electrode (Kawahito, 38, Machida, 222) is outside of the semiconductor layer (Kawahito, 38 is outside 21, see fig. 21, Machida, 222 is outside 232, see fig. 13); and a second capacitor layer (Kawahito, 18, Machida, n-type in MEM 223) of the second conductivity type (Kawahito, n-type, Machida, n-type) below the second channel layer (Machida, p-type in MEM 223), wherein the second capacitor layer (Kawahito, 18, Machida, n-type in MEM 223) is in the semiconductor layer (Kawahito, 18 is in 21, see fig. 21, Machida, n-type of 223 is in 232, see fig. 13) and the second capacitor layer (Kawahito, 18, Machida, n-type in MEM 223) is configured to accumulate the specific amount of the charge (Kawahito, paragraphs 216, fig. 21, Machida, paragraph 167, fig. 13).
Claim(s) 3, 4 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) as modified by Machida (US 20140084138) as applied to claim 2 above, and further in view of Ma et al. (US 20180090537).
Re claim 3: Kawahito as modified by Machida teaches the each of the plurality of pixels includes a first transistor (Kawahito, 37, Machida, 222) that includes the first channel layer (Kawahito, 21 under 37, Machida, p-type layer in MEM 223) and the first gate electrode (Kawahito, 37, Machida, 222) and is electrically connected to a first signal line (Kawahito, B), and a threshold value of the first transistor is modulated by the first gate electrode (Kawahito, 37, fig. 21, Machida, 222, fig. 13), but does not specifically teach the first transistor is an amplification transistor and modulation of the threshold value of the first amplification transistor is based on the specific amount of the charge accumulated in the first capacitor layer. Ma teaches modulation of a threshold value of a first amplification transistor (20/16/18/26/24) is based on a specific amount of charge accumulated in a first capacitor layer (18) (paragraph 36, fig. 1). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first gate and the first channel of Kawahito as modified by Machida be an amplification transistor modulated by the charge in the capacitor similar to Ma in order to reduce the amount of circuitry while improving charge amplification and conversion providing for more compact efficient design for the sensor.
Re claim 4: Kawahito as modified by Machida and Ma teaches the sensor, wherein the each of the plurality of pixels further includes a second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38, Machida, 222), the second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38, Machida, 222) includes the second gate electrode (Ma, see fig. 1, Machida, see fig. 13, Kawahito, see fig. 21), the second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38, Machida, 222) is electrically connected to a second signal line (Kawahito, B), and modulation of a threshold value of the second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38, Machida, 222) is based on the specific amount of the charge accumulated in the second capacitor layer (Ma, 18, paragraph 36, fig. 1).
Re claim 10: Kawahito as modified by Machida and Ma teaches the sensor, wherein each of the first capacitor layer (Kawahito, 18) and the first amplification transistor (Kawahito, 37/28, Ma, 20/16/18/26/24) is on the first side of the photoelectric conversion section (Kawahito, PD, see fig. 21), in a plan view as viewed from an incident direction of the light to the semiconductor layer (Kawahito, 21, see fig. 21 and 22), and each of the second capacitor layer (Kawahito, 28, Machida, n-type in MEM 223) and the second amplification transistor (Kawahito, 38/18, Ma, 20/16/18/26/24) is on the second side of the photoelectric conversion section (Kawahito, PD), in the plan view (Kawahito, see fig. 21 and 22).
Claim(s) 5, 6 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) as modified by Machida (US 20140084138) as applied to claim 1 above, and further in view of Kawahito et al. (US 20090114919, hereinafter Kawahito ‘919).
Re claim 5: Kawahito as modified by Machida teaches the sensor, wherein the each of the plurality of pixels further includes the substrate (Kawahito, 21) connected to a power supply (Kawahito, VDD, see fig. 21), but does not specifically teach a first power supply diffusion layer of a second conductivity type, the first power supply diffusion layer is on the first side of the photoelectric conversion section. Kawahito ‘919 teaches wherein each of a plurality of pixels further includes a first power supply diffusion layer (24a) of the second conductivity type (n-type), the first power supply diffusion layer (24a) is on a first side of a photoelectric conversion section (22) (see fig. 3), and the first power supply diffusion layer (24a) is connected to a power supply (VDD) (see fig. 3). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a first power supply diffusion layer connected to the power supply of Kawahito similar to Kawahito ‘919 in order to have a region for connecting the power supply to the circuitry for resetting the circuit to a base power for higher quality image formation.
Re claim 6: Kawahito as modified by Machida and Kawahito ‘919 teaches the sensor, wherein the each of the plurality of pixels further includes a second power supply diffusion layer (Kawahito ‘919, 24b) of the second conductivity type (Kawahito ‘919, n-type), the second power supply diffusion layer (Kawahito ‘919. 24b) on a second side of the photoelectric conversion section (Kawahito ‘919, 22, see fig. 3), and the second power supply diffusion layer (Kawahito ‘919. 24b) is connected to the power supply (Kawahito ‘919, Vdd, fig. 3).
Re claim 19: Kawahito as modified by Machida teaches the sensor, wherein the plurality of pixels includes: an imaging pixel configured to acquire an image of a target (Kawahito, paragraph 216, fig. 21), but does not specifically teach includes a distance measuring pixel configured to measure a distance to the target based on the image of the target. Kawahito ‘919 teaches includes a distance measuring pixel that measures a distance to a target by an imaging pixel that acquires an image of the target (paragraph 72-81, abstract, fig. 1-6). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to include measuring distance similar to Kawahito ‘919 with the device of Kawahito as modified by Machida in order to form a two dimensional image corresponding to the distance information providing for a versatile design.
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) as modified by Machida (US 20140084138) as applied to claim 2 above, and further in view of Cazaux et al. (US 20180167606).
Re claim 11: Kawahito as modified by Machida teaches the sensor, wherein the light is incident on the first surface of the semiconductor layer (Kawahito, see fig. 21, Machida, fig. 13), but does not specifically teach the light is incident on a second surface of the semiconductor layer, the second surface of the semiconductor layer is opposite to the first surface of the semiconductor layer. Cazaux teaches light is incident on a second surface (filters located 662) of a semiconductor layer (p substrate), the second surface of the semiconductor layer is opposite to a first surface of the semiconductor layer (on side of 656 further away from filter 662, see fig. 6, light passes through filters 662 to first side on opposite side of filters 662). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the light pass through second side for back-side illumination to allow for a smaller thinner device providing for more compact design.
Re claim 12: Kawahito as modified by Machida and Cazaux teaches the sensor, further comprising a light shielding film (Cazaux, 664) is on a region that excludes the photoelectric conversion section (Cazaux, see fig. 6, 664 is between photoelectric conversion sections 650/652, pinned photodiode), and the light shielding film (Cazaux, 664) overlaps the first capacitor layer and the second capacitor layer (Cazaux, MEMs), in a plan view as viewed from an incident direction of the light to the semiconductor layer (Cazaux, p substrate, see fig. 6).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) as modified by Machida (US 20140084138) and Cazaux et al. (US 20180167606) as applied to claim 11 above, and further in view of Cheng et al. (US 20190148431).
Re claim 13: Kawahito as modified by Machida and Cazaux teaches the sensor, further comprising a light shielding film (Cazaux, 664) that is provided so as to overlap the first and second capacitor layers (Cazaux, MEMs) and does not overlap the photoelectric conversion section (Cazaux, P8, PZ, P4) in a plan view as viewed from an incident direction of light to the semiconductor layer (Cazaux, p substrate, see fig. 6), but does not specifically teach further comprising a reflecting portion that is provided so as to overlap the first and second capacitor layers in a plan view as viewed from an incident direction of light to the semiconductor layer and reflects light to the photoelectric conversion section. Cheng teaches further comprising a reflecting portion (222) overlaps a first and second circuit layers (242/240/232/211/210), in a plan view as viewed from an incident direction of light to a semiconductor layer (202/204), and the reflecting portion is configured to reflect light to a photoelectric conversion section (204, paragraph 30, fig. 2 and 3). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to further include a reflecting portion with the shielding layer covering the capacitor layers of Kawahito as modified by Machida and Cazaux similar to Cheng in order to ensure light is guided to the photosensor reducing cross talk and noise providing for higher quality image formation.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawahito (US 20100187401) as modified by Machida (US 20140084138) and Ma et al. (US 20180090537) as applied to claim 4 above, and further in view of Kawahito et al. (US 20090114919, hereinafter Kawahito ‘919).
Re claim 20: Kawahito as modified by Machida and Ma teaches the sensor, wherein the each of the plurality of pixels further includes the first and second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38 and 37, Machida, 222) that includes the first and the second channel layer and the second gate electrode (Ma, see fig. 1, Machida, see fig. 13, Kawahito, see fig. 21) and is electrically connected to the first and the second signal line (Kawahito, B), and the threshold value of the first and the second amplification transistor (Ma, 20/16/18/26/24, paragraph 36, fig. 1, Kawahito, 38, Machida, 222) is modulated by the amount of the charge accumulated in the second capacitor layer (Ma, 18, paragraph 36, fig. 1), but does not specifically teach the pixel transmits a signal voltage to each of the first signal line and the second signal line, wherein the signal voltage corresponds to a signal state associated with the specific amount of the charge accumulated in each of the first capacitor layer and second capacitor layer; and transmit a reset voltage based on the transmission of the signal voltage, wherein the reset state of each of the first capacitor layer and second capacitor layer, the first capacitor layer is further configure to discharge the specific amount of the charge to the first signal line, the second capacitor layer is further configured to discharge the specific amount of the charge to the second signal line, and each of the signal voltage and the reset voltage is associated with a correlated double sampling process. Kawahito ‘919 teaches each pixel of a plurality of pixels transmit a signal voltage to each of a first signal line (B1) and a second signal line (B2), wherein the signal voltage corresponds to a signal state associated with a specific amount of charge accumulated in a first capacitor layer (27b) and second capacitor layer (27a) (see fig. 2 and 3), and transmits a reset voltage based on the transmission of the signal voltage, wherein the reset voltage corresponds to a reset state of each of the first capacitor layer (27b) and second capacitor layer (27a), the first capacitor layer (27b) is further configured to discharge the specific amount of the charge to the first signal line (B1), the second capacitor layer (27a) is further configured to discharge the specific amount of charge the second signal lines (B2) (see fig. 2 and 3), and each of the signal voltage and the reset voltage is associated with a correlated double sampling process (paragraph 78). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to do correlated double sampling on the two capacitor layers of Kawahito as modified by Machida and Ma similar to Kawahito ‘919 in order to subtract the noise from the output signal providing for higher quality image formation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER D BENNETT/Examiner, Art Unit 2878