DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for domestic benefit under 35 U.S.C. 365(c) with PCT/CN2020/130801.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on April 13, 2023 and June 9, 2025 were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I Claims 1-4, 10-13 in the reply filed on January 16, 2026 is acknowledged. The traversal is on the ground(s) that Hori fails to teach the manufacturing method comprising at least one of: planarizing a first contact surface between the first semiconductor layer and the first reflector, or planarizing a second contact surface between the second semiconductor layer and the second reflector. Specifically applicant argues that Hori teaches the first contact surface is not between the first semiconductor layer and the first reflector or the second contact surface is between the second semiconductor layer and the second reflector because paragraph 0158 of Hori states “the surfaces of the buried layer and the lower clad layer are smoothed typically by CMP (chemical mechanical polishing) and subsequently the lower clad layer is made to grow thereon once again” This is not found persuasive because the contact surface in Hori is found between the first semiconductor layer and the first reflector. (see annotated Fig. 8A below). In addition applicant argues that the amendment is not taught in Masui nor Hori. However Hori teaches each cavity length at each position of a cavity resonator between the first reflector and the second reflector is the same. (Paragraphs 0147 & 0150 teach the thickness of the first and second semiconductor layers to be 540 nm which makes the position of the cavity resonator the same between the first and second reflector.)
The requirement is still deemed proper and is therefore made FINAL.
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Claims 5-9, 14 are withdrawn by applicant as being drawn to a nonelected Group, there being no allowable generic or linking claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 10, 12 are rejected as being unpatentable over 35 U.S.C. 103 over Han et al. US 20170237234 in view of Masui et al. US 20110007769 and Zhang et al. CN 103325894.
Regarding Claim 1, Han teaches A manufacturing method of a vertical cavity surface emitting laser, wherein the vertical cavity surface emitting laser (Fig. 1) comprises a first reflector (Fig. 1, 110 Paragraph 0040 “a first bottom-side reflector 110”), a first semiconductor layer (Fig. 1, 120 Paragraph 0040 “a second semiconductor layer 120 of a second conductivity type (e.g., n-type).”), an active layer (Fig. 1, 130 Paragraph 0040 “VCSEL may include an active region 130”), a second semiconductor layer (Fig. 1, 140 Paragraph 0040 “a first semiconductor layer 140 of a first conductivity type (e.g., p-type)”), and a second reflector (Fig. 1, 150 Paragraph 0040 “a second top-side reflector 150.”) sequentially stacked (Fig. 1 shows the layers sequentially stacked);
wherein a conductivity type of the first semiconductor layer is opposite to a conductivity type of the second semiconductor layer (Paragraph 0040 “a first semiconductor layer 140 of a first conductivity type (e.g., p-type) and a second semiconductor layer 120 of a second conductivity type (e.g., n-type).”);
wherein each cavity length at each position of a cavity resonator between the first reflector and the second reflector is the same. (Paragraph 0066 “The cavity region may have a length L, which may be between approximately one wavelength and approximately five wavelengths of the VCSEL's emission wavelength (as modified by the refractive index of the cavity region). The length L approximately determines a cavity length for the VCSEL. When the cavity length L is on the order of a few wavelengths, the VCSEL may comprise a microcavity that may support one or a few longitudinal optical modes. In some implementations, the cavity length L may be longer than five wavelengths.” Fig. 1 shows that the cavity length at each position of the cavity resonator is the same. See annotated Fig. 1 below)
Han does not teach an oxide layer where the oxide layer comprises a light transmitting region and a light shielding region, and the light shielding region surrounds the light transmitting region; and the manufacturing method comprises at least one of:
planarizing a first contact surface between the first semiconductor layer and the first reflector, or
planarizing a second contact surface between the second semiconductor layer and the second reflector.
However,
Masui teaches an oxide layer (Fig. 2, 18), where the oxide layer comprises a light transmitting region (Fig. 2, 18A) and a light shielding region (Fig. 2 18B), and the light shielding region surrounds the light transmitting region ( Paragraph 0046 “The current injection region 18A is, for example, composed of p-type Alx9Ga1-xAs (0<x9≤1). The current constricting region 18B contains, for example, aluminum oxide (Al2O3)” AlGaAs will transmit light and Al2O3 blocks light see Paragraph 0049 of Masui. Fig. 2 shows the light shielding region surrounds the light transmitting region) and the oxide layer is between a second semiconductor layer and the second reflector (Fig. 1 shows 18 is between 14 and the top half of 15 Paragraph 0042 “The upper spacer layer 14 is, for example, composed of p-type Alx5Ga1-x5As” Paragraph 0039 “The upper DBR layer 15”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified laser as taught by Han by adding the oxide layer as disclosed by Masui. One of ordinary skill in the art would have been motivated to make this modification in order to control the flow of current (Masui Paragraph 0044 “current narrowing layer.”)
Han in view of Masui does not teach planarizing a first contact surface between the first semiconductor layer and the first reflector, or planarizing a second contact surface between the second semiconductor layer and the second reflector.
However,
Zhang teaches planarizing a first contact surface between the first semiconductor layer and the first reflector, or
planarizing a second contact surface between the second semiconductor layer and the second reflector. (Paragraphs 0025-0027 “on the epitaxial wafer by electron beam evaporation device for preparing 250nm thick p type current extension layer of ITO 13, growth of the ITO surface of the AFM scan as shown in FIG. 7, can know the surface RMS roughness of ITO is about 8nm; 3) using ICP etching technology to etch the surface to less than 10nm/min of the etching rate of the ITO thinned to less than I00nm. 4) using polishing technology after processing flat etching the ITO, the ITO surface RMS after polishing as shown in FIG. 8, after the ICP and polishing technology, surface RMS of ITO is reduced to; 5) through corrosion of the ITO with diameter shorter than 20 microns round; 6) the structure using inductively coupled plasma etching technology apparatuses, forming n-type table surface;” ITO is a semiconductor layer that is planarized and forms a contact surface between the second semiconductor layer and the second reflector)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of manufacturing as taught by Han by adding the planarizing step as disclosed by Zhang. One of ordinary skill in the art would have been motivated to make this modification in order to form a flat surface. (Zhang Paragraph 0029 “forming a n-type table surface”)
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Regarding Claim 2, Han in combination with Masui and Zhang teaches sequentially forming the first reflector, the first semiconductor layer, the active layer, and a second semiconductor material layer on a substrate (Han Fig. 1, 105 Paragraph 0007 “the laser cavity 170 and emitting laser beam 175 are oriented perpendicular to the planar surface of the substrate 105 on which the VCSEL is fabricated, and the laser beam travels in a direction of the p-n junction.”); and
planarizing a first surface of the second semiconductor material layer away from the substrate to obtain the second semiconductor layer, wherein the first surface after planarization becomes the second contact surface. (Zhang Paragraphs 0025-0027 “on the epitaxial wafer by electron beam evaporation device for preparing 250nm thick p type current extension layer of ITO 13, growth of the ITO surface of the AFM scan as shown in FIG. 7, can know the surface RMS roughness of ITO is about 8nm; 3) using ICP etching technology to etch the surface to less than 10nm/min of the etching rate of the ITO thinned to less than I00nm. 4) using polishing technology after processing flat etching the ITO, the ITO surface RMS after polishing as shown in FIG. 8, after the ICP and polishing technology, surface RMS of ITO is reduced to; 5) through corrosion of the ITO with diameter shorter than 20 microns round; 6) the structure using inductively coupled plasma etching technology apparatuses, forming n-type table surface;” Figs. 1-3 See Claim 1 for rational)
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Regarding Claim 3, Han in combination with Masui and Zhang teaches before sequentially forming the first reflector, the first semiconductor layer, the active layer, and the second semiconductor material layer on the substrate, the method further comprises: sequentially forming a nucleation layer (Han Fig. 5A, 510) and a buffer layer (Han Fig. 5A, 520) on the substrate. (Han Paragraphs 0052-0054)
Regarding Claim 4, Han in combination with Masui and Zhang teaches after planarizing the first surface of the second semiconductor material layer away from the substrate to obtain the second semiconductor material layer, the method further comprises: sequentially forming the oxide layer and the second reflector on the second semiconductor layer. (Masui Fig. 5A-5B shows sequentially forming the oxide layer and the second reflector on the semiconductor layer See Claim 1 for rational.)
Regarding Claim 10, Han in combination with Masui and Zhang teaches the first semiconductor layer is an N-type semiconductor layer (Han Fig. 1 shows 120 is a n type semiconductor); the second semiconductor layer is a P-type semiconductor layer (Han Fig. 1 shows 140 is a p type semiconductor); and the active layer comprises a multiple quantum well structure. (Paragraph 0040 “The active region 130 may comprise multiple-quantum-well (MQW) layers or a superlattice (SL).”)
Regarding Claim 12, Han in combination with Masui and Zhang teaches a material of the first semiconductor layer comprises a group III-V compound, and a material of the second semiconductor layer comprises a group III-V compound. (Paragraph 0065 “According to some embodiments, fabrication of the cavity region may comprise depositing an n-type gallium-nitride layer 560, multiple quantum wells 565 or superlattice (SL) for the active region, and a p-type gallium-nitride layer 570 to form a structure as depicted in FIG. 5F.”)
Claim 11 is rejected as being unpatentable over 35 U.S.C. 103 over Han, Masui and Zhang in view of Doan et al US 20140087499.
Regarding Claim 11, Han in combination with Masui and Zhang does not teach the multiple quantum well structure is a periodic structure in which GaN and AlGaN are alternately arranged, or a periodic structure in which GaN and AlInGaN are alternately arranged.
However,
Doan teaches the multiple quantum well structure is a periodic structure in which GaN and AlGaN are alternately arranged, or a periodic structure in which GaN and AlInGaN are alternately arranged. (Paragraph 0043 “he MQW active layer 44 can be an InGaN/GaN (or AlGaN/GaN or AlInGaN) MQW active layer.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the multiple quantum well structure as taught by Han by having it bee made of a periodic structure where AlGaN and GaN are alternately arranged as disclosed by Doan. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) MPEP 2144.07. The reference has demonstrated the AlGaN/GaN multiple quantum well structure is sutible to produce laser light in the violet or blue range (Doan Paragraph 0043 “The produced light can have a wavelength between 250 nm to 600 nm.”)
Claim 13 is rejected as being unpatentable over 35 U.S.C. 103 over Han, Masui and Zhang in view of Lee US 20210075193.
Regarding Claim 13, Han teaches the vertical cavity surface emitting laser further a first electrode, and a second electrode, (Paragraph 0040 “Electrical contact to the VCSEL 100 may be made through the substrate 105 on the bottom side and through a deposited conductive contact 160 on the top side of the device” The bottom side electrical contact is the first electrode and 160 is the second electrode)
Han does not teach the vertical cavity surface emitting laser further comprises a third insulating material layer, a fourth insulating material layer wherein the third insulating material layer is located on a side of the first reflector away from the second reflector, and the first electrode is located on a side of the third insulating material layer away from the first reflector; the fourth insulating material layer is located on a side of the second reflector away from the first reflector, and the second electrode is located on the side of the fourth insulating material layer away from the second reflector; and the second electrode contacts the second reflector through a through hole in the fourth insulating material layer.
However,
Lee teaches the vertical cavity surface emitting laser further comprises a third insulating material layer (Fig. 6a, 210 Paragraph 0263 “The substrate 210 may be formed of a material suitable for growth of semiconductor materials or a carrier wafer, and may be formed of a material having excellent thermal conductivity, and may include a conductive substrate or an insulating substrate”), a fourth insulating material layer (Fig. 6a, 270 Paragraph 0258 “The passivation layer 270 may be made of an insulating material, for example, a nitride or an oxide.”) wherein the third insulating material layer is located on a side of the first reflector away from the second reflector (Fig. 6a shows 210 is located on the bottom side of reflector 220), and the first electrode is located on a side of the third insulating material layer away from the first reflector (Fig. 6a shows electrode 215 located on the bottom side of 210); the fourth insulating material layer is located on a side of the second reflector away from the first reflector (Fig. 6a shows 270 on the top side of reflector 250), and the second electrode is located on the side of the fourth insulating material layer away from the second reflector (Fig. 6a shows the second electrode 280 on top of the fourth insulating material 270); and the second electrode contacts the second reflector through a through hole in the fourth insulating material layer. (Fig. 6a shows the second electrode touches the second reflector in a hole in 270 at the point 282 contacts 250)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the vertical cavity surface emitting laser as taught by Han by adding the third insulating material as disclosed by Lee. One of ordinary skill in the art would have been motivated to make this modification in order to control the thermal conductivity of the vertical surface emitting laser device. (Lee Paragraph 0263 “he substrate 210 may be formed of a material suitable for growth of semiconductor materials or a carrier wafer, and may be formed of a material having excellent thermal conductivity, and may include a conductive substrate or an insulating substrate.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the vertical cavity surface emitting laser as taught by Han by adding the fourth insulating material as disclosed by Lee. One of ordinary skill in the art would have been motivated to make this modification in order to protect and insulate the vertical surface emitting laser device. (Lee Paragraph 0258 “The passivation layer 270 is also disposed on a side surface of the surface-emitting laser device 201 separated by device units, and protects and insulates the surface-emitting laser device 201.”)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ueki US 20040184498 teaches a similar structure to Fig. 17 in the application.
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/STEPHEN SUTTON KOTTER/Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828