CTNF 18/249,098 CTNF 101544 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 6-7, and 9 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Kwon et al. (US 2020/0058688 A1) . Regarding Claim 1, Kwon discloses sensor device ([0026] an image processing apparatus 200 may include an image sensor 110) , comprising: a semiconductor substrate ([0040] The image sensor 100 may include a substrate 1) ; and a wiring layer part disposed on the semiconductor substrate having a plurality of wiring layers ([0044] First wiring lines 19 may be disposed on the first interlayer dielectric layer 15… [0045] The first interlayer dielectric layer 15 may be provided thereon with a second interlayer dielectric layer 21 covering the first wiring lines 19… [0053] Third wiring lines 39 may be disposed on the third interlayer dielectric layer 35) , wherein: the semiconductor substrate and the wiring layer part constitute a laminated structure in which a pixel is disposed ([0040] As shown in FIG. 4, the second deep device isolation layer 3 b may be spaced apart from the first deep device isolation layer 3 a . In one pixel UP, the second deep device isolation layer 3 b may divide the substrate 1 into a first region R1 and a second region R2. The first region R1 may be a light-receiving section. The second region R2 may be a circuit section. The first and second device isolation layers 3 a and 3 b may penetrate the substrate 1) , the pixel including: a photoelectric conversion element that performs photoelectric conversion ([0041] A first impurity region 5 may be disposed in the substrate 1 of the first region R1… The first impurity region 5 and the substrate 1 therearound may constitute a PN junction to provide a photoelectric conversion region) ; a first charge holding part and a second charge holding part that hold charges accumulated in the photoelectric conversion element ([0048] The first bottom electrode 25 b 1, the first conductive pillars 27 b 1, the first dielectric layer 29 b 1, and a portion of the top electrode 31 u may constitute a first capacitor C1. The second bottom electrode 25 b 2, the second conductive pillars 27 b 2, the second dielectric layer 29 b 2, and a portion of the top electrode 31 u may constitute a second capacitor C2) ; a first transfer transistor that transfers the charges to the first charge holding part ([0034] For example, each unit pixel of the image sensor may include a photoelectric conversion region PD, a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a pre- charge transistor PC, a sampling transistor SAM, a calibration transistor Cal, a second source follower transistor SF2, a selection transistor SEL, a first capacitor C1, and a second capacitor C2) ; and a second transfer transistor that transfers the charges to the second charge holding part ([0079] four transfer transistors TX1, TX2, TX3, and TX4 may share one floating diffusion region FD. In this case, four first regions R1 may be disposed adjacent to each other. The four transfer transistors TX1, TX2, TX3, and TX4 may be turned on in sequence. For example, when the first transfer transistor TX1 is turned on, charges accumulated in a first photoelectric conversion region PD1 may be sensed by the operation discussed with reference to FIG. 2. The same operation may be sequentially performed on the second, third, and fourth transfer transistors TX2, TX3, and TX4. Examiner Note: The operation discussed with reference to Fig. 2 is provided above in reference to Paragraph 34 ) ; and a shield part ([0045] The dummy bottom electrode 25 s may have a closed loop shape that surrounds the first and second bottom electrodes 25 b 1 and 25 b 2… [0049] When viewed in plan view, the dummy dielectric layer 29 s and the dummy top electrode 31 s may have a closed loop shape that surrounds the top electrode 31 u . The dummy bottom electrode 25 s , the dummy conductive pillars 27 s , the dummy dielectric layer 29 s , and the dummy top electrode 31 s may constitute a shield structure 33 s ) surrounding a gate wiring line is formed for the gate wiring line of each of the first transfer transistor and the second transfer transistor ([0052] The image sensor 100 includes the shield structure 33 s that surrounds the first and second capacitors C1 and C2. Thus, a parasitic capacitance may be prevented or minimized between conductive lines (e.g., the third edge contact plug 37 p ) adjacent to the first and second capacitors C1 and C2, which may result in a reduction in coupling noise. The image sensor 100 may thus produce a sharp image) extending in a thickness direction in the wiring layer part (Fig. 4 Examiner Note: Notice that element 33s in Fig. 4 (reproduced below) is shown in a thickness direction in the wiring layer part ) . PNG media_image1.png 729 672 media_image1.png Greyscale Regarding Claim 2, Kwon discloses that the shield part is disposed across a plurality of the wiring layers ([0045] The second interlayer dielectric layer 21 may be provided thereon with a first bottom electrode 25 b 1, a second bottom electrode 25 b 2, a dummy bottom electrode 25 s … [0075] The dummy bottom electrode 25 s and a shield pattern 38 s on the dummy bottom electrode 25 s may constitute the shield structure 330 s . The shield pattern 38 s may penetrate the third interlayer dielectric layer 35, connecting the dummy bottom electrode 25 s to one of the third wiring lines 39… [0045] The first interlayer dielectric layer 15 may be provided thereon with a second interlayer dielectric layer 21 covering the first wiring lines 19… [0053] Third wiring lines 39 may be disposed on the third interlayer dielectric layer 35) . Regarding Claim 3, Kwon discloses that the gate wiring line includes a wiring line extending in an in-plane direction ([0044] First wiring lines 19 may be disposed on the first interlayer dielectric layer 15. The first interlayer dielectric layer 15 may be provided therein with first contact plugs 17 electrically connected to the first wiring lines 19. Some of the first contact plugs 17 may contact the first, second, and third gate electrodes 9 a , 9 b , and 9 c . Examiner Note: Fig. 5 (reproduced below) shows wiring lines 19 running horizontally across the dielectric layer and you can see plug 17 dropping down from horizontal wiring line 19 to hit gate 9b, therefore the horizontal wiring of 19 is included in the gate wiring line ) on an inner side of the shield part ([0049] the dummy dielectric layer 29 s and the dummy top electrode 31 s may have a closed loop shape that surrounds the top electrode 31 u . The dummy bottom electrode 25 s , the dummy conductive pillars 27 s , the dummy dielectric layer 29 s , and the dummy top electrode 31 s may constitute a shield structure 33 s … [0066] The mold layer 26 may include a plurality of first pillar holes 26 b 1 that expose a top surface of the first bottom electrode 25 b 1, a plurality of second pillar holes 26 b 2 that expose a top surface of the second bottom electrode 25 b 2, and a plurality of dummy pillar holes 26 s that expose a top surface of the dummy bottom electrode 25 s . The first dielectric layer 29 b 1, the second dielectric layer 29 b 2, and the dummy dielectric layer 29 s may extend respectively into the first pillar holes 26 b 1, the second pillar holes 26 b 2, and the dummy pillar holes 26 s , and thus have contact respectively with the first bottom electrode 25 b 1, the second bottom electrode 25 b 2, and the dummy bottom electrode 25 s Examiner Note: Fig. 5 (reproduced below) shows the shield structure 33s is composed of vertical dummy contact plugs (26s) and dummy conductive pillars (27s).Because these vertical elements are connected to electrodes (25s, 31s) that form a closed loop around the internal pixel stack, they define a lateral perimeter. Since the horizontal gate wiring (19) and associated plugs (17) are situated between these vertical shield elements in the cross section of Fig. 5, the gate wiring is disposed on the “inner side” of the shield part ) . PNG media_image2.png 584 688 media_image2.png Greyscale Regarding Claim 4, Kwon discloses that the gate wiring line includes a through via penetrating the plurality of the wiring layers ([0044]-[0045] The first interlayer dielectric layer 15 may be provided therein with first contact plugs 17 electrically connected to the first wiring lines 19. Some of the first contact plugs 17 may contact the first, second, and third gate electrodes 9 a , 9 b , and 9 c … The second interlayer dielectric layer 21 may be provided therein with second contact plugs 23 b and 23 that penetrate the second interlayer dielectric layer 21 and have electrical connection with the first wiring lines 19… [0054] Third wiring lines 39 may be disposed on the third interlayer dielectric layer 35. The third interlayer dielectric layer 35 may be provided thereon with a fourth interlayer dielectric layer 41 covering the third wiring lines 39. Fourth contact plugs 43 may penetrate the fourth interlayer dielectric layer 41 and have electrical connection with the third wiring lines 39. Fourth wiring lines 45 may be disposed on the fourth interlayer dielectric layer 41. The fourth wiring lines 45 may be covered with a fifth interlayer dielectric layer 47. The first, second, third, fourth, and fifth interlayer dielectric layers 15, 21, 35, 41, and 47) Examiner Note: As shown in Fig 5, elements 17 and 23b function together as a stacked via assembly that physically penetrates the plurality of wiring layers (shown as 15 and 21 ) . Regarding Claim 6, Kwon discloses that the shield part has an annular cross-sectional shape in an in-plane direction ([0045] The dummy bottom electrode 25 s may have a closed loop shape that surrounds the first and second bottom electrodes 25 b 1 and 25 b 2... [0049] the dummy dielectric layer 29 s and the dummy top electrode 31 s may have a closed loop shape that surrounds the top electrode 31 u ) . Regarding Claim 7, The sensor device according to claim 1, wherein the shield part includes an insulating material ([0047] The first, second, and dummy dielectric layers 291 b 1, 29 b 2, and 29 s may have one of single-layered and multi-layered structures of the same material, for example, silicon oxide, tungsten oxide, copper oxide, aluminum oxide, titanium oxide, tantalum oxide, zirconium oxide, lanthanum oxide, or a combination thereof) that is different from an interlayer insulating material in the wiring layer part ([0054] The first, second, third, fourth, and fifth interlayer dielectric layers 15, 21, 35, 41, and 47 may include, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous dielectric layer) . Regarding Claim 9, Kwon discloses that the shield part is formed as a cavity part ([0060] or more of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The mold layer 26 may be patterned to form a plurality… of dummy pillar holes 26 s that expose a top surface of the dummy bottom electrode 25 s … A conductive layer may be stacked to fill… dummy pillar holes… 26s… and then flat etched to faun… dummy conductive pillars 27s… in the… dummy pillar holes 26s) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2020/0058688 A1) in view of Mase et al. (US 2023/0026004 A1) . Regarding Claim 5, Kwon is not relied upon as teaching that an inter-pixel wiring line being a connection destination of the gate wiring line is formed in a farthest wiring layer which is the wiring layer farthest from the semiconductor substrate in the wiring layer part, and the shield part extends from an adjacent wiring layer of the farthest wiring layer in the wiring layer part toward a side of the semiconductor substrate. However, Mase teaches that an inter-pixel wiring line being a connection destination of the gate wiring line ([0064] The wiring layer 60 is electrically connected to each pixel 11 a and the CMOS read circuit unit 12) is formed in a farthest wiring layer which is the wiring layer farthest from the semiconductor substrate in the wiring layer part ([0064] The wiring layer 60 is provided on the first surface 20 a of the semiconductor layer 20 so as to cover the electrode layer 40 Examiner Note: Fig. 3, reproduced below, shows layer 60 (the wiring layer) being the furthest away from layer 20 (the semiconductor substrate) ) , and the shield part extends from an adjacent wiring layer of the farthest wiring layer in the wiring layer part toward a side of the semiconductor substrate ([0065] A trench 29 is formed in the semiconductor layer 20 so as to separate the pixels 11 a from each other. The trench 29 is formed on the first surface 20 a of the semiconductor layer 20. Examiner Note: Fig. 3, reproduced below, shows element 29 extending from layer 40 (an adjacent wiring layer) towards a side of the semiconductor substrate ) . PNG media_image3.png 569 809 media_image3.png Greyscale Kwon and Mase are considered to be analogous to the claimed invention because they are both in the same field of image sensors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the inter-pixel shielding structure of Kwon to include the top-down wiring and trench geometry of Mase with a reasonable expectation of success. This modification would have been motivated by the desire to improve light receiving sensitivity and suppress crosstalk between adjacent pixels. By integrating Mase’s teaching of routing inter-pixel gate signals in a farthest wiring layer with a shield from an adjacent layer into Kwon’s global shutter sensor, the system can ensure that electrical isolation begins at the primary signal distribution point. A person of ordinary skill in the art would recognize that using Mase’s stacked wiring and trench configuration would yield the predictable result of a high-density image sensor with minimized signal interference and improved pixel to pixel isolation . 07-21-aia AIA Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2020/0058688 A1) in view of Na(US 2018/0190702 A1) . Regarding Claim 8, Kwon teaches the shield part ([0052] According to the present example embodiment, the image sensor 100 includes the shield structure 33 s that surrounds the first and second capacitors C1 and C2. Thus, a parasitic capacitance may be prevented or minimized between conductive lines (e.g., the third edge contact plug 37 p ) adjacent to the first and second capacitors C1 and C2, which may result in a reduction in coupling noise) . Kwon is not relied upon as teaching that the shield part includes a Low-k material. However, Na teaches a Low-k material ([0236] The dielectric fill 824 is typically an electrically insulating material with a dielectric constant lower than that of the surrounding absorption region 506. Electric field is able to penetrate further into a region of low dielectric constant compared to region of high dielectric constant. By placing the dielectric-filled trench 822 in proximity to the doped regions 802 and 812, some of the high electric field regions formed around the doped regions 802 and 812 and in depletion regions (“space charge region”) surrounding the doped regions 802 and 812 are pulled into the dielectric fill 824) . Kwon and Na are considered to be analogous to the claimed invention because they are both in the same field of semiconductor image sensors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the shield structure of Kwon to include the low-k material of Na with a reasonable expectation of success. This modification would have been motivated by the desire to minimize the parasitic capacitance and coupling noise inherent in high-density sensor arrays. By integrating Na’s teaching of utilizing a dielectric fill with a low dielectric constant to reduce electric field penetration and noise into Kwon’s shield structure, which is designed to prevent or minimize parasitic capacitance between conductive lines, the system can achieve a higher degree of signal integrity. A person of ordinary skill in the art would recognize that forming the shield part of Kwon using the low-k material property taught by Na would yield the predictable result of further reducing coupling noise . 07-21-aia AIA Claim s 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2020/0058688 A1) in view of Finkelstein (US 2022/0302184 A1) . Regarding Claim 10, Kwon is not relied upon as teaching that the sensor device is formed as a sensor device for distance measurement using an indirect ToF method. However, Finkelstein teaches that the sensor device is formed as a sensor device for distance measurement using an indirect ToF method ([0003] ToF 3D imaging systems may utilize… indirect ToF (iToF) measurement (where the amplitude of the emitted optical signal is modulated and the phase delay or phase shift of the reflected optical signal is measured…)) Kwon and Finkelstein are considered to be analogous to the claimed invention because they are both in the same field of semiconductor image sensors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the image sensor of Kwon to include the indirect Time-of-Flight (iToF) distance measurement of Finkelstein with a reasonable expectation of success. This modification would have been motivated by the desire to enable precise 3D range finding and depth profiling using a high-performance pixel architecture. By integrating the Finkelstein teaching of measuring phase shifts in reflected optical signals to determine distance into Kwon’s architecture, the system can effectively calculate depth data while maintaining high signal integrity through Kwon’s discloses shield structures. A person of ordinary skill in the art would recognize that utilizing Kwon’s sensor to implement Finkelstein’s iToF modulation would yield the predictable result of an accurate 3D image sensor with reduced parasitic capacitance and noise. Regarding Claim 11, Kwon teaches a sensing module ([0026] an image processing apparatus 200 may include an image sensor 110) , comprising: the sensor unit includes a semiconductor substrate ([0040] The image sensor 100 may include a substrate 1) and a wiring layer part disposed on the semiconductor substrate and having a plurality of wiring layers ([0044] First wiring lines 19 may be disposed on the first interlayer dielectric layer 15… [0045] The first interlayer dielectric layer 15 may be provided thereon with a second interlayer dielectric layer 21 covering the first wiring lines 19… [0053] Third wiring lines 39 may be disposed on the third interlayer dielectric layer 35) ; the semiconductor substrate and the wiring layer part constitute a laminated structure in which a pixel is disposed ([0040] As shown in FIG. 4, the second deep device isolation layer 3 b may be spaced apart from the first deep device isolation layer 3 a . In one pixel UP, the second deep device isolation layer 3 b may divide the substrate 1 into a first region R1 and a second region R2. The first region R1 may be a light-receiving section. The second region R2 may be a circuit section. The first and second device isolation layers 3 a and 3 b may penetrate the substrate 1) , the pixel including: a photoelectric conversion element that performs photoelectric conversion ([0041] A first impurity region 5 may be disposed in the substrate 1 of the first region R1… The first impurity region 5 and the substrate 1 therearound may constitute a PN junction to provide a photoelectric conversion region) ; a first charge holding part and a second charge holding part that hold charges accumulated in the photoelectric conversion element ([0048] The first bottom electrode 25 b 1, the first conductive pillars 27 b 1, the first dielectric layer 29 b 1, and a portion of the top electrode 31 u may constitute a first capacitor C1. The second bottom electrode 25 b 2, the second conductive pillars 27 b 2, the second dielectric layer 29 b 2, and a portion of the top electrode 31 u may constitute a second capacitor C2) ; a first transfer transistor that transfers the charges to the first charge holding part ([0034] For example, each unit pixel of the image sensor may include a photoelectric conversion region PD, a transfer transistor TX, a reset transistor RX, a first source follower transistor SF1, a pre- charge transistor PC, a sampling transistor SAM, a calibration transistor Cal, a second source follower transistor SF2, a selection transistor SEL, a first capacitor C1, and a second capacitor C2) ; and a second transfer transistor that transfers the charges to the second charge holding part ([0079] four transfer transistors TX1, TX2, TX3, and TX4 may share one floating diffusion region FD. In this case, four first regions R1 may be disposed adjacent to each other. The four transfer transistors TX1, TX2, TX3, and TX4 may be turned on in sequence. For example, when the first transfer transistor TX1 is turned on, charges accumulated in a first photoelectric conversion region PD1 may be sensed by the operation discussed with reference to FIG. 2. The same operation may be sequentially performed on the second, third, and fourth transfer transistors TX2, TX3, and TX4. Examiner Note: The operation discussed with reference to Fig. 2 is provided above in reference to Paragraph 34 ) ; and a shield part ([0045] The dummy bottom electrode 25 s may have a closed loop shape that surrounds the first and second bottom electrodes 25 b 1 and 25 b 2… [0049] When viewed in plan view, the dummy dielectric layer 29 s and the dummy top electrode 31 s may have a closed loop shape that surrounds the top electrode 31 u . The dummy bottom electrode 25 s , the dummy conductive pillars 27 s , the dummy dielectric layer 29 s , and the dummy top electrode 31 s may constitute a shield structure 33 s ) surrounding a gate wiring line is formed for the gate wiring line of each of the first transfer transistor and the second transfer transistor ([0052] The image sensor 100 includes the shield structure 33 s that surrounds the first and second capacitors C1 and C2. Thus, a parasitic capacitance may be prevented or minimized between conductive lines (e.g., the third edge contact plug 37 p ) adjacent to the first and second capacitors C1 and C2, which may result in a reduction in coupling noise. The image sensor 100 may thus produce a sharp image) extending in a thickness direction in the wiring layer part (Fig. 4 Examiner Note: Notice that element 33s in Fig. 4 (reproduced above) is shown in a thickness direction in the wiring layer part ) . Kwon is not relied upon as teaching a light-emitting unit that emits light for distance measurement; and a sensor unit that receives the light emitted from the light-emitting unit and reflected by an object, However, Finkelstein teaches a light-emitting unit that emits light for distance measurement; and a sensor unit that receives the light emitted from the light-emitting unit and reflected by an object ([0003]where the length of time between emitting an optical signal and sensing or detecting the optical signal after reflection from an object or other target is measured to determine distance… [0021] The optical sensor array is a light detection and ranging (LIDAR) detector array, and a source of the incident photons is a LIDAR emitter array) . Kwon and Finkelstein are considered to be analogous to the claimed invention because they are both in the same field of semiconductor image sensors. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified the sensing module of Kwon to include the light-emitting unit and sensor unit receiver of Finkelstein with a reasonable expectation of success. This modification would have been motivated by the desire to provide a complete 3D imaging solution capable of range finding and depth profiling. By integrating Finkelstein’s teaching of a light-emitting unit (LIDAR emitter array) that emits light and a sensor unit that receives reflected light to determine distance into Kwon’s pixel array, the system can perform active distance sensing while protecting sensitive signal lines from parasitic capacitance and noise. A person of ordinary skill in the art would recognize that utilizing the high-performance shielded pixel structure of Kwon as the receiver within the LIDAR or iToF system framework of Finkelstein would yield the predictable result of a distance measurement sensor with improved signal integrity and accurate depth map generation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVAN H HAUT whose telephone number is (571)272-7927. The examiner can normally be reached Monday-Thursday 10am-3pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at (571) 272-9358. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /E.H.H./Patent Examiner, Art Unit 3645 /HELAL A ALGAHAIM/SPE , Art Unit 3645 Application/Control Number: 18/249,098 Page 2 Art Unit: 3645 Application/Control Number: 18/249,098 Page 3 Art Unit: 3645 Application/Control Number: 18/249,098 Page 4 Art Unit: 3645 Application/Control Number: 18/249,098 Page 5 Art Unit: 3645 Application/Control Number: 18/249,098 Page 6 Art Unit: 3645 Application/Control Number: 18/249,098 Page 7 Art Unit: 3645 Application/Control Number: 18/249,098 Page 8 Art Unit: 3645 Application/Control Number: 18/249,098 Page 9 Art Unit: 3645 Application/Control Number: 18/249,098 Page 10 Art Unit: 3645 Application/Control Number: 18/249,098 Page 11 Art Unit: 3645 Application/Control Number: 18/249,098 Page 12 Art Unit: 3645 Application/Control Number: 18/249,098 Page 13 Art Unit: 3645