DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 12/08/2025 have been fully considered but they are not persuasive.
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Fig. 16 of Park (as labeled by examiner above) discloses the second power signal bus (solid line bus) comprises a first part (as labeled by examiner above) and a second part (as labeled by examiner above) disposed on opposite two sides of the first power signal bus in a first direction (X – across the page), so as to at least partially surround the first power signal bus,
wherein each of the first part and the second part extends along a second direction (Y – up and down the page) different from the first direction and extends beyond opposite edges of the first power signal bus.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. 20220157917.
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Regarding claim 1, fig. 16 of Park discloses a display substrate, having a display region DA, and a peripheral region at least partially surrounding the display region, and comprising:
a base substrate BSL, a plurality of sub-pixels (PXUs – par [0075]), disposed on the base substrate and located in the display region,
a first power signal line CDP1 and a second power signal line CDP2 (fig. 8), disposed on the base substrate and at least partially located in the display region,
wherein the first power signal line CDP2 is configured to transmit a first power signal to at least a portion of the plurality of sub-pixels, and the second power signal line CDP1 is configured to transmit a second power signal different from the first power signal to at least a portion of the plurality of sub-pixels (fig. 8);
a first power signal bus (dotted line bus) and a second power signal bus (solid line bus), disposed on the base substrate and located in the peripheral region,
wherein the first power signal line CDP1 is electrically connected to the first power signal bus (dotted line bus), and the second power signal line CDP2 is electrically connected to the second power signal bus (2 – solid line bus),
the second power signal bus (solid line bus) comprises a first part (as labeled by examiner above) and a second part (as labeled by examiner above) disposed on opposite two sides of the first power signal bus in a first direction (X – across the page), so as to at least partially surround the first power signal bus,
wherein each of the first part and the second part extends along a second direction (Y – up and down the page) different from the first direction and extends beyond opposite edges of the first power signal bus.
Regarding claim 2, fig. 14 of Park disclose further comprising: a light-shielding layer BML1, disposed on the base substrate, wherein each of the plurality of sub-pixels comprises a light emitting device and a pixel driving circuit for driving the light emitting device, and the pixel driving circuit is disposed on the light-shielding layer, the first power signal bus is disposed at a same layer (top surface of BSL) with the light-shielding layer.
Regarding claim 3, figs. 10 and 14 of Park discloses wherein the pixel driving circuit comprises a thin film transistor, the thin film transistor comprises a gate electrode disposed on the light-shielding layer and a source/drain electrode located on the gate electrode, the first part and the source/drain electrode are disposed at a same layer (top surface layer of BSL).
Regarding claim 4, Park discloses wherein the second part and the gate electrode are disposed at a same layer (top surface of BSL).
Regarding claim 5, fig. 16 of Park discloses wherein the second power signal bus further comprises a third part (left part) and a fourth part (right part) that are electrically connected with the first part and the second part, and the third part and the fourth part are located on opposite two sides of the first power signal bus, the first part, the second part, the third part and the fourth part together surround the first power signal bus.
Regarding claim 6, fig. 16 of Park discloses wherein the third part and the fourth part are disposed at a same layer (top surface of BSL) with the first part and are integrally connected with the first part.
Regarding claim 7, fig. 16 of Park discloses wherein a structure of the third part and a structure of the fourth part are symmetrical (around the DA as shown in fig. 16).
Regarding claim 8, fig. 16 of Park discloses further comprising: a first power connection line (connection point between APA2), disposed at a same layer with the first power signal bus, and electrically connected to the first power signal bus and the first power signal line.
Regarding claim 10, Park discloses wherein the second power signal line is disposed at a same layer (top surface of BSL) with the source/drain electrode.
Regarding claim 11, fig. 16 of Park discloses wherein the second power signal line extends from the display region to the peripheral region and is electrically connected to the first part.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Park.
Regarding claim 12, Park does not disclose of wherein an electrical potential of the first power signal is higher than an electrical potential of the second power signal.
Note that a recitation of the intended use such as “wherein an electrical potential of the first power signal is higher than an electrical potential of the second power signal” of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. See In re Casey, 152 USPQ 235 (CCPA 1967) and In re Otto, 136 USPQ 458, 459 (CCPA 1963).
Allowable Subject Matter
Claims 9 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893