DETAILED ACTION
Claims 14-26 are currently pending and have been examined in this application. Claims 1-13 have been cancelled.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is made FINAL in response to the “amendment” and “remarks” filed 06/22/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US20200019477) in view of Hyde (US20210300425) further in view of Ahmed (US20150193902).
Claim 14:
Jain explicitly teaches:
A data processing network for a redundant and validated carrying out of a plurality of successive data processing step, each of which is used to generate output data from input data, output data of a first data processing step being at least partially simultaneously input data of a further data processing step,
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
“One conventional strategy for avoiding random errors is to capture random errors by having multiple redundant processors, which have the same circuit design, simultaneously perform the same computational tasks on the same inputs and then their outputs are compared.” (Para 0003)
the data processing network comprising: at least a first data processor and a second data processor, the first and second data processors configured to be redundant such that each is configured to carry out each of the data processing steps; and a comparator,
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
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the first data processor and the second data processing module being configured to transmit [control parameters] of the data processing steps to the comparator
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
Examiner Note: Bracketed text not explicitly taught by primary reference, but is taught by non-primary reference later in the rejection.
the comparator processor and,
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
Examiner Note: Bracketed text not explicitly taught by primary reference, but is taught by non-primary reference later in the rejection.
Jain does not explicitly teach:
control parameters … control parameters …based on the comparison, to provide at least one synchronized control parameter that contains an item of control information relating to at least one data processing step that has been carried out; and a task distributer configured to, based on the at least one synchronized control parameter, plan and initiate the execution of subsequent data processing steps on available data processors, wherein the task distributer allocates processing tasks to the first and second data processors according to their current availability.
Hyde, in the same field of endeavor of vehicle data processing, teaches:
control parameters … control parameters …based on the comparison, to provide at least one synchronized control parameter that contains an item of control information relating to at least one data processing step that has been carried out; and a task distributer configured to, based on the at least one synchronized control parameter, plan and initiate the execution of subsequent data processing steps on available data processors,
(Hyde) – “FIG. 6 is a block diagram depicting a process 600 for generating autonomous vehicle functional outputs using functional circuitry and checking output consistency using monitoring circuitry according to example embodiments of the present disclosure.” (Para 0124)
“The monitoring circuitry 618 of the autonomous vehicle computing system can be used to determine a difference between the first output data 614 and second output data 616 of the functional circuits 606 and 612. More particularly, monitoring circuitry 618 can generate comparative data 620 associated with one or more differences between the first output data 614 and the second output data 616. As an example, first output data 614 may indicate a first output describing a first trajectory of an object external to the autonomous vehicle while second output data 616 may indicate a second trajectory of the object. If the first trajectory and the second trajectory are within a certain degree of similarity (e.g., a 5% variation in trajectory angle, a 10% difference in trajectory length, etc.), the comparative data 620 can indicate that the functionality of both outputs is assured.” (Para 0128)
“The autonomous vehicle computing system can generate one or more motion plans based at least in part on the comparative data 620. In some implementations, generating the one or more motion plans can include, if either of the first output data 614 or the second output data 616 are motion plans or otherwise include motion plans, selecting one of the outputs. As an example, both the first output data 614 and the second output data 616 may be motion plans. To generate the motion plan, the autonomous vehicle computing system can select either of the outputs as the motion plan.” (Para 0132)
“The autonomous vehicle computing system can generate one or more vehicle control signals 624 using a vehicle control signal generator 622…The vehicle control signals 624 can be based at least in part on the comparative data 620, the optimal output 621, and/or one or more motion plans.” (Para 0135)
Examiner Note: Per BRI, vehicle control signals corresponds with subsequent data processing steps.
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Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Hyde does not explicitly teach:
wherein the task distributer allocates processing tasks to the first and second data processors according to their current availability.
Ahmed, in the same field of endeavor of data processing, teaches:
wherein the task distributer allocates processing tasks to the first and second data processors according to their current availability.
(Ahmed) – “The method 400 further includes the first data processing system dynamically allocating the needed data processing between the first data processing system and the second data processing system, based on the capabilities of the second data processing system (act 408). The needed data processing consists of a first portion to be performed by the first data system and a second portion to be performed by the second data processing system.” (Para 0076)
“As will be discussed in more detail below, the capabilities may include information such as available processing power, available memory, available persistent storage, available hardware devices, available software applications installed, available managed runtime environments or development platforms, available human user interfaces, etc.” (Para 0019)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the data processing across first and second data processing systems of Ahmed. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order to “dynamically change the amount of data processing performed by each of the two systems.” (Ahmed Para 0014)
Claim 15:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the comparison of the control parameters includes an identity check, and each synchronized control parameter requires an identity of the control parameters from the first data processor and the second data processor.
(Hyde) – “FIG. 6 is a block diagram depicting a process 600 for generating autonomous vehicle functional outputs using functional circuitry and checking output consistency using monitoring circuitry according to example embodiments of the present disclosure.” (Para 0124)
“The monitoring circuitry 618 of the autonomous vehicle computing system can be used to determine a difference between the first output data 614 and second output data 616 of the functional circuits 606 and 612. More particularly, monitoring circuitry 618 can generate comparative data 620 associated with one or more differences between the first output data 614 and the second output data 616. As an example, first output data 614 may indicate a first output describing a first trajectory of an object external to the autonomous vehicle while second output data 616 may indicate a second trajectory of the object. If the first trajectory and the second trajectory are within a certain degree of similarity (e.g., a 5% variation in trajectory angle, a 10% difference in trajectory length, etc.), the comparative data 620 can indicate that the functionality of both outputs is assured.” (Para 0128)
“The autonomous vehicle computing system can generate one or more motion plans based at least in part on the comparative data 620. In some implementations, generating the one or more motion plans can include, if either of the first output data 614 or the second output data 616 are motion plans or otherwise include motion plans, selecting one of the outputs. As an example, both the first output data 614 and the second output data 616 may be motion plans. To generate the motion plan, the autonomous vehicle computing system can select either of the outputs as the motion plan.” (Para 0132)
Examiner Note: Per BRI, identity may correspond with aspect of the data which provides any context for the data.
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 16:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the data processing network is configured to use the at least one synchronized control parameter provided by the comparator
(Hyde) – “FIG. 6 is a block diagram depicting a process 600 for generating autonomous vehicle functional outputs using functional circuitry and checking output consistency using monitoring circuitry according to example embodiments of the present disclosure.” (Para 0124)
“The monitoring circuitry 618 of the autonomous vehicle computing system can be used to determine a difference between the first output data 614 and second output data 616 of the functional circuits 606 and 612. More particularly, monitoring circuitry 618 can generate comparative data 620 associated with one or more differences between the first output data 614 and the second output data 616. As an example, first output data 614 may indicate a first output describing a first trajectory of an object external to the autonomous vehicle while second output data 616 may indicate a second trajectory of the object. If the first trajectory and the second trajectory are within a certain degree of similarity (e.g., a 5% variation in trajectory angle, a 10% difference in trajectory length, etc.), the comparative data 620 can indicate that the functionality of both outputs is assured.” (Para 0128)
“The autonomous vehicle computing system can generate one or more motion plans based at least in part on the comparative data 620. In some implementations, generating the one or more motion plans can include, if either of the first output data 614 or the second output data 616 are motion plans or otherwise include motion plans, selecting one of the outputs. As an example, both the first output data 614 and the second output data 616 may be motion plans. To generate the motion plan, the autonomous vehicle computing system can select either of the outputs as the motion plan.” (Para 0132)
“the monitoring circuitry 618 can both assure the first output data 614 and the second output data 616 while also determining an optimal output 621 for input to the vehicle control signal generator 622.” (Para 0134)
Examiner Note: “further data processing steps” is recited with a high degree of generality and may correspond with any form of data processing.
Claim 17:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the at least one synchronized control parameter is a validity parameter that contains an item of validity information relating to least one of the data processing steps that has been carried out.
(Hyde) – “the autonomy computing system can utilize the plurality of functional circuits to assure the validity of an output by generating a plurality of outputs and evaluating a consistency between the outputs. For example, the autonomous vehicle can obtain sensor data from a sensor system of the autonomous vehicle and process the sensor data using two or more functional circuits to generate two individual outputs associated with an autonomous compute function. The autonomous vehicle computing system can determine if significant differences exist between the two outputs (e.g., by using an assured monitoring circuit, validating the outputs using opposite functional circuitries, etc.).” (Para 0026)
“FIG. 6 is a block diagram depicting a process 600 for generating autonomous vehicle functional outputs using functional circuitry and checking output consistency using monitoring circuitry according to example embodiments of the present disclosure.” (Para 0124)
“The monitoring circuitry 618 of the autonomous vehicle computing system can be used to determine a difference between the first output data 614 and second output data 616 of the functional circuits 606 and 612. More particularly, monitoring circuitry 618 can generate comparative data 620 associated with one or more differences between the first output data 614 and the second output data 616. As an example, first output data 614 may indicate a first output describing a first trajectory of an object external to the autonomous vehicle while second output data 616 may indicate a second trajectory of the object. If the first trajectory and the second trajectory are within a certain degree of similarity (e.g., a 5% variation in trajectory angle, a 10% difference in trajectory length, etc.), the comparative data 620 can indicate that the functionality of both outputs is assured.” (Para 0128)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 18:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
further comprising: at least one sequentialization processor configured to sort and to synchronize the control parameters from at least one of the first and second dataprocessors or the data processing steps respectively, and to then forward the sorted and synchronized control parameters with a sorting to the comparator processors have executed the data processing steps.
(Hyde) – “The monitoring circuitry can be configured to evaluate the outputs according to the specified order in which the outputs are received. The specified order in which the outputs are received can be the same order in which the sensor data is obtained and the outputs are generated. By evaluating the outputs in the specified order, the monitoring circuitry can determine an output consistency of the respective outputs.” (Para 0052)
“the autonomy compute architecture may specify a plurality of functional circuits each configured to utilize different hardware resources (e.g., differing amounts of compute power, different hardware configurations, etc.) to generate identical outputs in an asynchronous manner.” (Para 0062)
“Each of the functional circuits (e.g., 806A-806D) can use neural network(s) (e.g., neural network(s) 808A-808D) to generate respective output data (e.g., 810A-810D) over a time period (e.g., an amount of time required to process the input and generate an output). The respective outputs 810A-810D (e.g., a motion plan, perception, prediction, object trajectory, pose, etc.) can be based at least in part on the sensor data 804. As the time period represents the amount of time required for processing over all of the functional circuits 806A-806D, the time period can be variable and can vary based on the computational capacity of each functional circuit. As an example, the first functional circuitry 806A including four GPUs may generate the output over a smaller portion of the time period than second functional circuitry 806B with a single GPU. Further, even assuming that all functional circuits have identical computational capacity, the sequential and asynchronous input of sensor data 804 to each of the respective functional circuits 806A-806D can lead to a sequential and asynchronous generation of respective outputs 810A-810D. More particularly, the outputs 810A-810D can be generated in the same specified order as the inputs (e.g., sensor data 804). As the outputs 810A-810D are generated, the outputs 810A-810D can be sent to monitoring circuitry 812” (Para 0149)
“The monitoring circuitry 812 can be configured to evaluate the output data 810A-810D according to the specified order in which the outputs are received. The specified order in which the output data 810A-810D is received by the monitoring circuitry 812 can be the same order in which the sensor data 804 is obtained and the output data is generated. By evaluating the output data 810A-810D in the specified order, the monitoring circuitry 812 can determine output consistency data 814 that evaluates a consistency between the output data 810A-810D.” (Para 0151)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 19:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain further teaches:
wherein the first data processor is realized with first hardware components and the second data processor is realized with second hardware components, the first hardware components and the second hardware components being physically separated from each other.
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
“One conventional strategy for avoiding random errors is to capture random errors by having multiple redundant processors, which have the same circuit design, simultaneously perform the same computational tasks on the same inputs and then their outputs are compared. The multiple processors are typically separate substantially identical cores of a system on chip (SoC) device.” (Para 0003)
Examiner Note: Per BRI, “physically separated” may correspond to any form or degree of separation of the components.
Claim 20:
Jain in combination with the references relied upon in Claim 19 teach those respective limitations. Jain further teaches:
wherein at least one of the first and second processors has a hardware component that is [not ASIL-D compliant].
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
“One conventional strategy for avoiding random errors is to capture random errors by having multiple redundant processors, which have the same circuit design, simultaneously perform the same computational tasks on the same inputs and then their outputs are compared. The multiple processors are typically separate substantially identical cores of a system on chip (SoC) device.” (Para 0003)
Examiner Note: Jain teaches hardware which has no teaching of being ASIL-D compliance due to a lack of inclusion of ASIL-D from the disclosure, though it is not explicitly taught as being non-compliant. For clarity the bracketed text will be explicitly taught by non-primary reference.
Jain does not explicitly teach:
not ASIL-D compliant
Hyde, in the same field of endeavor of vehicle data processing, teaches:
not ASIL-D compliant
(Hyde) – “The data associated with the sensor system can be received by the non-assured functional circuitry 912. Non-assured functional circuitry 912 can be or otherwise include hardware components (e.g., processor(s), ASIC(s), FPGA(s), etc.) that are not certified to a certain functional safety standard (e.g., ASIL-D of ISO26262, etc.).” (Para 0165)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 21:
Jain in combination with the references relied upon in Claim 19 teach those respective limitations. Jain further teaches:
wherein the comparator is realized with third hardware components which are physically separated from the first hardware components and the second hardware components.
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
Examiner Note: Fig. 1 shows the comparator as being separate hardware. Per BRI, “physically separated” may correspond to any form or degree of separation of the components.
Claim 22:
Jain in combination with the references relied upon in Claim 21 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the third hardware components are ASIL-D compliant.
(Hyde) – “The autonomous vehicle compute architecture can include one or more monitoring circuits. A monitoring circuit can, in some implementations, include any and/or all of the hardware devices previously mentioned with regards to the functional circuit. As an example, a monitoring circuit can include a PCB, a CPU, memory, and storage device(s). Further, in some implementations, the components of the monitoring circuit can be assured to a specified functional safety standard (e.g., ASIL-D of ISO 26262, etc.). More particularly, the monitoring circuit itself can be assured, and therefore, with the right considerations, the monitor circuit can assure the functionality of outputs of the functional circuits and/or assure the proper operation of the functional circuits themselves.” (Para 0033)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 23:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the comparator has a data memory in which ascertained control parameters are stored with items of time information, so that a logical timeline is produced that maps a sequence of processing of the data processing steps with the first and second data processors of the data processing network.
(Hyde) – “As another example, the autonomy computing system can process the sensor data using a plurality of functional circuits in a specified order (e.g., processing sensor data obtained at time 1 with first processing circuitry, processing sensor data obtained at time 2 with second processing circuitry, etc.). The autonomous vehicle computing system can utilize monitoring circuitry to determine a level of consistency across the outputs of the functional circuits, and can determine an optimal output based on this consistency.” (Para 0026)
“The monitoring circuitry can be configured to evaluate the outputs according to the specified order in which the outputs are received. The specified order in which the outputs are received can be the same order in which the sensor data is obtained and the outputs are generated. By evaluating the outputs in the specified order, the monitoring circuitry can determine an output consistency of the respective outputs. More particularly, the monitoring circuitry can detect large variations between outputs over time. It should be noted that the sensor data obtained by each functional circuit can be different (e.g., based on the time it was obtained, etc.) and therefore each output should not necessarily be identical. Instead, the output consistency can measure large variations in the outputs to determine if the outputs are sufficiently consistent.” (Para 0052)
“A monitoring circuit can, in some implementations, include any and/or all of the hardware devices previously mentioned with regards to the functional circuits (e.g., 202, 206, etc.). As an example, monitoring circuitry 210 can include a PCB, a CPU, memory, and storage device(s).” (Para 0103)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 24:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain further teaches:
wherein a hardware component of the first and second data processors is
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
Examiner Note: See 112b rejection. Jain teaches various power intensive forms of hardware for the processing units which would be more powerful that a comparator.
Claim 25:
Jain in combination with the references relied upon in Claim 14 teach those respective limitations. Jain does not explicitly teach the following limitations in full. Hyde further teaches:
wherein the comparison of the control parameters includes a check of whether an error occurring during data processing in at least one of the first data processor or in the second data processor is below a tolerance limit, and wherein, based on the result of the check, a synchronized control parameter
(Hyde) – “The autonomous vehicle computing system can determine if significant differences exist between the two outputs (e.g., by using an assured monitoring circuit, validating the outputs using opposite functional circuitries, etc.). For example, if the difference(s) between the outputs does not satisfy a threshold difference (e.g., trajectory outputs deviate by a certain degree, only one output recognizes the presence of an object, etc.), the autonomy computing system can operate in a normal operational state, for instance by selecting one of the outputs or combining the outputs for use in generating motion plans, control signals, etc. for the autonomous vehicle. If the difference(s) between the outputs satisfies a threshold difference, however, the autonomy computing system can initiate one or more actions, such as by generating a motion plan to bring the vehicle to a safe stop.” (Para 0026)
Examiner Note: See 112b rejection.
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Claim 26:
Jain explicitly teaches:
A method for operating a data processing network, comprising the following steps: a) carrying out a data processing step with a first data processorprocessor processor processor
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
“One conventional strategy for avoiding random errors is to capture random errors by having multiple redundant processors, which have the same circuit design, simultaneously perform the same computational tasks on the same inputs and then their outputs are compared.” (Para 0003)
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c) carrying out, with a comparator, a comparison of corresponding [control parameters] that were transmitted by the first data processorprocessor
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
Examiner Note: Bracketed text not explicitly taught by primary reference, but is taught by non-primary reference later in the rejection.
wherein the first and second data processors are configured to be redundant such that each is configured to carry out each of the data processing steps.
(Jain) – “FIG. 1 is a simplified schematic diagram of system 100 in accordance with one embodiment of the disclosure. System 100 may be an SoC device. System 100 comprises a plurality of redundant processing units 101, such as processing units 101(0) and 101(1), and a comparator 102. All of the processing units 101 have the same circuit design so that given identical inputs—and barring any unique processing errors—each would produce identical outputs. In other words, the processing units 101(0) and 101(1) are substantially identical. Note that inputs to processing units include both commands and data.” (Para 0025)
“A processing unit 101 may be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a digital signal processor (DSP). When each of the plurality of processing units 101 performs redundant processing of corresponding identical inputs (not shown), the comparator 102 compares corresponding result output signals 101a—such as, e.g., outputs 101a(0) and 101a(1)—of the processing units 101 to determine whether a unique processing error occurred in one of the processing units 101. Specifically, if the comparator 102 determines that the values received from result outputs 101a are not all identical, then the comparator provides an output indicating that at least one of the processing units 101 suffered a processing error.” (Para 0026)
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Jain does not explicitly teach:
control parameter … control parameter …control parameters …based on the comparison, providing at least one synchronized control parameter that contains an item of control information relating to at least one data processing step that was carried out; and d) planning and initiating, based on the at least one synchronized control parameter, via a task distributer,
Hyde, in the same field of endeavor of vehicle data processing, teaches:
control parameters … control parameters … based on the comparison, providing at least one synchronized control parameter that contains an item of control information relating to at least one data processing step that was carried out; and d) planning and initiating, based on the at least one synchronized control parameter, via a task distributer,
(Hyde) – “FIG. 6 is a block diagram depicting a process 600 for generating autonomous vehicle functional outputs using functional circuitry and checking output consistency using monitoring circuitry according to example embodiments of the present disclosure.” (Para 0124)
“The monitoring circuitry 618 of the autonomous vehicle computing system can be used to determine a difference between the first output data 614 and second output data 616 of the functional circuits 606 and 612. More particularly, monitoring circuitry 618 can generate comparative data 620 associated with one or more differences between the first output data 614 and the second output data 616. As an example, first output data 614 may indicate a first output describing a first trajectory of an object external to the autonomous vehicle while second output data 616 may indicate a second trajectory of the object. If the first trajectory and the second trajectory are within a certain degree of similarity (e.g., a 5% variation in trajectory angle, a 10% difference in trajectory length, etc.), the comparative data 620 can indicate that the functionality of both outputs is assured.” (Para 0128)
“The autonomous vehicle computing system can generate one or more motion plans based at least in part on the comparative data 620. In some implementations, generating the one or more motion plans can include, if either of the first output data 614 or the second output data 616 are motion plans or otherwise include motion plans, selecting one of the outputs. As an example, both the first output data 614 and the second output data 616 may be motion plans. To generate the motion plan, the autonomous vehicle computing system can select either of the outputs as the motion plan.” (Para 0132)
“The autonomous vehicle computing system can generate one or more vehicle control signals 624 using a vehicle control signal generator 622…The vehicle control signals 624 can be based at least in part on the comparative data 620, the optimal output 621, and/or one or more motion plans.” (Para 0135)
Examiner Note: Per BRI, vehicle control signals corresponds with subsequent data processing steps.
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Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the methods of using a blockchain for managing the autonomy computing system of Hyde. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order “to allow assured processing of outputs in an autonomous vehicle computing system.” (Hyde Para 0002)
Hyde does not explicitly teach:
wherein the task distributer allocates processing tasks to the first and second data processors according to their current availability, and
Ahmed, in the same field of endeavor of data processing, teaches:
wherein the task distributer allocates processing tasks to the first and second data processors according to their current availability, and
(Ahmed) – “The method 400 further includes the first data processing system dynamically allocating the needed data processing between the first data processing system and the second data processing system, based on the capabilities of the second data processing system (act 408). The needed data processing consists of a first portion to be performed by the first data system and a second portion to be performed by the second data processing system.” (Para 0076)
“As will be discussed in more detail below, the capabilities may include information such as available processing power, available memory, available persistent storage, available hardware devices, available software applications installed, available managed runtime environments or development platforms, available human user interfaces, etc.” (Para 0019)
Therefore, it would be obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the redundant processing modules of Jain with the data processing across first and second data processing systems of Ahmed. One of ordinary skill in the art would have been motivated to make these modifications, with a reasonable expectation of success, in order to “dynamically change the amount of data processing performed by each of the two systems.” (Ahmed Para 0014)
Response to Arguments
Applicant's arguments with respect to the 35 U.S.C. 103 rejection mailed 02/20/2026 have been fully considered but are not convincing. Rejection has been updated to reflect amendment.
Specifically, Applicant argues:
“Applicant submits that Jain in view of Hyde and Ahmed fails to disclose each and every element of claim 14. For example, Jain in view of Hyde and Ahmed fails to teach or suggest "a task distributer configured to ... plan and initiate the execution of subsequent data processing steps on available data processors," as recited in claim 14. Furthermore, the references cannot be combined as alleged in the Office Action, and Jain in view of Hyde and Ahmed additionally fails to teach or suggest "the first and second data processors configured to be redundant such that each is configured to carry out each of the data processing steps," as recited in claim 14.
In rejecting claim 14, the Office Action alleges that "Hyde ... teaches: ... a task distributor configured to, based on the at least one synchronized control parameter, plan and initiate the execution of subsequent data processing steps on available data processors." Action at 7. However, Hyde cannot teach this. The Office Action attempts to map Hyde's "generat[ion] [of] one or more vehicle control signals 624 using a vehicle control signal generator 622" to a task distributor planning and initiating the execution of subsequent data processing steps, further adding that "[per] BRI, vehicle control signals corresponds with subsequent data processing steps." Action at 8. Per this mapping, Hyde's vehicle control signals-ones that "control the vehicle"- allegedly constitute "subsequent data processing steps."
Referring to Hyde's FIG. 6 (reproduced below), these control signals cannot constitute "subsequent data processing steps."
FIG.6
In one aspect, Hyde's data processing steps occur exclusively between 604 and 622, as evidenced by the label of "AUTONOMOUS VEHICLE COMPUTING SYSTEM." Hyde is silent as to any exterior processing/computing occurring outside of the computing system, and thus, as the vehicle control signals are depicted outside of the computing system, these cannot comprise data processing steps.
Accordingly, Hyde's vehicle control signals are 1) an output of the system, and thus, not "processing steps;" and 2) not subject to "subsequent data processing." Hyde teaches that these vehicle control signals are configured as an output that results in direct actuation of the vehicle. Hyde is silent as to any further processing or subsequent steps that occur as a result of the vehicle control signals. Accordingly, the mapping presented in the Office Action fails, and Hyde cannot teach "a task distributor configured to, based on the at least one synchronized control parameter, plan and initiate the execution of subsequent data processing steps on available data processors."
It is not convincing to argue that “Hyde's vehicle control signals are 1) an output of the system, and thus, not "processing steps;" and 2) not subject to "subsequent data processing."” This assertion provides an overly narrow interpretation of “processing step” which is recited with a significantly large degree of generality. Any processing or output by a processor (or similar hardware) may correspond to a processing step. As such, the output control signals of Hyde do correspond with subsequent processing steps. It is unclear how such an alleged distinction could be justified without further narrowing the limitations of the claim.
Applicant further argues:
“Even if, arguendo, Hyde is argued to teach the task distributor, the Jain, Hyde, and Ahmed combination cannot teach each and every limitation of the claim. The Office Action relies upon Ahmed to allegedly teach "wherein the task distributor allocates processing tasks to the first and second data processors according to their current availability." Action at 10. However, Ahmed would be incompatible with Jain and Hyde, and thus, could not be used to supply the deficiencies as alleged.
For example, Ahmed is directed to the "[d]ivision of processing between systems." Ahmed at Title (emphasis added). Specifically, a first data processing system receives information defining a desired result, then "dynamically allocates the needed data processing between the first data processing system and the second data processing system." Ahmed at Abstract. Ahmed thus teaches the splitting of processing between two processing systems, rather than the repetition of the same processing on each of two systems.
In fact, the Office Actions own citations, such as "[t]he needed data processing consists of a first portion to be performed by the first data system and a second portion to be performed by the second data processing system" completely undermines the combination into Hyde, and the mapping onto present claim 14. Action at 10. Even the stated motivation of "in order to 'dynamically change the amount of data processing performed by each of the two systems[]"' undermines this point-both Jain and Hyde require a redundant, mirrored processing procedure. Action at 10. Thus, Ahmed is incompatible with, and would not be combined with, Jain and Hyde (either individually or in combination).
While Applicant respectfully traverses the current rejections, claim 14 has been amended to recite that "the first and second data processors configured to be redundant such that each is configured to carry out each of the data processing steps," thereby rendering moot any potential mapping of Ahmed onto the claimed language. Consequently, the cited portions of Jain, Hyde, and Ahmed, individually or in combination, fail to disclose each and every element of claim 14. Hence, claim 14 is patentable. Claims 15-25 are patentable, at least by virtue of depending from a patentable claim. Claim 26 recites limitations similar to claim 14, and is thus patentable for reasons similar to those described above. Accordingly, withdrawal of the rejections is requested.”
However, this is unconvincing. Ahmed clearly teaches the allocation of processing to two processing systems based on available processing power, available memory, available persistent storage, etc. (Ahmed Para 0019 and 0076) which is what it is relied upon to teach. Jain clearly and explicitly teaches first and second processors configured to be redundant (Jain 0025-0025, Fig. 1). As fully evidenced above, the combination of the two in addition to Hyde teaches all of the claimed limitations with motivations for combining provided above. Merely pointing out differences between different references is not sufficient to negate the propriety of this combination.
As such, all remaining claims remain rejected over 35 U.S.C. 103.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Agarwal (US20210405915) teaches a similar task scheduling with redundant processing data.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID RUBEN PEDERSEN whose telephone number is (571)272-9696. The examiner can normally be reached M-Th: 07:00 -16:00 Eastern.
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/DAVID RUBEN PEDERSEN/Examiner, Art Unit 3658
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