Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is responsive to the applicant's amendment and request for continued examination (RCE) submitted on 12/22/2025. Claims 1, 3, 5-6 and 9 have been amended. Claims 20-22 have been previously canceled. Thus, claims 1-19 and 23 are currently pending in the instant application.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/22/2025 has been entered.
Claim Objections
Claims 3, 7-8, 10, 13 and 23 are objected to because of the following informalities:
In claim 3, lines 1-2, it is suggested that the limitation recites “wherein in case of the control signal being a current, a power output will be the sum of the power generated by two microdevices” should be changed to --wherein when the control signal is a current, a power output is a sum of the power generated by two microdevices-- to make it clearer.
In claim 7, lines 1-2, it is suggested that the limitation recites “wherein a control signal is a voltage, and an output power is a sum of a power generated by each microdevice” should be changed to --wherein when a control signal is a voltage, a power output is a sum of the power generated by each microdevice-- to make it clearer.
In claim 8, lines 1-2, it is suggested that the limitation recites “the method of claim 6, wherein the control signal is a current, the output power is a weighted average of the two microdevices” should be changed to --The method of claim 7, wherein when the control signal is a current, the power output is a weighted average of the two microdevices-- to make it clearer and to avoid antecedence basis.
In claim 10, lines 1-2, it is suggested that the limitation recites " wherein a ratio of the two devices is operated in different operating conditions” should be changed to --wherein a ratio of the two microdevices is operated in different operating conditions-- to make it clearer and to avoid antecedence basis.
In claim 23, line 1, it is suggested to add a comma in between --The method of claim 6, wherein--.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-19 and 23 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 19189633 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claim limitations of the copending application no. 19189633 are clearly anticipated the claim limitations of the pending application. They are containing the same essential limitations, and they are both containing same structure configured to do the same function.
Regarding claims 1-19 and 23, the limitations of the applicant's claims are obvious variations of the mapped claims above. While the pending claims use different vernacular than the copending claims. For example, the pending claim 1 recites the limitation "connecting the two microdevices from at least one contact point in a series structure" and the copending claim 1 recites the limitation "connecting the two microdevices from at least one contact point in a series structure within a pixel or a subpixel," the pending claim 6 recites the limitation “connecting the two microdevices in parallel” and the copending claim 11 recites the limitation “connecting the two microdevices in parallel within a pixel or a subpixel,” and the pending claim 9 recites the limitation “controlling the two microdevices separately” and the copending 15 recites the limitation “controlling the two microdevices separately, wherein the two microdevices are integrated within a pixel or a subpixel.” Also, the dependent claims of pending application are similar to the dependent claims of copending application. The principle difference is that the pending claims are broader in scope than the copending claims. It is generally understood that anticipation is the epitome of obviousness. Alternatively, the elimination of an element and its function is generally held to be within the skill of the art. Therefore, it would have been obvious that the claims 1-19 and 23 of pending application has the same structures as claims 1-20 of copending application no. 19189633.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 6 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the limitation recites “controlling the series structure through other accessible contact points” is unclear and leaves the reader in doubt as to the meaning of the technical feature to which it refers. It is unclear that how does it control controlling the series structure through other accessible contact points?
Regarding claim 2, the limitation recites “wherein a control signal is an application of a current or coupling to a voltage level” is unclear and leaves the reader in doubt as to the meaning of the technical feature to which it refers. It is unclear that where does a control signal coming from? And what is a coupling to a voltage level?
Regarding claim 6, the limitation recites “controlling the parallel microdevices structure by at least two contact points of each microdevice that are coupled to each other” is unclear and leaves the reader in doubt as to the meaning of the technical feature to which it refers. It is unclear that how does it control controlling the parallel microdevices structure by at least two contact points of each microdevice?
Regarding claim 9, the limitation recites “controlling the two microdevices separately; and optimizing each microdevice for separate operations by biasing the microdevices differently for each operation condition” is unclear and leaves the reader in doubt as to the meaning of the technical feature to which it refers. It is unclear that how does it control the two microdevices separately? How does it optimizing each microdevice for separate operations? And how does it bias the microdevices differently for each operation condition?
The claim fails to recite sufficiently definite structure, material or acts for achieving the functional result recited in the claim to reasonably apprise one of ordinary skill in the art of the scope of the claim.
Note: for compact prosecution purposes, the examiner interprets the claims above as best understood in the rejections below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a1) as being anticipated by Sakariya et al. (U.S Publication No. 20140168037 A1).
Regarding claim 1, Sakariya discloses a method to integrate two microdevices in pixels or subpixels (which is a smart pixel lighting and display microcontroller, see fig. 1-17) comprising:
connecting the two microdevices (which includes LED device 115 and microcontroller 110 via a smart pixel 120) from at least one contact point in a series structure (In this figure, and in the figures to follow, each illustrated LED device 115 may represent a single LED device, or may represent multiple LED devices arranged in series, in parallel, or a combination of the two, such that that multiple LED devices may be driven from the same control signal, see fig. 1, paragraph [0041] and [0044]-[0045]); and
controlling the series structure through other accessible contact points (which is the smart-pixel .mu.C 110 is configurable to accept at least one input, which can control at least one LED device, or at least one group of LED devices in series, parallel, or a combination of the two, see paragraph [0044]-[0045]).
Regarding claim 2, Sakariya discloses the method of claim 1, wherein a control signal is an application of a current or coupling to a voltage level (In one embodiment, the smart-pixel micro matrix 100 is manufactured on a receiving substrate, which has been prepared with distribution lines 125 to couple the various .mu.C devices 110 and the LED devices 115. In one embodiment, the distribution lines include scan lines, which are coupled to one or more scan drivers V.sub.select, and data lines, which are coupled to one or more data drivers V.sub.data, see paragraph [0041] and [0044]-[0045]).
Regarding claim 3, Sakariya discloses the method of claim 2, wherein in case of the control signal being a current, a power output is a sum of the power generated by two microdevices (see paragraph [0044]-[0045]), (and when the two microdevices are connected in series is implicit as disclosed in the description of the present application, see page 4, lines 1-2, “if the microdevice is micro LED and the control signal is current, the power output will be the sum of the power generated by two devices).
Regarding claim 4, Sakariya discloses the method of claim 3, wherein the microdevices are micro light emitting diodes (LEDs), (see fig. 1, paragraph [0031] and [0041]).
Regarding claim 5, Sakariya discloses the method of claim 2, wherein the microdevices are sensors (see paragraph [0032]), the control signal is in the form of electrical positive or negative charge or current being averaged (see fig. 1 and 11, paragraph [0032] and [0057]), (and the control signal being an averaged when the two microdevices are connected in series is implicit as disclosed in the description of the present application, see page 4, lines 3-4, “in the case of a sensor, the control signal will be averaged”).
Regarding claim 6, Sakariya discloses a method to integrate two microdevices in pixels or subpixels (which is a smart pixel lighting and display microcontroller, see fig. 1-17) comprising:
connecting the two microdevices (which includes LED device 115 and microcontroller 110 via a smart pixel 120) in parallel (In this figure, and in the figures to follow, each illustrated LED device 115 may represent a single LED device, or may represent multiple LED devices arranged in series, in parallel, or a combination of the two, such that that multiple LED devices may be driven from the same control signal, see fig. 1, paragraph [0041] and [0044]-[0045]); and
controlling the parallel microdevices structure by at least two contact points of each microdevice that are coupled to each other (which is the smart-pixel .mu.C 110 is configurable to accept at least one input, which can control at least one LED device, or at least one group of LED devices in series, parallel, or a combination of the two, see paragraph [0044]-[0045]).
Regarding claim 7, Sakariya discloses the method of claim 6, wherein a control signal is a voltage, and an output power is a sum of a power generated by each microdevice (see paragraph [0044]-[0045]), (and when the two microdevices are connected in parallel is implicit as disclosed in the description of the present application, see page 4, lines 6-8, “in case of micro LED, if the control signal is voltage the output power will be the sum of the power generated by each device).
Regarding claim 8, Sakariya discloses the method of claim 6, wherein the control signal is a current, the output power is a weighted average of the two microdevices (see paragraph [0044]-[0045]), (and when the two microdevices are connected in parallel is implicit as disclosed in the description of the present application, see page 4, line 9, “if the control signal is current, the output power will be the weighted average of the two devices).
Claims 9-10 are rejected under 35 U.S.C. 102(a1) as being anticipated by Charisoulis et al. (U.S Patent No. 10395594 B1).
Regarding claim 9, Charisoulis discloses a method to integrate two microdevices in pixels or sub pixels (which is methods, systems, and apparatuses for controlling an emission of the light emitting devices are described herein. The light emitting devices may be light emitting diode (LED) devices including μLED devices or organic LED, see fig. 1) devices comprising:
controlling the two microdevices separately, wherein the two microdevices are integrated within a pixel or a subpixel (n this figure, and in the figures to follow, each illustrated LED device, e.g., micro LED 115, may represent a single LED device, or may represent multiple LED devices arranged in series, in parallel, or a combination of series and parallel. The LED devices can couple to a common ground or may each have a separate ground connection. The exemplary hybrid micro driver display architecture 100 illustrated shows three control inputs and six LED outputs, but embodiments are not so limited. A single micro Driver IC 110 can control multiple lighting emitting devices, where each lighting devices has a separate analog input into the micro Driver IC 110, see fig. 1, col. 5, lines 45-55); and
optimizing each microdevice for separate operations by biasing the microdevices differently for each operation condition (see col. 11, lines 22-31, and col. 13, lines 16-24).
Regarding claim 10, Charisoulis discloses the method of claim 9, wherein a ratio of the two devices is operated in different operating conditions by biasing the microdevices differently for each operation condition (see col. 11, lines 22-31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al. (U.S Patent No. 10395594 B1) in view of Henley (U.S Publication No. 20180174931 A1).
Regarding claims 11-14, Charisoulis discloses all the limitations of 10, except for specifying that wherein a smoothing function is being used to transition between the two microdevices; wherein the two microdevices are micro light emitting diodes (LEDs), a first microdevice has better external quantum efficiency (EQE) at higher current levels while a second microdevice has a better EQE at a lower current density; wherein for lower current levels of operation, the second microdevice is turned ON and for higher current level of operation, the first microdevice is turned ON; wherein for a middle current level, the two microdevices are ON at the same time and the level of control signal for each said microdevice is decided by a smoothing function.
Henley discloses micro-LED device characterization data such as external quantum efficiency as a function of forward bias current density (see paragraph [0002] and [0009]). Henley further discloses the external quantum efficiency is sensitive to current density and other device characteristics (see paragraph [0064] and equation 7). Henley discloses where a microdevices having better EQE at higher current levels while
another microdevice has a better EQE at a lower current density.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention was made to modify the method as taught by Charisoulis with the method as taught by Henley so that microdevice is turn on based on its characterization data and current level. And the use of a smoothing function would have been obvious to a person skilled in the art having regard to the combination of Charisoulis in view of Henley, which is the common general knowledge.
Claims 15 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Sakariya et al. (U.S Publication No. 20140168037 A1)in view of Chaji et al. (U.S Publication No. 20220208738 A1).
Regarding claims 15 and 23, Sakariya discloses all the limitations of the method of claims 1 and 6, except for specifying that wherein the two microdevices share some common layers and each have separated layers as well.
Chaji, on the other hand, discloses structures and methods are disclosed for fabricating optoelectronic solid state array devices. And there may be a plurality of micro devices on the micro device substrate to form a micro device array. According to yet another embodiment, a method of fabricating a micro device array may comprise steps of providing an array of micro devices having bumps on a top surface of a substrate, forming at least one common contact at one or more common layers of the substrate, forming a bridge for the common contact close to a height of the micro devices. In another case, common layers may include active layers (e.g., quantum wells). The micro device may be covered by a passivation layer. The passivation layer may have an opening on top of the device to provide an electrical coupling path to the micro device. In one embodiment, the micro device may be covered by a passivation layer and the space between the micro devices may be filled by a dielectric layer prior to the adhesive layer. The dielectric layer can be black matrix or reflective. In another embodiment, a planarization layer may be formed on or over the array of micro devices covering the height of the micro devices. The planarization layer may be an adhesive layer(see paragraph [0005], [0032], [0035], [0046], [0052], and [0086]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention was made to modify the method as taught by Charisoulis with the method as taught by Chaji the two microdevices share some common layers and each have separated layers as well, which is considered as an obvious matter of design choice based upon an actual design requirement so that the various designs of circuit may be satisfied.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al. (U.S Patent No. 10395594 B1) in view of Chaji et al. (U.S Publication No. 20220208738 A1).
Regarding claims 16 and 17, Charisoulis discloses all the limitations of the method of claim 15, except for specifying that wherein the two microdevices have functional layers between current injection layers and one of the current injection layers is the common layer and the functional layers are separated; and wherein one of charge injection layers and functional layers are common and the other charge injection layer is separated to form two different layers.
Chaji, on the other hand, discloses structures and methods are disclosed for fabricating optoelectronic solid state array devices. And there may be a plurality of micro devices on the micro device substrate to form a micro device array. In one case, the bump provided on the at least one micro device is conductive. The micro device array may have one or more common layers. In one case, the common layer may be a second electrode. In another case, common layers may include active layers (e.g., quantum wells). The micro device may be covered by a passivation layer. The passivation layer may have an opening on top of the device to provide an electrical coupling path to the micro device (see abstract, paragraph [0052]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention was made to modify the method as taught by Charisoulis with the method as taught by Chaji having the additional features related to the common layer(s) in which the two microdevices have functional layers between current injection layers and one of the current injection layers is the common layer and the functional layers are separated; and wherein one of charge injection layers and functional layers are common and the other charge injection layer is separated to form two different layers, which is considered as an obvious matter of design choice based upon an actual design requirement so that the various designs of circuit may be satisfied.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al. (U.S Patent No. 10395594 B1) in view of Zhang et al. (U.S Publication No. 20210202616 A1).
Regarding claims18 and 19, Charisoulis discloses all the limitations of the method of claim 15, except for specifying that wherein sizes of the two microdevices are different, and wherein material and structure of microdevices are different to form different operation characteristics.
Zhang, on the other hand, discloses an integrated multi-color micro-LED display panel, arrays of different color micro LEDs are integrated with corresponding driver circuitry. Some colors of micro LEDs are inorganic micro LEDs, and other colors are organic micro LEDs. Different types of display panels can be fabricated. There can also be a wide variety of pixel sizes, ranging from sub-micron and below to 10 mm and above. The size of the overall display region can also vary widely, ranging from diagonals as small as tens of microns or less up to hundreds of inches or more (see abstract, and paragraph [0046]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention was made to modify the microdevices in the method as taught by Charisoulis with the method as taught by Zhang having the sizes of the two microdevices are different, and the material and structure of microdevices are different to form different operation characteristics, which is considered as an obvious matter of design choice based upon an actual design requirement so that the various designs of circuit may be satisfied.
Response to Arguments
Applicant’s arguments with respect to claims 1-19 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI N PHAM whose telephone number is (571)270-5518. The examiner can normally be reached M-F 9:00 am-5:00 pm.
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/Thai Pham/Primary Examiner, Art Unit 2844 01/14/2025